Application Of Fault Current Limiter Research Articles

계통연계형 PV(Photovoltaic) 설계 및 과도상태 특성 연구

This study investigated the design of a grid-connected photovoltaic (PV) system based on solar power generation and its characteristics during ground-fault incidents. Various approaches to enhance the stability and efficiency of the PV system were explored. Experimental results confirmed that the integration of solar arrays, DC/DC converters, and inverters optimized the output characteristics of the system. In particular, the analysis focused on current changes and control mechanisms during ground fault incidents and compared the effectiveness of DC circuit breakers and superconducting fault current limiters. Simulations were performed to propose solutions to address the problem of sudden increases in fault current. The results demonstrated the effectiveness of DC circuit breakers in limiting fault currents. Additionally, the application of fault current limiters improved both fault current limitation and response times for disconnection. The results of this study enhance the safety and economic operation of solar power systems and facilitate the adoption of eco-friendly energy. The results can be used as a reference for the design and operation of solar power systems in the future and can support the implementation of renewable energy policies.

A Comprehensive Review for Application of Fault Current Limiters in Power Systems

A Comprehensive Review for Application of Fault Current Limiters in Power Systems

Reduction of the DC Circuit Breaker Requirements by Bidirectional Solid-State Fault Current Limiter in DC Grid

Reliable and economic protection of DC grids against fault currents is the main challenge for the development of voltage source converter-based DC grids. Application of fault current limiters (FCLs) can limit the rapid increase of fault current and reduce the DC circuit breaker (DCCB) requirements to isolate the fault. This article reports a bidirectional solid-state FCL (BSSFCL) to protect the DC lines against DC short circuit fault. In addition, it can limit fault current in both directions. The circuit and principle operating of the proposed BSSFCL are presented. Then, the current limiting performance of the proposed BSSFCL is analyzed and its parameter design requirements are presented. Finally, the performance of the proposed BSFFCL is compared with that of the RL-current limiting circuit (RL-CLC), mutual inductance-type FCL (MIFCL), and restive mutual-inductance solid-state FCL (RMI-SSFCL). The numerical analysis and simulations were done using the PSCAD/EMTDC software. It was found that, the BSSFCL could effectively enhance the breaking capability of DCCBs. Moreover, it outperforms the RL-CLC, MIFCL, RMI-SSFCL in terms of the fault current limiting, the fault clearing time and metal oxide arrester (MOA) energy absorption of DCCBs.

Lamination process of second generation high temperature superconducting tape at Shanghai Superconductor Technology

As the second generation high temperature superconducting (HTS) tape enters the stage of commercialization and mass production, it has been successfully applied in several power and magnet devices. Different application scenarios also put forward different requirements for the electrical and mechanical properties of the HTS tape. This paper focuses on introducing the post-processing treatments of HTS tape, primarily copper plating and lamination. By preparing typical samples, the properties of copper-plated tapes and laminated tapes have been experimentally compared. The results show that under the condition of sufficient liquid nitrogen flow, the steady-state over-current tolerance of copper-laminated tape is significantly better than that of stainless steel-laminated and copper-plated tapes. At the same room temperature resistance, the over-current impact tolerance of stainless steel-laminated tape is 2–3 times that of copper-plated tape; the maximum transient current beared by the tapes reached 3896 A when they were put under shock for 8 ms, which has significant advantages in the application of resistive fault current limiter. At 77 K, yield strength Rp0.2 of the three types of superconducting tapes are > 1100 MPa for stainless steel-laminated tape, 645–1037 MPa for copper-plated tape and < 500 MPa for copper-laminated tape. The critical tensile stress of stainless steel laminated-tape is higher than that of copper-plated tape and copper-laminated tape. The tape reinforced structure described in this paper can provide a helpful reference for future design and manufacture of superconducting applications in power and magnet industries.

Progress on Second-Generation High-Temperature Superconductor Tape Targeting Resistive Fault Current Limiter Application

The resistive superconducting fault current limiter is well known for its simple structure and outstanding current-limiting effect, and it is broadly applied in power grid systems. The second-generation high-temperature superconductor (HTS) tape, of higher structural strength and greater room-temperature resistance, is well suited for application in resistive superconducting fault current limiters. The quenching caused by overcurrent in the HTS tape is a complexed coupling effect of several physical factors. The tape structure and properties directly impact the ultimate HTS tape’s quench performance. In this study, various SS316-laminated HTS tapes, of different critical currents, room-temperature resistances, and masses, were prepared. The pulse impact parameters of the various tape samples were measured using the RLC high-current impact test platform. By analyzing the resultant data, a quantitative assessment methodology to measure a tape’s tolerance toward impact was developed. The dependence of the HTS tape’s tolerance toward impact on its critical current, room-temperature resistance, and mass was studied. This provides numerical guidance on HTS material selection for resistive superconducting fault current limiters.

Study on the influencing factors to reduce the recovery time of superconducting tapes and coils for the DC superconducting fault current limiter applications

Superconducting fault current limiters (SFCLs) are important in improving the stability of electrical power systems. However, the existing resistive-type DC SFCL has a long recovery time, which cannot meet the requirements of power system auto-reclosure. Thus, it is necessary to investigate the methods of reducing recovery time of SFCLs. In the simulations on superconducting tapes, there is a lack of investigation about the effects of design factors of superconducting tapes and coils such as material, thickness, coil radius, coil winding method on recovery characteristics. The objective of this study is to obtain the effects of material and geometric properties of superconducting tapes and coils on recovery characteristics and obtain methods to reduce the recovery time. The recovery times under different conducting currents are also compared by simulations and experiments to verify simulation accuracy. The maximum error is below 40% and most of the cases have an error below 10%. Besides, by increasing tape thickness, the recovery time can be reduced by 22%. Tape materials and coil winding methods can be designed according to the auto-reclosure and current-limiting requirements of the power systems. The research provided directions for the design of superconducting tape and superconducting coil for resistive-type DC SFCLs.

Application of a resistive mutual-inductance fault current limiter in VSC-based HVDC system

The high DC fault current is a major challenge in voltage source converter (VSC)-based high voltage direct current (HVDC) systems. Direct-current circuit breakers (DCCBs) are used in these systems to protect the transmission lines against the DC fault current. However, they require large capacity and fast breaking speed to handle the DC fault current in VSC-based HVDC systems. Fault current limiters (FCLs) can be provide a reliable option to alleviate these issues. In this paper, a resistive mutual-inductance fault current limiter (RMFCL) is proposed to restrict the DC fault current in HVDC systems. It is based on the conventional mutual-inductance FCL that its power circuit is modified to reduce the DCCB requirements. The power circuit, principle operating and parameter design of the proposed RMFCL are presented. Then, the effectiveness of the proposed RMFCL is validated in a 3-terminal HVDC system in PSCAD/EMTDC system. Finally, its performance is compared with the parallel-resistor FCL (PRFCL), series-resistor FCL (SRFCL) and mutual-inductance FCL (MFCL). Comparative analysis demonstrates that the proposed RMFCL has superior performance in task of fault current amplitude, isolation time and energy absorption by the metal-oxide arrester (MOA) used in DCCB.

Experimental and Numerical Analysis of High-Temperature Superconducting Tapes Modified by Composite Thermal Stabilization Subjected to Thermomechanical Loading.

The strain behavior of SiC/Stycast 2850 FT composites under thermomechanical loading using a finite element analysis (FEA) was studied. These composites can serve as thermal stabilizers of high-temperature superconducting (HTS) tapes during limitation event in resistive superconducting fault current limiter (R-SCFCL) applications. For this purpose, the thermomechanical properties of four composite systems with different filler content were studied experimentally. The FEA was calculated using an ANSYS software and it delivered useful information about the strain distribution in the composite coating, as well as in particular layers of the modified HTS tapes. The tapes were subjected to bending over a 25 cm core, cooled in a liquid nitrogen (LN2) bath, and finally, quenched from this temperature to various temperatures up to 150 °C for a very short time, simulating real limitation conditions. The outputs from simulations were also correlated with the experiments. The most promising of all investigated systems was SB11-SiC20 composite in form of 100 µm thick coating, withstanding a temperature change from LN2 up to 120 °C.

Effect of the Conductor Length on the Hot-Spot Regime for Resistive-Type Superconducting Fault Current Limiter Applications

The design of the conductor of a resistive-type superconducting fault current limiter (R-SFCL) using the second generation of high-temperature superconductors (2G HTS) tapes is driven by two operation regimes. On one hand, when the quench occurs on the overall conductor (i.e., the limitation regime), it should withstand the highest possible electric field to reduce its length and make it cost-effective. On the other hand, it has also to cope with the hot-spot regime. Fault currents in the range of the critical current <b xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">I</b> <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"><b>c</b></sub> can lead to localized dissipation along the length of the conductor over the parts showing the lowest <b xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">I</b> <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"><b>c</b></sub> values. The almost nonlimitation of the current coming from the low normal zone propagation velocity of 2G HTS tapes causes temperature elevations in these zones, which highly threaten their integrity. To summarize, the conductor architecture is adapted to withstand a high electric field and to obtain a nondestructive value of the maximum temperature in a hot-spot regime. However, the <b xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">I</b> <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"><b>c</b></sub> variations, causing this last-mentioned regime, depend on the position along with the tape. This article aims to qualify the effect of a variable conductor length on the <b xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">I</b> <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"><b>c</b></sub> variations and, as a consequence, on the hot-spot regime. We first study the influence of the length on the <b xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">I</b> <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"><b>c</b></sub> variations. The minimum critical current tends to decrease when the conductor length increases. This behavior can be modeled by a Weibull distribution assuming a minimum critical current different from zero with an infinite length of the conductor. To assess this impact on the hot-spot regime, we develop a probabilistic approach using the deterministic one-dimensional modeling of 2G HTS conductor considering the <b xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">I</b> <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"><b>c</b></sub> inhomogeneity along its length to simulate a R-SFCL behavior. It appears that the more the conductor is long, the more the maximum temperature in the hot-spot regime is high. Moreover, the fact that two <b xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">I</b> <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"><b>c</b></sub> measurements corresponding to the same length of conductor present different maximum temperatures in hot-spot regime leads to present a method to design large-scale manufacturing conductors of the desired length, robust to survive hot-spot regime due to any <b xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">I</b> <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"><b>c</b></sub> variations.

Performance of Ratios‐Based Transformer Differential Protection Scheme in the Presence of Resistive Superconductor Fault Current Limiter

With the increased demand for electrical power, it is required to increase the number of power transformers in power systems. One of the main challenges facing protection engineers is the protection and isolation of power transformers in the shortest time possible, during internal faults. One of the alternative solutions to reduce the fault current in the power system is the application of a superconductor fault current limiter (SFCL). In this article, the ratios-based transformer differential protection algorithm is evaluated in the presence of resistive SFCL during internal fault conditions. A model of the system under study, including SFCL, is simulated and studies are performed in MATLAB/Simulink environment. The results demonstrate the capability of the ratios-based differential protection scheme to detect internal faults in the presence of SFCL.

Multi-resistor BFCL for FRT capability improvement of DFIG-based wind farm

Grid connection of wind farms (WFs) results in increment of short circuit level and decrement of fault ride-through (FRT) capability under fault conditions. Application of bridge-type fault current limiter (BFCL) was recognised as a promising and cost effective solution to cope with these problems. However, full resistor insertion of the conventional BFCL provides high transient overvoltage at the terminal of wind generator under low voltage sag condition, which can lead to failure operation of wind generator in despite of FRT requirement. This study presents a voltage adaptive multi-resistor BFCL (MRBFCL) to solve these problems for wide voltage sag levels. According to the depth of voltage sag level at the grid coupling point voltage, the MRBFCL inserts an appropriate combinational of resistors to compensate voltage sag level at acceptable level. To verify the efficiency of the proposed MRBFCL, time domain simulations were performed in PSCAD/EMTDC software under three different voltage sag levels. Also, the MRBFCL performance is compared with the conventional single-resistor BFCL. Simulation results reveal that the MRBFCL effectively enhance the FRT performance of doubly-fed induction generator (DFIG)-based WFs under wide range of voltage sag level and alleviate over voltage for low voltage sag conditions.

Sliding Mode Controller-Based BFCL for Fault Ride-Through Performance Enhancement of DFIG-Based Wind Turbines

The fault ride-through (FRT) capability and fault current issues are the main challenges in doubly fed induction generator- (DFIG-) based wind turbines (WTs). Application of the bridge-type fault current limiter (BFCL) was recognized as a promising solution to cope with these challenges. This paper proposes a nonlinear sliding mode controller (SMC) for the BFCL to enhance the FRT performance of the DFIG-based WT. This controller has robust performance in unpredicted voltage sag level and nonlinear features. Theoretical discussions, power circuit, and nonlinear control consideration of the SMC-based BFCL are conducted, and then, its performance is verified through time-domain simulations in the PSCAD/EMTDC environment. To reduce the chattering phenomenon and decrease the reaching time, it used the exponential reaching law (ERL) for designed SMC. Also, the SMC-based BFCL performance is compared with the conventional and PI controller-based BFCL for both symmetrical and asymmetrical short-circuit faults. Simulation results reveal that the SMC-based BFCL provides better performance compared with the conventional and PI controller-based BFCL to enhance the FRT.

Composite Heat Sink Material for Superconducting Tape in Fault Current Limiter Applications.

We enhanced the performance of superconducting tapes during quenching by coating the tapes with various composites, with regards to the application of such coated systems in superconducting fault current limiters. In composition of the coating, we varied the type of epoxy matrix, the content of ceramic filler particles and the use of reinforcement in order to optimize the thermal and the mechanical stability of the coated tapes. By this way modified superconducting tapes were able to reduce the maximum temperature 170 °C of not modified superconducting tape to 55 °C during the quench with electric field up to 130 V m−1.

Research Progress of Electromagnetic Properties of MgB2 Induced by Carbon-Containing Materials Addition and Process Techniques

For the high transition temperature (Tc) and low cost taking both raw materials and fabrication process into account, MgB2 has been a competitive candidate to replace the conventional NiTi superconductor for high-temperature application in fault current limiters, transformers, motors, magnetic resonance imaging, adiabatic demagnetization refrigerators, generators, etc. The carbon-containing materials addition induced high critical current density (Jc) is reviewed based on their influences on the upper critical field (Hc2), flux pinning force, and connectivity. The doping effects were compared in the overview focusing on SiC, organic dopants, and graphene-related dopants. SiC doping is featured for the high-field critical current density, which is caused by the increased Hc2 attributed to the substitution of carbon on boron site and the strong flux pinning force offered by the nanosized secondary phases in the MgB2 matrix. Organic dopants have the advantage over SiC dopant for their relatively homogeneous distribution in the MgB2 matrix based on wet mixing of the organics and the raw boron powders. Low doping level of two-dimensional materials can improve the superconducting properties in all measured fields because of the combined advantages of carbon substitution effect and grain connectivity. MgB2 fabricated with carbon-encapsulated boron also introduces strong flux pinning centers in MgB2, which show weak destruction of the connectivity of the MgB2 grains as reflected by the low-magnetic-supercurrent behavior. High-pressure treatment and diffusion method can fabricate high-density MgB2 superconductors with better connectivity and increase the Jc compared with the in situ and ex situ methods.

Study of Turn-to-Turn Electrical Breakdown for Superconducting Fault Current Limiter Applications

The rational insulation design of a resistive superconducting fault current limiter (r-SCFCL) requires data gathered from experimental setups representative of the final apparatus. Therefore, an experimental study was performed to characterize the electrical breakdown (BD) of liquid nitrogen in the particular conditions of a quenching superconducting device. To reproduce the electrical stress occurring within a real r-SCFCL winding, BD voltages with a grounded tape electrode were investigated with different polarities and pressures, with and without transient heating on the tape electrode. Pictures obtained with a high-speed camera and breakdown delay measurements allow to further characterize breakdown mechanisms.

Superconducting Fault Current Limiter Application for Induction Motor Starting Current Reduction

Superconducting fault current limiters (SFCLs) have significant advantages compared with conventional methods of fault current limiting and therefore have been applied to transmission and distribution systems in recent decades. Besides limiting fault currents, SFCLs can also be used to reduce induction motor starting currents. The major purposes for reducing motor starting currents are to alleviate power system voltage sags and to decrease motor winding heating. Traditionally, induction motor starting currents are decreased by applying reduced voltages using autotransformers, wye-delta starters, or series reactors. However, to ensure motor performance in steady-state operation, a step-by-step control scheme needs to be carefully implemented to disconnect the auxiliary devices from the circuit once the startup transient dies out. These approaches are not useful for reducing inrush currents when the circuit is reenergized upon reclosing after clearing a fault on a neighboring feeder. In this paper, we propose a scheme to reduce induction motor starting currents using SFCL, which has a less complex structure and provides more implementation flexibility than traditional methods. A detailed simulation model of the system with a power source, SFCL, induction motor, and a load is established in MATLAB-Simulink. The results demonstrate the validity and effectiveness of the proposed scheme.

Application of resistive super conductor fault current limiter for protection of grid-connected DGs

Penetration of Distributed Generation (DG) into the power system causes technical problems and bad effects on the safety of the system due to increasing the short circuit levels in transmission and distribution networks. So, there will be miscoordination problems of directional over current relays (DOCR) when DGs are integrated with looped power delivery systems. This paper presents a new approach of implementing resistive superconducting fault current limiters (SFCL) with DG units to obtain optimal setting of protection system. The protection coordination setting is optimized using particle swarm optimization (PSO) technique. The proposed algorithm is tested on nine-bus looped power distribution system and the effects of SFCL on protection system of DG-grid connected are analyze. Three cases are studied: no DG, grid-connected DGs with SFCL and grid-connected DGs without SFCL. Several simulations are implemented for different locations of fault.

Transport AC Loss Measurements in Bifilar Stacks Composed of YBCO-Coated Conductors

Increasing the current-carrying capacity of bifilar coils is essential for the high-temperature superconducting (HTS) fault current limiter (FCL) application. We built three bifilar stacks with two, four, and six conductors using 4 mm wide stabilized SuperPower YBCO wires to investigate ac loss dependence of the bifilar stacks on the number of conductors. In the three basic configurations, the upper half conductors carry current in one direction, and the lower half conductors carry current in the opposite direction. We report transport ac loss results on these stacks measured at three different frequencies. The measured loss values were compared with those in stacks with the same conductor number and geometry but producing different degrees of field cancellation. We also explored the dependence of ac loss on a central gap in bifilar stacks composed of four and six conductors and the results were compared with the numerical results obtained from a two-dimensional FEM model. Results show that the bifilar stacks where each turn is stacked with multiple wires is a promising option which compromise both high current-carrying capacity and lower ac loss for HTS FCL application.

Feasible Application Study of Several Types of Superconducting Fault Current Limiters in HVDC Grids

The eventual goal of high-voltage direct-voltage (HVDC) systems is to implement HVDC grids. One of the key obstacles in realization of the HVDC grid is the absence of a dc circuit breaker (DCCB). Several prototypes of DCCBs for the HVDC grid have been proposed, but no commercial solution has been developed yet due to insufficient dc fault current breaking capabilities and an unreliable protection-coordination scheme. In this respect, application of the suitable fault current limiter is necessary, and the use of a superconducting fault current limiter (SFCL), which has already been developed for the ac grid, is a viable solution, but there is no fundamental research about performance evaluation of SFCLs for the dc grid. Therefore, we aim to verify the applicability of the conventional SFCL in HVDC grids and perform a comparative analysis of the performance of several types of SFCLs. To analyze the performance of the conventional SFCL in the HVDC grid, three well-known representative types of SFCLs are modeled in MATLAB/Simulink, and their current limiting and recovery characteristics and energy dissipation are examined in voltage-source converter HVDC system application. From the simulation results, we deduced the strengths and the weakness of different types of SFCLs. Consequently, the likely SFCL candidate for commercialization in dc grid applications is suggested.

A Novel Three-Phase Compact Saturated-Core Fault Current Limiter

The application of fault current limiter is an effective method to limit fault current. The saturated-core fault current limiter (SFCL) is one of the promising devices. However, its commercialization is limited by the high demands for the ferromagnetic material and the dc source generating magneto motive force. This paper proposes a novel three-phase compact SFCL (CSFCL) in which a common core and a permanent magnet are used to solve the mentioned challenges. The common core can significantly reduce the amount of required ferromagnetic material. The basic operating principle of CSFCL is introduced based on the analysis of the CSFCL’s magnetic circuit and equivalent electrical circuit. Finite-element analysis (FEA) simulations were performed by ANSOFT to validate the effectiveness of the CSFCL’s fault clipping performance.