Fast Clock Research Articles

Dutch auction dynamics in non-fungible token (NFT) markets

Non-fungible tokens (NFTs) rose to prominence as a wide-scale implementation of blockchain technology to support the emergence of crypto-asset markets. These nascent digital markets raise questions about the behaviours of investors in the digital economy and their appetite for risk. Using 28,919 auction listings, 4937 sales, and 30,197 Telegram messages, we conduct a field study on the bidding and selling behaviours of NFT investors in a Dutch auction system. We reveal risk-seeking behaviours in our sample of Dutch auction sales. We document that time pressures and value propositions significantly influence NFT investors: fast clock speeds and greater price separations induce underbidding behaviours and are associated with low value retention for sellers. These results are confirmed using a matched-pairs analysis. Our study raises further questions on the risk preferences of investors in emergent digital marketplaces. We propose value maximisation strategies for marketplace developers and participants, while drawing attention to the presence of potentially exploitable biases and heuristics amongst participants, courtesy of bidding incentivisation schemes significantly altering how investors value NFTs.

Life in the fast lane: the role of temporal processing in risk-taking behaviors

An existing theoretical framework proposes that aberrant temporal processing and a fast internal clock, denoted by overestimation and under-reproduction of time, increases the likelihood of engagement in risky behaviors (ERB). The primary aim of this project was to improve our understanding of the relationship between temporal processing and ERB in college students. The present study used the Wittmann and Paulus (2008) theoretical framework to examine the associations between temporal processing and ERB in college students. College student participants (N = 215) completed self-report measures of ERB, delay aversion, inhibitory control, ADHD symptoms and objective cognitive time estimation and time reproduction tasks. Time estimation accuracy was significantly associated with lower engagement in sexual risk behaviors (OR = .988; 95% CI: .979, .996; p = .006) and aggressive behaviors (OR = .989; 95% CI: .980, .998; p = .018). Time reproduction was not significantly associated with ERB. The present study established preliminary support for the associations between aberrant temporal processing, namely aberrant time estimation, and ERB among college students.

The feeling of the passage of time against the time of the external clock

When people say that time is passing faster or slower, they are referring to the clock time. What exactly is the role of this reference to clock time in the awareness of the passage of time? Three experiments were conducted to examine this question. In Experiment 1, participants performed an easy and a difficult task in a condition with or without an external clock. In Experiment 2, the external clock was introduced after several trials of the easy task performed by the same participants. In Experiment 3, the speed of the clock hands was manipulated. Eye movements towards the clock were recorded by an eye tracker. The results showed that time was judged to pass faster with the external clock, thus reducing the distortion of the sense of time. Indeed, participants noticed that time passed faster than they initially thought. However, our results also showed that this was an occasional and short-lived adjustment of subjective time to objective time, with a greater acceleration in the presence of the fast clock. Indeed, the clock quickly lost its effect after a few trials, the feeling of the passage remaining based on the emotion felt, i.e., the boredom felt in the easy task. Our experiments thus showed that the feeling of the passage of time is primarily grounded in the emotional affect experienced (Embodiment), and that knowledge of clock time had only a small and transient corrective effect.

A Fast Lock-In Time, Capacitive FIR-Filter-Based Clock Multiplier with Input Clock Jitter Reduction

This paper presents a fast lock-in time clock frequency multiplier without using traditional clock generation circuits such as PLLs and DLLs. We propose a novel technique based on capacitive finite impulse response (FIR) filters to generate clock phases while reducing the input clock phase noise at the same time. A new delay line circuit is also proposed for improving power supply rejection. In addition, to improve the matching quality as well as the end-effects tolerance of the on-chip capacitors, a single-value series/parallel algorithm is proposed. Designed in a 0.18 μm digital CMOS process, with a 20 MHz input clock frequency, the multiplier achieves a multiplication factor of 5 with a lock-in time of less than 4 clock cycles. The input clock jitter is reduced from 7ns RMS to 153 ps RMS after frequency multiplication.

Automated, adaptive, fast reset circuit for wide-energy range detector front-end

In this article, we present a front-end amplifier that is equipped with a precise, fast, and automated reset circuit responsible for two actions: restoring the charge-sensitive amplifier output voltage from a pulse level to baseline, and the analog-to-digital conversion of the pulse amplitude. Importantly, the circuit is self-clocking, which allows to take advantage of the modern submicrometer CMOS process, and thus speed-up the reset and conversion phases. Thanks to the proposed approach, the fast clock signal distribution and an independent analog-to-digital converter per channel are not required, saving both the power consumption and the silicon area. The presented circuitry was adopted into 100-pixel-shaped recording channels and sent for fabrication in the CMOS 28 nm process.

Efficient and Accurate Optical Signal Processing and Digitization System for High Speed Data Acquisition and Analysis

The evolution of optical fiber technology has expanded its utility beyond communication to encompass measurement. Key components include the light source, detection elements, and processing circuits. This paper describes a system for optical signal processing and digitization of light pulses, employing advanced components to enhance data acquisition and analysis performance. The optical signal processing phase employed the LF356N operational amplifier, offering attributes like low bias current, high bandwidth, and rapid settling time. Configured as a transimpedance amplifier, the opamp transformed light signals into corresponding analog voltage signals. Subsequently, the voltage signal underwent digitization using the AD976AN, a 16-bit ADC with advanced features such as high-speed data acquisition and an integrated clock. This ADC was controlled by a Teesny 3.6 board with a fast CPU clock speed of up to 256 MHz, greatly facilitating rapid data analysis and algorithm execution. The hardware circuit underwent meticulous design, simulation, and fabrication, followed by rigorous testing involving various distinct light sources with differing parameters. The digitized and computed parameter values (obtained after subjecting the ADC outputs to the suggested algorithm) exhibited a high degree of similarity in comparison to the observed values on the oscillo-scope.

An Energy-Efficient SIFT Based Feature Extraction Accelerator for High Frame-Rate Video Applications

Visual feature extraction is a key technology of computer vision for intelligent video processing. Efficient feature extraction is a fundamental problem in computer vision applications. Scale-Invariant Feature Transform (SIFT) is one of the most popular feature extraction algorithms because SIFT features are invariant to image scale and rotation and robust to changes in illumination and noise. However, SIFT is a computationally-intensive and power-hungry algorithm, which needs to be accelerated by efficient hardware design to achieve both high-speed feature extraction and high energy efficiency for many high frame-rate video applications at Artificial-intelligent Internet of Things edges. In this work, an energy-efficient SIFT based feature extraction accelerator is proposed. In the Gaussian pyramid and Differences of Gaussian (DoG) pyramid construction process, three design methods are proposed to reduce power consumption and improve information fidelity: a fast and slow dual clock domain design method with a reconfigurable design strategy is proposed to reduce the computation resources; a partial sum reuse design method is proposed to further reduce the computation resources and the amount of computation; a dynamic padding design method is proposed to solve the problem of information loss at image edges and corners after convolution operation. In the keypoint descriptor generation process, an optimized algorithm using circular region and polar coordinates is proposed to parallelize the main orientation assignment and descriptor generation to achieve high-speed processing, while maintaining a comparable matching accuracy with the state-of-the-art designs. The experiment results show that the proposed SIFT hardware accelerator is able to extract features by up to 162 frames per second ( <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">$640\times 480$ </tex-math></inline-formula> pixels) under 100 MHz, with the power consumption of 364.26 mW and energy efficiency of 2.25 mJ/frame based on 180 nm technology, which is suitable for many high frame-rate AIoT applications including autonomous driving cars and unmanned aerial vehicles.

Massively parallel probabilistic computing with sparse Ising machines

Solving computationally hard problems using conventional computing architectures is often slow and energetically inefficient. Quantum computing may help with these challenges, but it is still in the early stages of development. A quantum-inspired alternative is to build domain-specific architectures with classical hardware. Here we report a sparse Ising machine that achieves massive parallelism where the flips per second—the key figure of merit—scales linearly with the number of probabilistic bits. Our sparse Ising machine architecture, prototyped on a field-programmable gate array, is up to six orders of magnitude faster than standard Gibbs sampling on a central processing unit, and offers 5–18 times improvements in sampling speed compared with approaches based on tensor processing units and graphics processing units. Our sparse Ising machine can reliably factor semi-primes up to 32 bits and it outperforms competition-winning Boolean satisfiability solvers in approximate optimization. Moreover, our architecture can find the correct ground state, even when inexact sampling is made with faster clocks. Our problem encoding and sparsification techniques could be applied to other classical and quantum Ising machines, and our architecture could potentially be scaled to 1,000,000 or more p-bits using analogue silicon or nanodevice technologies. Sparsification techniques can be used to create Ising machines prototyped on field-programmable gate arrays that can quickly and efficiently solve combinatorial optimization problems.

A 16-Bit Parallel Prefix Carry Look-Ahead Kogge-Stone Adder Implemented in Adiabatic Quantum-Flux-Parametron Logic

Extremely energy-efficient logic devices are required for future low-power high-performance computing systems. Superconductor electronic technology has a number of energy-efficient logic families. Among them is the adiabatic quantum-flux-parametron (AQFP) logic family, which adiabatically switches the quantum-flux-parametron (QFP) circuit when it is excited by an AC power-clock. When compared to state-of-the-art CMOS technology, AQFP logic circuits have the advantage of relatively fast clock rates (5 GHz to 10 GHz) and 5 - 6 orders of magnitude reduction in energy before cooling overhead. We have been developing extremely energy-efficient computing processor components using the AQFP. The adder is the most basic computational unit and is important in the development of a processor. In this work, we designed and measured a 16-bit parallel prefix carry look-ahead Kogge-Stone adder (KSA). We fabricated the circuit using the AIST 10 kA/cm2 High-speed STandard Process (HSTP). Due to a malfunction in the measurement system, we were not able to confirm the complete operation of the circuit at the low frequency of 100 kHz in liquid He, but we confirmed that the outputs that we did observe are correct for two types of tests: (1) critical tests and (2) 110 random input tests in total. The operation margin of the circuit is wide, and we did not observe any calculation errors during measurement.

Flow-Controlled and Clock-Distributed Optical Switch and Control System

Switching the traffic in the optical domain has been considerably investigated as a future-proof solution to overcome the intrinsic bandwidth bottleneck of electrical switches in data center networks (DCNs). However, due to the lack of fast and scalable optical switch control mechanism, the lack of optical buffers for contention resolution, and the complicated implementation of fast clock and data recovery (CDR), the practical deployment of fast optical switches in data centers (DCs) remains a big challenge. In this work, we develop and experimentally demonstrate for the first time a flow-controlled and clock-distributed optical switch and control system, implementing 43.4 ns optical switch configuration time, less than 3.0E-10 packet loss rate resulting from the packet contention, and 3.1 ns fast CDR time. Experimental results confirm that zero buffer overflow caused packet loss and lower than <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">$3~ \boldsymbol {\mu }\text{s}$ </tex-math></inline-formula> server-to-server latency are achieved for network deploying a smaller electrical buffer of 8192 bytes at a traffic load of 0.5. Real servers running the Transmission Control Protocol (TCP) traffic generating and monitoring tools are exploited in this switch and control system as well, validating its capability of running practical DCNs services and applications with full TCP bandwidth.

Clock-Latency-Aware Pre-CTS for better Timing Closure in VLSI Design

A common strategy for reducing the time jump due to a clock tree insertion is to add a clock uncertainty value. If a small clock uncertainty value is selected for the Pre-CTS optimization, then a significant timing jump is observed when the clock tree is inserted, and clock timings are propagated. On the other hand, if the clock uncertainty is large, then the place and route (PNR) flow does not converge. This approach has been proven to be insufficient as each timing path is affected differently by the creation of the clock tree. In this paper, we suggest a more targeted approach whereby all pins in the clock tree will be annotated with their estimated latency, and therefore clock arrival times under ideal clocks should closely model the post-CTS arrival times. This objective is achieved by introducing an accurate and fast clock prediction early in the flow at the pre-CTS stage. As a result, the transition from the pre-CTS stage to the post-CTS stage becomes easier without significant timing jumps. An experiment on nine commercial test cases led to a significant TNS timing improvement of up to 68%, with an average of 35% at the end of the route stage. The full PNR flow runtime is not impacted. We achieved a 3% average runtime reduction over all test cases. Keywords—Clock-latency estimation, Clock-tree Synthesis, Integrated circuit conception, Physical implementation, Static timing analysis, Static timing closure.

Switched-Capacitor Bandgap Voltage Reference for IoT Applications

This paper presents a switched-capacitor network (SCN) based bandgap voltage reference (BGR) for IoT applications. The proposed BGR employs a dual proportional-to-absolute-temperature (PTAT) clock topology to achieve both high precision and low power over a wide temperature range while relaxing the capacitor size requirements. Specifically, the fast PTAT clock assists in reducing the output voltage ripple of the dual-branch interleaved <inline-formula> <tex-math notation="LaTeX">$2\times $ </tex-math></inline-formula> charge pump (CP). Meanwhile, the slow PTAT clock controls the voltage divider SCN to relax the settling error at low temperature and the leakage-induced error at high temperature simultaneously, resulting in lower power consumption and smaller temperature coefficient (TC). We also propose a replica <inline-formula> <tex-math notation="LaTeX">$V_{\mathrm {EB}}$ </tex-math></inline-formula> generation branch in the series-parallel SCN to improve the BGR output TC due to the finite settling time during switching. Fabricated in 65nm standard CMOS, measurement results show that the proposed BGR obtains a TC of 32 ppm/&#x00B0;C at 0.5V supply within &#x2212;40 &#x00B0;C to 120 &#x00B0;C. The line regulation is 3.3mV/V or 0.66&#x0025;/V from 0.5V to 1V. Based on 10-chip measurement results, we obtain a <inline-formula> <tex-math notation="LaTeX">$3\sigma / \mu $ </tex-math></inline-formula> variation of 1.37&#x0025; before trimming, while 0.25&#x0025; after applying one-point trimming at 20&#x00B0;C.

Expected Constant Time Self-Stabilizing Byzantine Pulse Resynchronization

In extending fast digital clock synchronization to the bounded-delay model, the expected constant time Byzantine pulse resynchronization problem is investigated. In this problem, the synchronized state of the system should not only be deterministically maintained but be reached from arbitrary states with expected constant time in the presence of Byzantine faults. An intuitive geometric representation of the problem is introduced, with which the classical approximate agreement, randomized Byzantine agreement, and random walk are integrated with some geometric operations. Efficient realizations are also provided for practical uses. Compared with the state-of-the-art solutions, the assumed common pulses need not be regularly generated, the message complexity can be lowered as approximate agreement, and the expected stabilization time is optimal. With this, the provided solution can efficiently convert irregularly generated common pulses to self-stabilizing Byzantine pulse synchronization.

Radarski sistem za praćenje ciljeva velikih brzina zasnovan na upotrebi BPSK signala i digitalnoj kompenzaciji doplerovog pomaka

Introduction/purpose: This paper presents a model of a high speed target radar tracking system that is much simpler than the existing ones. The Doppler shift is compensated before signal compression, simultaneously with the modification of the clock signal in the compression filter. This is possible thanks to the development of FPGA technology. The most important for this application are very fast clock control units which enable operation with different frequency references up to 1 GHz with an accuracy far below 1 Hz. Methods: In this paper, the methodology of mathematical modeling and simulation is used. Results: The results of the analysis of the most important effects in radars caused by high-speed targets are presented and discussed - target migration through resolution cells and compression filter response distortion due to high target acceleration. Conclusion: Thanks to flexible RF and signal processing hardware, complex radar processing procedures are not required. The sensitivity of the BPSK signal to the Doppler shift (which is usually considered a disadvantage) can be used to reject targets at a slightly different rate. This system can be used in space debris tracking, airspace target tracking, car driving, etc.

HTNURL: Design of a High-Performance Low-Cost Triple-Node Upset Self-Recoverable Latch

A high-performance and low power consumption triple-node upset self-recoverable latch (HTNURL) is proposed. It can effectively tolerate single-node upset (SNU), double-node upset (DNU), and triple-node upset (TNU). This latch uses the C-element to construct a feedback loop, which reduces the delay and power consumption by fast path and clock gating techniques. Compared with the TNU-recoverable latches, HTNURL has a lower delay, reduced power consumption, and full self-recoverability. The delay, power consumption, area overhead, and area-power-delay product (APDP) of the HTNURL is reduced by 33.87%, 63.34%, 21.13%, and 81.71% on average.

Examining the effect of Libet clock stimulus parameters on temporal binding

Temporal binding refers to the subjective temporal compression between actions and their outcomes. It is widely used as an implicit measure of sense of agency, that is, the experience of controlling our actions and their consequences. One of the most common measures of temporal binding is the paradigm developed by Haggard, Clark and Kalogeras (2002) based on the Libet clock stimulus. Although widely used, it is not clear how sensitive the temporal binding effect is to the parameters of the clock stimulus. Here, we present five experiments examining the effects of clock speed, number of clock markings and length of the clock hand on binding. Our results show that the magnitude of temporal binding increases with faster clock speeds, whereas clock markings and clock hand length do not significantly influence temporal binding. We discuss the implications of these results.

Antimicrobial properties of silver nanoparticles prepared by Acacia etbaica (Schweinf.) valve extract

Here, we employed green and very fast (clock) synthesis of silver nanoparticles (AgNPs) by means of silver nitrate and Acacia etbaica valve extract at room temperature. Transmission electron microscopy (TEM) results confirm the spherical shape and diameter (size) ranging from 6.38 ± 3.21, 10.09 ± 3.21 and 20 ± 3.21 for AeAg-1, AeAg-2 and AeAg-3, respectively. TEM results showed that size of AgNPs increase as the concentration of AgNO3 decreases due to the low concentration of bio reducing agent present in the extract. The enhanced antimicrobial activity against human pathogenic microbes was investigated by diffusion method based on zone of inhibition. The prepared AgNPs showed high specificity against the tested pathogens, namely K. pneumonia, S. typhi, S. dysenteriae, P. mirabilis, S. saprophyticus, S. aureus and C. albican with inhibition zone between 22.3 ± 2.08 mm and 11.67 ± 1.15 mm. On the other hand, the prepared AgNPs did not exhibit high specifity against E. Faecalis and P. aeruginosa. Therefore, it can be concluded that the prepared AgNPs have potential as natural antimicrobial agents against microbes with multidrug resistance.

The Demonstration of S2P (Serial-to-Parallel) Converter with Address Allocation Method Using 28 nm CMOS Technology

To improve the performance of analog, RF, and digital integrated circuits, the cutting-edge advanced CMOS technology has been widely utilized. We successfully designed and implemented a high-speed and low-power serial-to-parallel (S2P) converter for 5G applications based on the 28 nm CMOS technology. It can update data easily and quickly using the proposed address allocation method. To verify the performances, an embedded system (NI-FPGA) for fast clock generation on the evaluation board level was also used. The proposed S2P converter circuit shows extremely low power consumption of 28.1 uW at 0.91 V with a core die area of 60 × 60 μm2 and operates successfully over a wide clock frequency range from 5 M to 40 MHz.

Pipeline FPGA-Based Implementations of ANNs for the Prediction of up to 600-Steps-Ahead of Chaotic Time Series

Chaotic time series prediction can be performed by applying different architectures of artificial neural networks (ANNs) that can be implemented on field-programmable gate arrays (FPGAs). However, the main challenges are the reduction of hardware resources to develop faster ANNs and the prediction capabilities for large horizons. In this manner, the contribution is devoted to introduce pipeline architectures in which some registers are placed between combinational blocks to divide the logic into shorter stages that can run with a faster clock. The cases of study are the multilayer perceptron (MLP), nonlinear autoregressive with exogenous input (NARX), and echo state network (ESN). In addition, another contribution is devoted to introduce the application of the decimation technique to extend the prediction horizon of the ANNs from 12 to 600-steps-ahead. The prediction capabilities of the MLP, NARX and ESN are compared by using eight chaotic time series with different maximum Lyapunov exponents. The pipeline FPGA-based implementations show that the ESN with a reservoir of at least 30 neurons guarantees a large prediction horizon of 600-steps-ahead. Another important advantage of the ESN is that its FPGA-based implementation can be performed by reusing one neuron, thus requiring the lowest quantity of hardware resources.

Boosting working memory with accelerated clocks

Our perception of time varies with the degree of cognitive engagement in tasks. The perceived passage of time accelerates while working on demanding tasks, whereas time appears to drag during boring situations. Our experiment aimed at investigating whether this relationship is mutual: Can manipulated announcements of elapsed time systematically affect the attentional resources applied to a cognitive task? We measured behavioral performance and the EEG in a whole report working memory paradigm with six items of different colors that each had to be reported after a short delay period. The 32 participants were informed about the current time after each 20 trials, while the clock was running at either 100% (normal), 120% (fast), or 80% (slow) of normal clock speed depending on the experimental block. The mean number of correctly reported colors per trial was significantly increased in the fast as compared to the slow and normal clock conditions. In the EEG, we focused on neural oscillations during working memory encoding and storage. As an electrophysiological correlate of task engagement, frontal theta power during the storage interval was increased in the fast clock condition. Also, the power of frontal theta oscillations predicted the number of correctly reported colors on a single-trial basis. This shows that a covert manipulation of clock speed can lead to an improvement in cognitive performance, presumably mediated by a higher allocation of attentional resources resulting from an adaptation of the subjective passage of time during an experiment.