Abstract

A high-performance and low power consumption triple-node upset self-recoverable latch (HTNURL) is proposed. It can effectively tolerate single-node upset (SNU), double-node upset (DNU), and triple-node upset (TNU). This latch uses the C-element to construct a feedback loop, which reduces the delay and power consumption by fast path and clock gating techniques. Compared with the TNU-recoverable latches, HTNURL has a lower delay, reduced power consumption, and full self-recoverability. The delay, power consumption, area overhead, and area-power-delay product (APDP) of the HTNURL is reduced by 33.87%, 63.34%, 21.13%, and 81.71% on average.

Highlights

  • With the semiconductor technology scaling down continuously, higher integration and lower power integrated circuits (ICs) have been successfully developed

  • Compared with the typical triple-node upset (TNU)-recoverable latches, the HTNURL proposed in this paper decreases the delay by 69.54%, the power consumption by 30.90%, the area overhead by 3.60%, and the area-power-delay product (APDP) by 88.60%

  • Direct ionization is caused by the incident particle, while indirect ionization is caused by secondary particles created by nuclear reactions between the particle and the device

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Summary

Introduction

With the semiconductor technology scaling down continuously, higher integration and lower power integrated circuits (ICs) have been successfully developed. In the high-density ICs, owing to charge sharing, high-energy particle strike may alter the logic values of double/triple nodes at the same time, resulting in a double-node upset (DNU) or even a triple-node upset (TNU) [4]. Because of latches’ problems mentioned above, we designed a high-performance and low-power latch which is TNU self-recoverable. This latch comprises four series of C-element modules, each consisting of four two-input C-elements. Compared with the typical TNU-recoverable latches, the HTNURL proposed in this paper decreases the delay by 69.54%, the power consumption by 30.90%, the area overhead by 3.60%, and the APDP by 88.60%.

Typical Radiation Hardened Designs
LCHRNAN
Delta DICE
LCTNURL
Verification Results
Effect of PVT Variations on Latches
Conclusion and Future Work

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