Fast Chip Research Articles

Addendum: A graph placement methodology for fast chip design.

Addendum: A graph placement methodology for fast chip design.

Noise coupling reduction using temperature enhanced device for future integrated circuit integration applications

<p>Information technology-to-internet of things may have succeeded because of fast silicon chip capability expansion. Moore's law, which reduces device size, boosted integrated circuit (IC) performance. Delay rises with highdensity connection parasitic capacitance. Interconnect delays have surpassed transistor delays and slowed progress. An alternative is required now to reduce connection latency. The third dimension is used in popular 3D IC technology IC technology requires through silicon via (TSV) for signal integrity and heat mitigation. Noise coupling hinders electrical communication between signal-carrying TSVs (aggressive TSVs) and ground TSVs (victim TSVs), a 3D IC bottleneck. TSVs must be dielectrically insulated from Si substrates to avoid electrical signal interference. Additionally, first-order modelling will confirm the suggestions. This article proposes using the nanosheet field effect transistor (NSFET) to overcome 3D IC noise coupling and complementary metal oxide semiconductor (CMOS) technology nodes. After discussing the electronic industry and sub nm, several basic metrics and criteria for developing electronic components are presented. The first technique uses Perylene-N's exceptional noise-cancelling characteristics. Second technique uses electrical TSV (ETSV), thermal TSV (TTSV), and heat source models to measure noise coupling on numerous ICs. The third proposes many noise-reducing materials. The suggested structures outperform traditional approaches.</p>

Effect of the nutrition violation on the of development of functional gastrointestinal disorders in school-age children

Nutrition is one of the important risk factors for the occurrence of functional gastrointestinal disorders in children (FGID).
 Objective — to study the nutrition violations in children with FGID.
 Materials and methods. Observation involved 110 children with FGID aged 6 to 18 years. The patients were divided into two groups: I study group included 44 children with an overlap of functions dyspepsia (FD) and irritable bowel syndrome (IBS). The II study group consisted of 66 pediatric patients with FD. The control group consisted of 30 healthy children. The diagnosis of functional dyspepsia and IBS was established based on the clinical symptoms according to the Rome IV criteria (2016). To detect violations in the nutritional regimen and food preferences of schoolchildren, a questionnaire survey was performed with the use of the Youth Adolescent Food Frequency Questionnaire, adapted to the model of children’s nutrition in Ukraine.
 Results. The frequency of violations in the nutritional regimen, such as refusal of breakfast or a full lunch at school, reducing the daily frequency of meals, was higher in children with FGID than in healthy children. The violations of nutrition in children with overlapping FD and IBS was observed more often than in children with FD. The frequency of consumption of vegetables, cereals and grains was lower in children with FGID, and the consumption of meat, sausages and confectionery, fast food, chips, nuts and seeds, energetics and sweet carbonated beverages was higher than in healthy children. In children with overlapping FD and IBS, the frequency of consumption of vegetables, cereals and grains is lower, and the consumption of confectionery, fast food, energetics, and sweet carbonated drinks was higher than in children with FD.
 Conclusions. Violations of the regimen and quality of nutrition is a risk factor for the formation of FGIR in children and should be considered in the treatment.

NTIMP1—A Fast Pulse Readout Chip With 1.2 V Power Supply Applied to the Diamond Detector in HIAF

A very fast pulse readout ASIC, NTIMP1, with 1.2 V power supply is presented in this work. It is going to be used as front-end electronics (FEE) for reading out the diamond detector signals in the TOF (Time of Flight) wall of RIBLL2 experiment of the High Intensity Heavy Ion Accelerator Facility (HIAF), China. So that an 8-channel fast front-edge readout chip named as NTIMP1 is proposed in this work. Each channel of NTIMP1 has a high-bandwidth preamplifier (with adjustable thresholds) dealing with differential current input, a fast hysteresis discriminator, and a LVDS (Low-Voltage Differential Signaling) module ensuring long-distance signal transmission. Fabricated with 0.13 μm standard CMOS Technology, NTIMP1 can get an input ranging from 2 fC to 2000 fC and the input impedance of the preamplifier can be adjusted externally with an off-chip resistor, so as to match with the electrode impedance of diamond detector. The bandwidth of the preamplifier is 495.5 MHz, which allows a very short signal peaking time of no more than 1 ns. The jitter of the leading edge is lower than 15 ps with 100 fC input charge suggesting that NTIMP1 is suitable for high-resolution TOF measurement as well as time-slewing correction.

A temperature-insensitive process corner detection circuit based on self-timing ring oscillator

A process corner detection circuit based on a self-timing ring oscillator is proposed to identify on-chip process variations. Composed of a self-timing ring oscillator with 5 stages of C-element, a counting module and a reset module, it is able to distinguish slow, typical and fast dies. Implemented in a 40 nm CMOS process with 1.2 V supply and 100 MHz frequency, it has a small area of 436 μm2 with 0.18 mW power consumption. Implemented in the foundry's test circuit and tested with probe card in foundry, the measured results show that it can distinguish slow, typical and fast chips with no overlaps between the counting results under different temperatures of −25, 25, 75 and 125 °C. It is advantageous in its insensitivity to temperature for on-chip process corner detection.

Immunofluorescence analysis of breast cancer biomarkers using antibody-conjugated microbeads embedded in a microfluidic-based liquid biopsy chip

Early and precise detection of tumors could lead to more effective treatments. Microfluidic technology holds great promise as an emerging tool for the early diagnosis of cancer. However, since the flow in microchannels is usually laminar, the mass transfer efficiency is low, resulting in low biosensing efficiency and sensitivity. In this paper, we employed immunofluorescence analysis in a microfluidic chip to develop a continuous, fast and efficient liquid biopsy chip. We disrupt the laminar flow and improve mass transfer efficiency by filling the chip with antibody-conjugated microbeads. Meanwhile, the microbeads increased the contact area of the immunoaffinity reaction, which greatly enhanced the binding of the antibody to the target protein, amplified the fluorescent signal, and significantly improved the sensitivity and efficiency of detection. This microfluidics-based liquid biopsy device required only a small volume of plasma sample (20–50 μL), realized a low limit of detection (LOD, 0.1 ng/mL), and can detect biomarkers within 55–75 min. We tested plasma from 15 breast cancer (BC) patients and 5 non-cancer controls to demonstrate its clinical application in breast cancer diagnosis, showing that the biomarkers carcinoembryonic antigen (CEA) and cancer antigen 15-3 (CA15-3) reflect the presence of BC, and the method can accurately distinguish cancer patients from non-cancer controls. Receiver operator characteristic (ROC) curves showed that the combined assessment of the two biomarkers provided extremely high sensitivity and specificity. This study provides a new strategy for rapid early diagnosis of cancer and other diseases.

Research on Architecture of Local Domain Application Based on Radio Frequency Identification

Along with the speedy improvement of sensing systems, wireless transmission technology, and faster and faster chip, the scope of application of the Internet of things (IoT) has substantially and rapidly increased, and research and innovation that integrate artificial intelligence. At same time, campus application construction as the foundation of intelligence education is being on the march, which demands newly emerging computer technologies support, such as IoT, AI, Big data and so on. In this study, we provide an architecture of smart campus based on Radio Frequency Identification (RFID) which can offer new solutions to solve some problems such as position, identification, store information and so on because of its strong anti-interference capability and non-intrusiveness, as core technology of IoT. Then based on this architecture, a kind of intelligent campus application system scheme is proposed, which can realize the function of automatic identity recognition, book reading, internal consumption, student positions. Moreover, for some special exact location demands, this paper proposes a method to precisely measure RFID tag location based on triangulation principle, which is embedded in the architecture. The application of Internet of things technology can better promote some origination or company efficiency, such as more efficient service for teachers’ and students’ work, study and life.

Recapitulation of First Pass Metabolism Using 3D Printed Microfluidic Chip and Organoid.

The low bioavailability of oral drugs due to first pass metabolism is a major obstacle in drug development. With significant developments in the field of in vitro organ modeling and microfluidic chip three-dimensional (3D) printing, the challenge is to apply these for the production and evaluation of new drug candidates. This study aimed to produce a microfluidic chip to recapitulate and assess the feasibility of the first pass metabolism. The infill condition of the polycarbonate transparent filament and layer height was optimized to visualize and maintain the organoid or spheroid on the chip. Next, the chip was fabricated using a 3D printer after a computer-aided design (CAD). The chip consisted of three wells of different heights. The small intestinal (SI) organoid and colorectal adenocarcinoma spheroids were placed on the second and third wells, respectively. No additional equipment was assembled, and the tilted tunnel was connected to each well to transport the material by gradient force. The chip was fabricated using 50% and 0.1 um thickness. Among the three different prototypes of chip (chips 1, 2, and 3), the highest distribution of plasmids in the Matrigel of the second well was observed in Chip 2 at 48 h. The effect of first pass metabolism was analyzed using docetaxel. In the chip without an SI organoid, there was a marked decrease in the viability of colorectal adenocarcinoma spheroids due to drug efficacy. However, in the chip with the SI organoid, no significant change in viability was observed because of first pass metabolism. In conclusion, we presented a simple, fast, and low-cost microfluidic chip to analyze the efficacy change of candidate drug by the first pass metabolism.

The Relationship Between Intuitive Eating and Diet Quality in a College Population

Many college students have nutrient poor and energy dense diets and are also more likely to experience poor body image, which can result in unsafe dieting behaviors for the purpose of managing weight. Intuitive eating is an alternative approach to dieting that focuses on physiological hunger and fullness cues, while eating for both satisfaction and health without restriction of any foods. This study examined the association between intuitive eating and diet quality in a college population. College students, aged 18-56 years, completed an online survey which assessed intuitive eating using the Intuitive Eating Scale-2 (IES-2) and diet quality using the Starting The Conversation (STC) simplified food frequency instrument. IES-2 total score was positively correlated with higher overall diet quality and was negatively correlated with fast food and chip consumption. Eating for physical rather than emotional reasons and body-food choice congruence IES-2 subscales were positively correlated with diet quality while the unconditional permission to eat subscale was negatively correlated with diet quality. Strategies that focus on eating for health and well-being and minimize emotional eating are associated with higher overall diet quality and may be incorporated in dietary interventions among college students aimed at promoting healthy behaviors.

Probing Three Distinct Crystal Polymorphs of Melt-Crystallized Polyamide 6 by an Integrated Fast Scanning Calorimetry Chip System

Probing Three Distinct Crystal Polymorphs of Melt-Crystallized Polyamide 6 by an Integrated Fast Scanning Calorimetry Chip System

Bio‐Sourced Poly l‐Lactide‐Flax Composites with Close to Maximum Stiffness at Low Fiber Content through Two‐Stage Annealing

AbstractPoly l‐Lactide (PLLA) composites with short flax fibers (from 0 to 10 wt/wt%) with close to maximum theoretical stiffness are prepared by melt‐compounding and injection‐molding followed by a two‐step isothermal crystallization protocol that fully separates the nucleation and growth stages (Tammann). The use of fast chip scanning calorimetry for thermal characterization avoids the complicating issues of crystal reorganization during the cooling and heating steps between the isothermal stages. Flax fibers are very efficient and selective nucleating agents of PLLA favoring the ordered α form. The resulting morphology exhibits trans‐crystallization on the fibers surface, predominantly at fiber defects, with a clear reduction of crystal size and a very strong fiber matrix cohesion. Efficient nucleation further leads to a large reduction of the overall crystallization time. Avrami analysis evidences a reduction of crystal growth dimensionality, consistent with both optical and scanning electron microscopy. The high modulus of the composites is unambiguously related to the strong orientation of the fibers in the tensile direction, to their high aspect ratio and to the excellent matrix‐fibers cohesion. On the other hand, the tensile strength and hardness appear isotropic within experimental uncertainty and are unfavorably influenced by the presence of the fibers and by the two‐stage annealing.

Internet of Everything: Macro & Micro

Ten years ago, venture capitalist Marc Andreessen proclaimed that software was eating the world. Today, the hottest features in the latest phones are software updates or AI improvements, not faster chips or new form factors. Technology is becoming more mundane, and ultimately, invisible.

A graph placement methodology for fast chip design.

Chip floorplanning is the engineering task of designing the physical layout of a computer chip. Despite five decades of research1, chip floorplanning has defied automation, requiring months of intense effort by physical design engineers to produce manufacturable layouts. Here we present a deepreinforcementlearning approach to chip floorplanning. In under six hours, our method automatically generates chip floorplans that are superior or comparable to those produced by humans in all key metrics, including power consumption, performance and chip area. To achieve this, we pose chip floorplanning as a reinforcementlearning problem, and develop an edge-based graph convolutional neural network architecture capable of learning rich and transferable representations of the chip. As a result, our method utilizes past experience to become better and faster at solving new instances of the problem, allowing chip design to be performed by artificial agents with more experience than any human designer. Our method was used to design the next generation of Google's artificial intelligence (AI) accelerators, and has the potential to save thousands of hours of human effort for each new generation. Finally, we believe that more powerful AI-designed hardware will fuel advances in AI, creating a symbiotic relationship between the two fields.

Design and realization of a weak magnetic fast electric heating chip

In a high-sensitivity atomic magnetometer, increasing the temperature of the vapor cell causes higher polarized atomic density, which enhances the intensity of the output signal. Therefore, it is essential to precisely control the temperature of the vapor cell. Based on the principle of electric heating and reverse magnetic cancellation, miniature weak magnetic electric heating chips of single-layer and double-layer structure are designed. By measuring the magnetic flux density at different distances and currents, it can be proved that the chips suppress the magnetic field. The experiment results show that the double-layer chip is better than the single-layer chip in respect of magnetic suppression and temperature response. The magnetic flux density introduced by the current at 5 mm from the chip is 0.0722 nT mA−1. These results show that a high-precision heating method for the atomic vapor cell can be realized by the double-layer meander structure, which provides a simple and fast electric heating scheme for atomic polarization.

Diet quality, school attendance, and body weight status in adolescent girls in rural Guatemala.

A cluster of factors affects nutritional status among adolescent girls in low- and middle-income countries (LMICs). We investigated the association between school attendance and diet quality among 498 rural adolescent girls (352 attending and 146 not attending school) in Tecpán, Guatemala. In a cross-sectional study, we collected sociodemographic and anthropometric data and characterized the dietary intake using a Food Frequency Questionnaire. We then calculated diet quality using the Healthy Eating Score (HES). Multiple linear regression models were conducted to evaluate the effects of school attendance on diet quality. We found that the overall diet quality among the study participants was poor, according to the HES. However, those who attended school had significantly higher intakes of vitamin A-rich fruits and vegetables (P=0.04), other fruits (P=0.01), and milk and milk products (P=0.004), but a higher intake of fast foods, chips, and saturated fatty acids (P < 0.001). Furthermore, the effects of school attendance on diet quality were significant after adjusting for sociodemographic and lifestyle factors (β coefficient=-1.70, 95% CI: -3.30 to -0.11) but was attenuated when further adjusted for weight status (β coefficient=-1.58, 95% CI: -3.17 to 0.02). Our findings suggest that diet quality among girls in rural Guatemala is poor, particularly among those who do not attend school. To advance our understanding of adolescent diet in LMICs, future studies should include adolescents who are out of school.

FPGA Architectural Flow: CAD Improvements

Field Programmable Gate Arrays have long been seen as a viable alternative to Application Specific Integrated Circuits (ASICs) . While ASICs have very sophisticated commercialized EDA tools that deliver very fast and power efficient chips, the FPGA world has unfortunately not seen the kind of software investment the ASIC world has seen. However, with the ever rising demand of FPGA based applications and increasing semiconductor complexity of late, the techniques and efficient algorithms of ASIC software have trickled down to FPGA as well, In this paper, we are going to look at some of these techniques that have resulted in better performance per watt- a key metric in FPGA world. We will also do a brief comparison of ASIC vs FPGA design flow and FPGA architecture, connect the dots and make user better aware of the challenges that are faced by FPGA designers in implementing a certain design technique and how the software tries to overcome those challenges. This paper would be useful for new ASIC developers entering in the FPGA world, or even experienced FPGA developers who can get some ideas from this paper for the betterment of the FPGA compilation process.

High Speed Energy Efficient Multiplier Using 20nm FinFET Technology

VLSI technology is essential for chip fabrication, and multiplier circuits are used in electronic gadgets consistency of design, small, fast, and so forth Multiplier assumes a significant function in the present computerized handling and different applications. Multipliers are the key segments in some fast frameworks, for example, FIR channels, chip, ALU and other business applications like PCs, mobiles, rapid mini-computers, and some broadly useful processors require double multipliers. Since a most recent couple of years, the minuscule size of MOSFET, that is under many nanometres, made some operational issues, for example, expanded entryway oxide spillage, intensified intersection spillage, high sub-limit conduction and decreased yield opposition. To defeat the above issues, FinFET has the upsides of an expansion in the working pace, decreased force utilization, diminished static spillage current is utilized to understand most of the applications by supplanting MOSFET. The Multiplier is designed by using FinFET. This multiplier we can use for specific application. Successive multiplier circuits are broadly utilized for data storage like memory and used for sequential circuits. The plan is recreated utilizing Cadence virtuoso with 20nm innovation. Near execution investigation is done rather than the other standard circuits by taking the essential presentation measurements, for example, deferral, force, and force postpone item (PDP), energy defers item (EDP) measurements into thought.

Algorithm and Architecture Design of FAST-C Image Corner Detection Engine

First-in–first-out (FIFO) line buffers occupy considerable logic gates and consume significant power of the feature from accelerated segment test (FAST) image corner detection engine. In this study, a FAST-Chip (FAST-C) engine is proposed to eliminate these drawbacks. It comprises three core techniques: arch pixel estimation (APE), hardware-efficient line buffer (HLB), and interleaving-based parallel access (IPA). APE can save three line buffers using gradient information for pixel prediction. With APE, the number of line buffers can be saved by 33%. HLB effectively organizes static random access memories (SRAMs) as line buffers to store reference pixels rather than FIFO. It demands less power and fewer logic gates. IPA makes the FAST-C engine have regular data paths and smooth data scheduling, keeping hardware throughput. Experiment results show that the accuracy difference between FAST and FAST-C is as minor as 2.29%. The proposed FAST-C engine is implemented using the Taiwan Semiconductor Manufacturing Company (TSMC) 0.18- $\mu \text{m}$ CMOS process with a logic gate count of 223k, where the line buffers are included. Its frequency is 613 MHz with a power consumption of 1.18 W. Its maximum throughput can sufficiently support $3840\times 2.160$ (4k) @ 60 frames per second (fps). Compared with sophisticated FAST engines, the FAST-C engine presents outstanding energy efficiency (EE) and area efficiency (AE).

Design and characterization of the FAST chip: a front-end for 4D tracking systems based on Ultra-Fast Silicon Detectors aiming at 30 ps time resolution

Detectors able to measure the time of flight with very high accuracy (∼10 ps RMS) are becoming fundamental in the design of new High Energy Physics experiments, where accurate time measurements will be used to mitigate pileup effects. The development of such detectors has spurred intense R&D in both silicon sensors and the associated readout electronics, aiming at obtaining silicon-based detectors with a time resolution in the few tens-of-picosecond range. This work presents FAST, a family of three different 20 channel amplifier-comparator chips, tailored to the readout of Ultra Fast Silicon Detectors. These ASICs have been designed optimizing the sensor-readout interplay with the aim of reaching the smallest possible jitter term. The three chips of the FAST family differ in the architecture of the front-end while sharing the channel back-end, consisting of a leading-edge discriminator and a LVDS driver. The goal of these front-ends is to achieve a time resolution of about 30 ps RMS while coupled to a sensor with a few pico-Farad capacitance, keeping the power budget of the single channel below 1.3 mW. This paper reports the description of the FAST design architecture and summarizes the results on the initial characterization of one chip of the FAST family, in a stand-alone test structure and when coupled to a UFSD.

A fast digital chip implementing a real-time noise-resistant algorithm for estimating blood pressure using a non-invasive, cuffless PPG sensor

A fast digital chip is designed and fabricated successfully to implement the algorithm for estimating blood pressure (BP) in real time by a non-invasive cuffless photoplethysmogram (PPG) Sensor. The fast response accomplished by this digital computation chip is made possible by one-time calibration only and the Taiwan Semiconductor Manufacturing (TSMC) T18 process to realize the chip in an area of 3.97 mm2. The experimental result shows that the overall power consumption of the chip is 15.62 mW. Finally, the blood pressure measurement platform has been developed with a user interface (UI) for long-term continuous cuffless BP measurement. The non-invasive blood pressure sensor is applied to the wrist arteries of 44 subjects for sensing the PPG pulsation of the blood vessel, and then estimating BPs (blood pressures). Measurement results shows that the maximum error in the BP measurement is ± 6 mmHg. Which is less than 8 mmHg, defined by the Advancement of Medical Instrumentation (AAMI) and British Hypertension Society (BHS) standard.