FPGA Architectural Flow: CAD Improvements

Abstract

Field Programmable Gate Arrays have long been seen as a viable alternative to Application Specific Integrated Circuits (ASICs) . While ASICs have very sophisticated commercialized EDA tools that deliver very fast and power efficient chips, the FPGA world has unfortunately not seen the kind of software investment the ASIC world has seen. However, with the ever rising demand of FPGA based applications and increasing semiconductor complexity of late, the techniques and efficient algorithms of ASIC software have trickled down to FPGA as well, In this paper, we are going to look at some of these techniques that have resulted in better performance per watt- a key metric in FPGA world. We will also do a brief comparison of ASIC vs FPGA design flow and FPGA architecture, connect the dots and make user better aware of the challenges that are faced by FPGA designers in implementing a certain design technique and how the software tries to overcome those challenges. This paper would be useful for new ASIC developers entering in the FPGA world, or even experienced FPGA developers who can get some ideas from this paper for the betterment of the FPGA compilation process.