Fast Power Estimation Research Articles

BPNS: A Fast and Accurate Power Estimation Model for Embedded Devices

The surge in the intelligent information age has led to a growing need for enhanced computing power in smart mobile devices. However, the accompanying increase in computing power brings about a significant challenge — high power consumption. This poses a notable hurdle for mobile devices that prioritize sustainability performance. Effectively addressing power consumption estimation is crucial for overcoming this sustainability issue. In this paper, we propose using a branching parallel neural networks (BPNS) that consists of FCNN-LSTM and a attention mechanism to estimate the power consumption of a device. In addition, a data stabilization module is incorporated into the framework to improve the power estimation accuracy. We implement and assess the performance of BPNS for online estimation across diverse smart mobile devices, conducting a comparative analysis with commonly used neural networks. Notably, our approach achieves a deviation of 0.28W, 0.65W and 0.76W for online estimation on three smart mobile devices, and outperforms other methods in terms of estimation accuracy and computational cost.

NeuPow

In this article, we present a new, simple, accurate, and fast power estimation technique that can be used to explore the power consumption of digital system designs at an early design stage. We exploit the machine learning techniques to aid the designers in exploring the design space of possible architectural solutions, and more specifically, their dynamic power consumption, which is application-, technology-, frequency-, and data-stimuli dependent. To model the power and the behavior of digital components, we adopt the Artificial Neural Networks (ANNs), while the final target technology is Application Specific Integrated Circuit (ASIC). The main characteristic of the proposed method, called NeuPow, is that it relies on propagating the signals throughout connected ANN models to predict the power consumption of a composite system. Besides a baseline version of the NeuPow methodology that works for a given predefined operating frequency, we also derive an upgraded version that is frequency-aware, where the same operating frequency is taken as additional input by the ANN models. To prove the effectiveness of the proposed methodology, we perform different assessments at different levels. Moreover, technology and scalability studies have been conducted, proving the NeuPow robustness in terms of these design parameters. Results show a very good estimation accuracy with less than 9% of relative error independently from the technology and the size/layers of the design. NeuPow is also delivering a speed-up factor of about 84× with respect to the classical power estimation flow.

Fast and Accurate System-Level Power Estimation Model for FPGA-Based Designs

In this paper, we present an efficient and fast system-level power estimation model for the FPGA-based designs. To estimate the dynamic power early, first time, LLVM IR code analysis is employed at the C-level designs and then the neural network-based estimation model is built from the information obtained from this high-level profiling. The model accuracy is validated through designs of heterogeneous domains from the CHStone and MachSuite benchmarks. An insignificant relative error of 0.21–3.6% is observed for the analyzed benchmark designs with the exceptional increase in the estimation speed by 63 times of magnitude as compared to the Xilinx Vivado Design Suite. Moreover, the model eliminates the need for synthesis-based exploration. In addition, the effectiveness of proposed approach is also verified through a comparison with the other reported works.

Fast and efficient power estimation model for FPGA based designs

With the growing scope of embedded computing, specific design objectives demand quick exploration and estimation of design metrics. Power estimation is one such primary design metric which needs to be estimated at the earliest stage of high-level design. In this paper, a model is presented to estimate dynamic power requirement of any given application for a target field-programmable gate array (FPGA) device. The methodology comprises of the profiling of the C/C++ programs through a low-level virtual machine (LLVM) pass and training of an artificial neural network model using the profiling results to estimate power. For profiling an application, the LLVM based framework is employed, which generates target independent LLVM intermediate representation (IR). A module pass is written to obtain the count of the different type of instructions. A model using artificial neural network has been proposed to give the power estimate, which takes as inputs the category-wise number of instructions and FPGA target resources on which the respective applications are mapped. The Zynq family device is profiled using Vivado HLS v.2015.4. The model has been validated against CHStone benchmark programs. Furthermore, a reduced relative error of 0.19% to 7.9% is observed for the analyzed benchmark designs, with the exceptional increase in estimation speed, which is more than the order of magnitude of the conventional Xilinx Vivado Design Suite. Therefore, for designers, this modeling methodology provides better, accurate and fast power estimation, at the early stage of the VLSI design.

Accurate and Stable Run-Time Power Modeling for Mobile and Embedded CPUs

Modern mobile and embedded devices are required to be increasingly energy-efficient while running more sophisticated tasks, causing the CPU design to become more complex and employ more energy-saving techniques. This has created a greater need for fast and accurate power estimation frameworks for both run-time CPU energy management and design-space exploration. We present a statistically rigorous and novel methodology for building accurate run-time power models using performance monitoring counters (PMCs) for mobile and embedded devices, and demonstrate how our models make more efficient use of limited training data and better adapt to unseen scenarios by uniquely considering stability. Our robust model formulation reduces multicollinearity, allows separation of static and dynamic power, and allows a $100{\times }$ reduction in experiment time while sacrificing only 0.6% accuracy. We present a statistically detailed evaluation of our model, highlighting and addressing the problem of heteroscedasticity in power modeling. We present software implementing our methodology and build power models for ARM Cortex-A7 and Cortex-A15 CPUs, with 3.8% and 2.8% average error, respectively. We model the behavior of the nonideal CPU voltage regulator under dynamic CPU activity to improve modeling accuracy by up to 5.5% in situations where the voltage cannot be measured. To address the lack of research utilizing PMC data from real mobile devices, we also present our data acquisition method and experimental platform software. We support this paper with online resources including software tools, documentation, raw data and further results.

FPGA emulation methodology for fast and accurate power estimation of embedded processors

Abstract Early estimation of application-specific power consumption has become one of the major constraints of modern ASIC design. While in early stages of the design process precise power consumption can only be obtained from very time consuming gate-level (GTL) simulation, power estimation methodologies aim to reduce computational overhead by deriving models to approximate power consumption on higher levels. This work presents an FPGA accelerated power estimation methodology for programmable processors based on a hybrid functional level (FLPA) and instruction level power analysis (ILPA) that can be mapped onto an FPGA together with the functional emulation. It enables fast and accurate estimation of application-specific power consumption and energy per task which is crucial for power-aware design of embedded processor architectures. The approach allows both hardware and software designers to optimize their implementations not only for processing performance but also for power efficiency. The power emulation methodology and considerations for the FPGA implementation of the power estimation is described in detail. Model validation against GTL power simulation and results are given for a typical embedded RISC processor and a commercial-grade Application Specific Instruction Set Processor (ASIP). Power consumption models yield fast and accurate power estimation with a %MAE of less than 9% and NRMSE of less than 7% enabling co-optimization of both hardware and software with respect to power consumption in early design stages.

Power analysis approach and its application to IP-based SoC design

Purpose Low-power consumption has become an important issue that cannot be ignored in System-on-Chip (SoC) design. The key challenge encountered by system design is how to maintain balance between the estimation accuracy and speed. This paper aims at demonstrating an accurate and fast power estimation technique. Design/methodology/approach The methodology adopted in the paper is to use input patterns with the predefined statistical characteristics which helps to analyze the average power consumption of the different intellectual-property (IP) cores and the interconnects/buses in SoC design. Similarly the paper has implemented Genetic algorithm (GA) to generate sequences of input signals during the power estimation procedure. Findings The GA concurrently optimizes the input signal characteristics that influence the final solution of the pattern. In addition to that, a Monte-Carlo zero-delay simulation is also performed for individual IP core and bus at high-level. By the simple addition of these cores/buses, power is predicted by a novel macro-model function. In experiments, the average error is estimated at 13.84%. Research limitations/implications To present the research findings with clarity and to avoid complexities, the paper does not consider delay factors like glitches, jitter etc. in the power model. Practical implications The proposed methodology allowed accurate power/energy analysis of practical applications mapped onto Network-on-Chip (NoC) based Multiprocessors SoC platform. It enables the performance analysis of different design alternatives under the load imposed by complex applications. Originality/value This paper is an original contribution and the results demonstrate that our novel technique could be implemented to achieve fast and accurate power estimation in the early stage of any SoC design.

Power estimation for intellectual property-based digital systems at the architectural level

Estimating power consumption is becoming the critical issue that cannot be neglected in VLSI (very large scale integration) design procedure. Low power solutions are an imperative requirement for the SoC (System-on-Chip) flow that gives designers a powerful methodology to analyze, estimate, and optimize today’s increasing power concerns.We present an efficient power macro-modeling technique at the architectural level for digital electronic systems. This technique estimates the power dissipation of intellectual property (IP) components to their statistical knowledge of the primary inputs/outputs. During the power estimation method, the sequence of an input stream is generated by a genetic algorithm (GA) using input metrics and the macro-model function to construct a set of functions that map the input metrics of a macro-block to its output metrics. Then, a Monte Carlo zero-delay simulation is performed and the power dissipation is predicted by a macro-model function. The most important contribution of the technique is that it allows fast power estimation of IP-based design by the simple addition of individual power consumption. This makes the power modeling of SoCs an easy task that permits evaluation of power features at the architectural level. In order to evaluate our model, we have constructed IP-based digital systems using different IP macro-blocks. In experiments with an individual IP macro-block the average error is 1–2% and for an entire IP-based system with interconnects, the error range is from 9% to 15%. The preliminary results are effective and our macro-model provides accurate power estimation.

Fast and accurate power estimation of FPGA DSP components based on high-level switching activity models

When designing DSP circuits, it is important to predict their power consumption early in the design flow in order to reduce the repetition of time consuming design phases. High-level modelling is required for fast power estimation when a design is modified at the algorithm level. This paper presents a novel high-level analytical approach to estimate logic power consumption of arithmetic components implemented in FPGAs. In particular, models of adders and multipliers are presented in detail. The proposed methodology considers input signal correlation and glitching produced inside the component. It is based on an analytical computation of the switching activity in the component which takes into account the component architecture. The complete model can estimate the power consumption for any given clock frequency, signal statistics and operands' word-lengths. Compared to other proposed power estimation methods, the number of circuit simulations needed for characterising the power model of the component is highly reduced. The accuracy of the model is within 10% of low-level power estimates given by the tool XPower, and it achieves better overall performance.

Accurate data path models for fast RT-level power estimation

A methodology is presented for RT-level power estimation using cycle-accurate power models of common components, exploiting their functionality, regularity, and symmetry. The proposed methodology consists of three steps: creation of a set of look-up tables of primitive blocks, creation of a C power model for each data path component, estimation of power consumption of an RT-level circuit using a simulation engine that exploits the component's regular structure. The accuracy and the efficiency of the proposed models are compared using QuickSim as a real delay gate-level power estimator. Experimental results show that the proposed models exhibit <0.5% error in both average and cycle-by-cycle power, while they are about 50 times faster than QuickSim simulator of Mentor Graphics.

High-level synthesis of low-power control-flow intensive circuits

In this paper, we present a comprehensive high-level synthesis system that is geared toward reducing power consumption in control-flow intensive as well as data-dominated circuits. An iterative improvement framework allows the system to search the design space by examining the interaction between the different high-level synthesis tasks. In addition to incorporating traditional high-level synthesis tasks such as scheduling, module selection and resource sharing, we introduce a new optimization that performs power-conscious structuring of multiplexer networks, which are predominant in control-flow intensive circuits. The scheduler employed is capable of loop optimizations within and across loop boundaries. We also introduce a fast power estimation technique, based on switching activity matrices, to drive the synthesis process. Experimental results for a number of control-flow intensive and data-dominated benchmarks demonstrate power reduction of up to 62% (58%) when compared to V/sub dd/-scaled area-optimized (delay-optimized) designs. The area overheads over area-optimized designs are less than 39%, whereas the area savings over delay-optimized designs are up to 40%.

Activity measures for fast relative power estimation directed numerical transformation for low power DSP synthesis

In this paper, we propose a method for optimizing digital signal processing (DSP) systems for both power and circuit area. The optimization involves application of numerical transformations to the matrices of a linear system. A greedy search algorithm is used, along with fast and efficient activity estimator to synthesize low power systems. The method is applicable to bit-serial, nibble-serial as well as fully word-parallel architectures. In this paper we focus primarily on bit-serial architectures and show that up to 35 percent savings in power and hardware may be obtained.

Event-Driven Power Estimation of CMOS Circuits

Fast and accurate power estimation has become an important topic with the increasing need for low power electronics. In this paper we address the problem of using event-driven simulation tools for power estimation. We identify and compare two approaches: input-driven and output-driven, and propose several ways of improvement. The estimation accuracy is degraded in event-driven power estimators due to superfluous and partial glitches. We described glitch filtering and estimation techniques pertaining to input-driven and output-driven power estimators. An output-driven power estimator, Peony, was developed which used the proposed path power idea to improve the estimation accuracy. It achieved significant power estimation accuracy improvement at a speed of two orders of magnitude faster than Spice.

Fast power estimation of large circuits

Our new technique for estimating transition probabilities of internal signals in combinational circuits uses Markov chains and reconvergence regions. To efficiently implement the computation, we use ROBDDs (reduced, ordered binary decision diagrams). Accounting for temporal dependence of signals, multiple concurrent transitions, and mutual dependence of internal signals, the technique provides an exact computation for small circuits and an approximate estimate for large circuits. Experimental results show the estimation technique is fast with only small inaccuracies.