Fast Point Multiplication Research Articles

High-Speed Area-Efficient Processor for Elliptic Curve Point Multiplication Over Prime Field Along with RSA Comparison

Creating a high-speed elliptic curve cryptographic (ECC) processor capable of performing fast point Multiplication with low hardware utilisation is a critical requirement in cryptography and network security. This paper describes the implementation of a high-speed, field-programmable gate array (FPGA) in this paper. A high-security digital signature technique is implemented using Edwards25519, a recently approved twisted Edwards’s curve. For point addition and point doubling operations on the twisted Edwards curve, advanced hardware configurations are developed in which each task involves only 516 and 1029 clock cycles, respectively. As an observation the ECC processor presented in this paper begins with the process which takes 1.48 ms of single-point multiplication to be performed. The comparison of key size and its ratio which shows the impact on processing of each processor is shown for ECC processor and RSA processor. The delay and number of slices used for the ECC processor is shown and this is a developed solution saves time by providing rapid scalar multiplication with low hardware consumption without compromising on security.

Low-Cost, Low-Power FPGA Implementation of ED25519 and CURVE25519 Point Multiplication

Twisted Edwards curves have been at the center of attention since their introduction by Bernstein et al. in 2007. The curve ED25519, used for Edwards-curve Digital Signature Algorithm (EdDSA), provides faster digital signatures than existing schemes without sacrificing security. The CURVE25519 is a Montgomery curve that is closely related to ED25519. It provides a simple, constant time, and fast point multiplication, which is used by the key exchange protocol X25519. Software implementations of EdDSA and X25519 are used in many web-based PC and Mobile applications. In this paper, we introduce a low-power, low-area FPGA implementation of the ED25519 and CURVE25519 scalar multiplication that is particularly relevant for Internet of Things (IoT) applications. The efficiency of the arithmetic modulo the prime number 2 255 − 19 , in particular the modular reduction and modular multiplication, are key to the efficiency of both EdDSA and X25519. To reduce the complexity of the hardware implementation, we propose a high-radix interleaved modular multiplication algorithm. One benefit of this architecture is to avoid the use of large-integer multipliers relying on FPGA DSP modules.

FPGA Implementation of High-Speed Area-Efficient Processor for Elliptic Curve Point Multiplication Over Prime Field

Developing a high-speed elliptic curve cryptographic (ECC) processor that performs fast point multiplication with low hardware utilization is a crucial demand in the fields of cryptography and network security. This paper presents field-programmable gate array (FPGA) implementation of a high-speed, low-area, side-channel attacks (SCAs) resistant ECC processor over a prime field. The processor supports 256-bit point multiplication on recently recommended twisted Edwards curve, namely, Edwards25519, which is used for a high-security digital signature scheme called Edwards curve digital signature algorithm (EdDSA). The paper proposes novel hardware architectures for point addition and point doubling operations on the twisted Edwards curve, where the processor takes only 516 and 1029 clock cycles to perform each point addition and point doubling, respectively. For a 256-bit key, the proposed ECC processor performs single point multiplication in 1.48 ms, running at a maximum clock frequency of 177.7 MHz in a cycle count of 262 650 with a throughput of 173.2 kbps, utilizing only 8873 slices on the Xilinx Virtex-7 FPGA platform, where the points are represented in projective coordinates. The implemented design is time-area-efficient as it offers fast scalar multiplication with low hardware utilization without compromising the security level.

A New RNS Approach for Fast Point Multiplication on Elliptic Curves over F p

A New RNS Approach for Fast Point Multiplication on Elliptic Curves over F p

Cryptography with fast point multiplication by using ASCII codes and its implementation

This paper describes the point multiplication through addition-subtraction method and its implementation through MATLAB to speed up the operations in elliptic curve cryptography ECC with ASCII codes under limited hardware resources. To further decrease the computation time, we employed the non-adjacent form of a binary sequence to decrease the total number of additions in ECC encryption/decryption. This paper implements ASCII code table for convenient manipulation of characters, and addition-subtraction method for point multiplication with less time and space complexity with its implementation in MATLAB. We can fully use the idle time of hardware resources by relaxing the data dependency on those arithmetic operations performed to accomplish the point multiplication. As a result, hardware utilisation increases. ECC is the most applicable and suitable algorithm for mobile devices due to its compact shape and size.

The Construction of GLV-Friendly Elliptic Curves With Fast Point Multiplication

The Construction of GLV-Friendly Elliptic Curves With Fast Point Multiplication

Fast point multiplication on Koblitz curves: Parallelization method and implementations

Point multiplication is required in every elliptic curve cryptosystem and its efficient implementation is essential. Koblitz curves are a family of curves defined over F 2 m allowing notably faster computation. We discuss implementation of point multiplication on Koblitz curves with parallel field multipliers. We present a novel parallelization method utilizing point operation interleaving. FPGA implementations are described showing the practical feasibility of our method. They compute point multiplications on average in 4.9 μs, 8.1 μs, and 12.1 μs on the standardized curves NIST K-163, K-233, and K-283, respectively, in an Altera Stratix II FPGA.

A New Minimal Average Weight Representation for Left-to-Right Point Multiplication Methods

This paper introduces a new radix-2 representation with the same average weight as the width-w nonadjacent form (w-NAF). In both w-NAF and the proposed representations, each nonzero digit is an odd integer with absolute value less than M. However, for w-NAF, M is of the form 2/sup w-1/, while, for the proposed representation, it can be any positive integer. Therefore, using the proposed integer representation, we can use the available memory efficiently, which is attractive for devices with limited memory. Another advantage of the proposed representation over-w-NAF is that it can be obtained by scanning the bits from left-to-right. This property is also useful for memory-constrained devices because it can reduce both the time and space complexity of fast point multiplication techniques.