Fast Non-volatile Memory Research Articles

NORM: An FPGA-based Non-volatile Memory Emulation Framework for Intermittent Computing

Today’s intermittent computing systems operate by relying only on harvested energy accumulated in their tiny energy reservoirs, typically capacitors. An intermittent device dies due to a power failure when there is no energy in its capacitor and boots again when the harvested energy is sufficient to power its hardware components. Power failures prevent the forward progress of computation due to the frequent loss of computational state. To remedy this problem, intermittent computing systems comprise built-in fast non-volatile memories with high write endurance to store information that persists despite frequent power failures. However, the lack of design tools makes fast-prototyping these systems difficult. Even though FPGAs are common platforms for fast prototyping and behavioral verification of continuously powered architectures, they do not target prototyping intermittent computing systems. This article introduces a new FPGA-based framework, named NORM ( N on-volatile mem OR y e M ulator), to emulate and verify the behavior of any intermittent computing system that exploits fast non-volatile memories. Our evaluation showed that NORM can be used to emulate and validate FeRAM-based transiently powered hardware architectures successfully.

MeF-RAM: A New Non-Volatile Cache Memory Based on Magneto-Electric FET

Magneto-Electric FET ( MEFET ) is a recently developed post-CMOS FET, which offers intriguing characteristics for high-speed and low-power design in both logic and memory applications. In this article, we present MeF-RAM , a non-volatile cache memory design based on 2-Transistor-1-MEFET ( 2T1M ) memory bit-cell with separate read and write paths. We show that with proper co-design across MEFET device, memory cell circuit, and array architecture, MeF-RAM is a promising candidate for fast non-volatile memory ( NVM ). To evaluate its cache performance in the memory system, we, for the first time, build a device-to-architecture cross-layer evaluation framework to quantitatively analyze and benchmark the MeF-RAM design with other memory technologies, including both volatile memory (i.e., SRAM, eDRAM) and other popular non-volatile emerging memory (i.e., ReRAM, STT-MRAM, and SOT-MRAM). The experiment results for the PARSEC benchmark suite indicate that, as an L2 cache memory, MeF-RAM reduces Energy Area Latency ( EAT ) product on average by ~98% and ~70% compared with typical 6T-SRAM and 2T1R SOT-MRAM counterparts, respectively.

Sub-nanosecond threshold switching dynamics in GeSb2Te4 phase change memory device

Conventional Ge–Sb–Te based phase change memory (PCM) devices offer promising attributes, including fast non-volatile memory operations, higher endurance and sub-ns re-crystallization/re-amorphization capabilities for the next generation high speed non-volatile memory. The threshold switching process in the amorphous phase of the PCM device enables breakdown of electrical resistance followed by rapid flow of device current, leading to Joules heating induced crystallization, known as SET operation. The speed of SET operation is, therefore, governed by voltage dependent threshold switching dynamics and the delay time (td) characteristics at the timescale of nanoseconds. Although GeSb2Te4 offers faster crystal growth velocity, realization of fast threshold switching capabilities remains unexplored. In this work, the ultrafast threshold switching dynamics of a prototypical GeSb2Te4 PCM device are investigated. The present experimental results demonstrate an exponential reduction of td upon increasing the applied voltage (VA) above its threshold voltage (VT). The td has been reduced to a strikingly lower value of 0.5 ns for VA of 1.6 times of VT, which enables faster SET operation within 3 ns as evidenced by a permanent change in the device resistance. These experimental findings of sub-nanosecond threshold switching dynamics and faster SET operation in the GeSb2Te4 device pave a way for designing a PCM device with ns programming speed for future electronics.

Atomic Force High Frequency Phonons Non-volatile Dynamic Random-Access Memory Compatible with Sub-7nm ULSI CMOS Technology

ABSTRACTThis paper reports a novel low power, fast nonvolatile memory utilizing high frequency phonons, atomic force dual quantum wells, ferromagnetism, coupled magnetic dipoles and random accessed magnetic devices. Very high-speed memories, such as SRAM and DRAM, are mostly volatile (data are lost when power is off). Nonvolatile memories, including FLASH and MRAM, are typically not as fast has DRAM or SRAM, and the voltages for WRITE/ERASE operations are relatively high. This paper describes a silicon nonvolatile memory that is compatible with advanced sub-7nm CMOS process. It consists of only one transistor (MOSFET) – small size, and more cost effective, compared with a 6-Transistor SRAM. There is no need to refresh, as required by DRAM. The access time can be less than 1ns – close to the speed level of relaxation time - much faster than traditional FLASH memories and comparable to volatile DRAM. The operating voltages for all memory functions can be as low as high speed CMOS.

Random Number Generation Based on Ferroelectric Switching

Hafnium oxide-based ferroelectric field-effect transistors (FeFETs) have a great potential for fast nonvolatile memory due to their high performance, fully CMOS compatible integration, and low-power operation. The aggressive scaling of these devices has revealed novel features, such as the multilevel storage capability and abrupt switching, which, however, appears to be a stochastic process. In this letter, we propose a path for true random number generation based on the statistical switching in a single FeFET device. It relies on an inherent randomness of the polarization reversal of ferroelectric domains in the gate stack. The bit sequence is generated by repeatedly programming an FeFET at a calibrated voltage and pulse width, and features random and equiprobable “ones” and “zeros,” which are separated by orders of magnitude in drain current. This simple yet reliable operation provides a compact one-transistor solution for the unbiased random number generation.

Optimizing I/O Operations in File Systems for Fast Storage Devices

Fast non-volatile memory (NVM) technologies (e.g., phase change memory, spin-transfer torque memory, and MRAM) provide high performance to legacy storage systems. These NVM technologies have attractive features, such as low latency and high throughput to satisfy application performance. Accordingly, fast storage devices based on fast NVM lead to a rapid increase in the demand for diverse computer systems and environments (e.g., cloud platforms, web servers, and database systems) where they are expected to be used as primary storage. Despite the promised benefits provided by fast storage devices, modern file systems do not take advantage of the storage’s full performance. In this article, we analyze and explore existing I/O strategies in read, write, journal I/O, and recovery paths between the file system and the storage device. The analysis shows that existing I/O strategies are an obstacle to get maximum performance of fast storage devices. To address this issue, we propose efficient I/O strategies that enable file systems to fully exploit the performance of fast storage devices. Our main idea is to transfer requests from discontiguous host memory buffers in the file systems to discontiguous storage segments in one I/O request to get maximize I/O performance. We implemented our scheme to read, write, journal I/O and recovery operations in the EXT4 file system and the JBD2 module. We demonstrate the implication of our idea in terms of application performance through well-known benchmarks. The experimental results show that our optimized file system achieves better performance than the existing file system, with improvements of up to 1.54 $\times$ , 1.96 $\times$ , and 2.28 $\times$ on ordered mode, data journaling mode, and recovery, respectively.

Don’t make cache too complex: A simple probability-based cache management scheme for SSDs

Solid-state drives (SSDs) have recently become a common storage component in computer systems, and they are fueled by continued bit cost reductions achieved with smaller feature sizes and multiple-level cell technologies. However, as the flash memory stores more bits per cell, the performance and reliability of the flash memory degrade substantially. To solve this problem, a fast non-volatile memory (NVM-)based cache has been employed within SSDs to reduce the long latency required to write data. Absorbing small writes in a fast NVM cache can also reduce the number of flash memory erase operations. To maximize the benefits of an NVM cache, it is important to increase the NVM cache utilization. In this paper, we propose and study ProCache, a simple NVM cache management scheme, that makes cache-entrance decisions based on random probability testing. Our scheme is motivated by the observation that frequently written hot data will eventually enter the cache with a high probability, and that infrequently accessed cold data will not enter the cache easily. Owing to its simplicity, ProCache is easy to implement at a substantially smaller cost than similar previously studied techniques. We evaluate ProCache and conclude that it achieves comparable performance compared to a more complex reference counter-based cache-management scheme.

A Delayed Container Organization Approach to Improve Restore Speed for Deduplication Systems

Data deduplication has become necessary to improve the space-efficiency of large-scale distributed storage systems, as the global data have accumulated at an exponential rate and they have significant redundancy. However, the negative impact on restore performance is a main challenge for deduplication systems. One of the key reasons is that when restoring data, the low average useful data ratio (UDR) of containers wastes a considerable part of disk bandwidth to read useless data. This is mainly attributed to the uncontrollable compositions of containers. To solve this problem, we propose a new approach called Delayed Container Organization (DCO) to delay the construction of containers after accumulating some redundant data chunks in fast Non-Volatile Memory (NVM) devices to organize high-UDR containers. For example, data chunks in the intersection of some data segments can be organized together in one container to achieve both high deduplication ratio and high UDRs when restoring these related data segments. DCO is implemented in a prototype deduplication system. The experimental results indicate that compared with Capping, DCO promotes the average UDR of containers by 38.30 percent, improves the restore performance by a factor of 2.2, and achieves better space-efficiency and higher cost performance.

Physical Unbiased Generation of Random Numbers With Coupled Resistive Switching Devices

The resistive-switching memory (RRAM) is currently under consideration for fast nonvolatile memory thanks to its relatively low cost and high performance. A key concern for RRAM reliability is stochastic switching, which impacts the operation of the digital memory due to distribution broadening. On the other hand, stochastic behaviors are enabling mechanisms for some computing tasks, such as physical unclonable function (PUF) and random number generation (RNG). Here, we present new circuit blocks for physical RNG, based on the coupling of two RRAM devices. The two-resistance scheme allows to overcome the need of probability tracking, where the operation voltage must be tuned to adjust the generation probabilities of 0 and 1. Probability tests are proved successful for one of the three proposed schemes.

A Differential 2R Crosspoint RRAM Array With Zero Standby Current

Memory power consumption dominates mobile system energy budgets in scaled technologies. Fast nonvolatile memory devices (NVMs) offer a tremendous opportunity to eliminate memory leakage current during standby mode. Resistive random access memory (RRAM) in a crosspoint structure is considered to be one of the most promising emerging NVMs. However, the absence of access transistors puts significant challenges on the write/read operation. In this brief, we propose a differential 2R crosspoint structure with array segmentation and sense-before-write techniques. A 64-KB RRAM device is constructed and simulated in a 28/32-nm CMOS predictive technology model and a Verilog-A RRAM model. This design offers an opportunity to use RRAM as a cache for increasing energy efficiency in mobile computing.

Preface: Focus on Functional Oxides

AbstractOxide materials might form the basis for the next technological revolutions in fields such as electronics, photovoltaics or heterogeneous catalysis by enabling the production of inexpensive, high capacity and fast nonvolatile memories, neuromorphic computers and control systems, and efficient energy conversion devices. All these possible applications have in common that they promise to expand the limits of existing technologies by exploiting the inherent material‐level complexity of oxides. However, the enhanced opportunities of this added complexity come at the price of significantly greater difficulties in understanding the materials' properties and their implications. Among many, the peculiar and variable mixture of ionic and covalent bonding behavior and the relative ease of changing the oxygen content of many compounds lead to fascinating effects. Furthermore, a deep level of understanding of the materials properties and their relation to synthesis is crucial for eventual applications. In recent years, an enormous amount of work has been devoted to the development of new experimental and theoretical tools, which have enabled much improved understanding of oxide behavior. Materials science is now becoming able to predict and engineer the behavior of oxide materials and explore brave new worlds of functionality.The recent advances in functional oxide science and technology prompted us to hold the CECAM workshop on “Functional Oxides for Emerging Technologies” at the Bremen Center for Computational Materials Science in October 2013, and it was during the preparation for this workshop that the Focus Issue on functional oxides was conceived.The three Review@RRL articles introduce the reader to innovative, low energy electron microscopy [1], controllable electric conduction at oxide interfaces [2], and ionic switching based RRAM [3]. The 20 original Letters present exciting new research on the topics of transport properties [4], super‐reducible oxides [5], ferroelectricity [6], point defects [7], memory applications [8–10], bulk properties [11–14], interfaces [15–17], surfaces [18–20] and catalytic properties [21–23].We sincerely hope that you will find our collection of articles from the forefront of functional oxide research to be informative and that reading our Focus Issue inspires you to come up with more and even better ideas and insights. (© 2014 WILEY‐VCH Verlag GmbH & Co. KGaA, Weinheim)

Effects influencing electron and hole retention times in Ge nanocrystal memory structures operating in the direct tunneling regime

We present an experimental study of the electron and hole charging and discharging processes in the direct tunneling regime of Ge nanocrystals (NCs) embedded in the SiO2 of metal/oxide/semiconductor transistors. A specific aim was to verify theoretical predictions of very long hole retention times for Ge NCs embedded in SiO2 with thin (direct) tunneling barriers which could be harnessed for fast nonvolatile memories. While we observed longer electron retention times than theoretically predicted, we did not find experimentally the expected long hole retention times. To explain the discrepancies between our results and the theoretical predictions, several nonideal properties of the real Ge–NC:SiO2/Si system were investigated. In particular, a Ge NC preparation-induced increase in the volume trap density in the tunnel oxide and an increase in the trap density at the interface between the tunnel oxide and the Si substrate were detected. However, this moderate increase in the trap densities by about one order of magnitude (as compared to reference samples without any Ge NCs) does not provide a plausible explanation for the short hole retention times observed. Rather, an electron current into the NCs during hole retention seems to limit the retention times. This effect should already occur in the ideal Ge–NC:SiO2/Si system, thus preventing the non-volatile memory applications of Ge NC based devices operating in the direct tunneling regime.

Size effects in nanoscale ferroelectrics

Ferroelectrics are among the most advanced candidates of fast non-volatile memory materials. How do the properties of the commonly used perovskites such as PbTiO 3, Pb(Zr x Ti 1− x )O 3 (PZT) and BaTiO 3 change with size? Is there a fundamental limit showing up below which ferroelectricity irrevocably ceases? While the operating voltage as the predominant driving force for commercial applications shifted the thickness down to a few unit cells, ferroelectrics are now on the verge of true nanoscale integration of laterally confined structures. Top-down, bottom-up approaches and their combination provide samples far below 100 nm and indicate that the interaction of electrode and ferroelectric becomes increasingly relevant in terms of strain, screening of the depolarization field and fatigue resistance. As the qualitative understanding of nanoscale ferroelectricity advances the ferroelectric limit appears to be below 10 nm thus paving the road for further miniaturization.

Design considerations for MRAM

MRAM (magnetic random access memory) technology, based on the use of magnetic tunnel junctions (MTJs) as memory elements, is a potentially fast nonvolatile memory technology with very high write endurance. This paper is an overview of MRAM design considerations. Topics covered include MRAM fundamentals, array architecture, several associated design studies, and scaling challenges. In addition, a 16-Mb MRAM demonstration vehicle is described, and performance results are presented.