Density Of Fast Interface States Research Articles

Study of the Density of Interface States at the Insulator/In0.52Al0.48As Interface

The C–V characteristics of Au/Al2O3/In0.52Al0.48As and Au/SiO2/In0.52Al0.48As metal–insulator–semiconductor structures have been studied. It has been established that the fragmentary measurement of the C–V characteristics of InAlAs-based metal–insulator–semiconductor structures, in contrast standard registration method to at a constant voltage sweep rate, significantly weakens the effect of the hysteresis phenomena and allows one to record stationary curves. It is shown that the density of fast interface states calculated by the Terman method from such C–V characteristics slightly changes over the InAlAs band gap and amounts to (3–6) × 1011 and (1–3) × 1011 eV–1 cm–2 for MIS structures with Al2O3 and SiO2, respectively.

Slow Trap Properties and Generation in Al2O3/GeOx/Ge MOS Interfaces Formed by Plasma Oxidation Process

Understanding of slow traps near Ge MOS interfaces and reduction of the slow trap density are one of the most crucial issues for realizing Ge CMOS devices, in addition to the thin equivalent oxide thickness (EOT) and the low density of fast interface states (Dit). In this study, we examine the slow trap density and location in the Al2O3/GeOx/Ge interfaces fabricated by plasma oxidation. The slow trap density of Al2O3/GeOx/Ge MOS interfaces formed by pre-plasma oxidation (pre-PO) is compared with that of the MOS interfaces formed by post-plasma oxidation (post-PO). Also, the dependence of the slow trap density on the GeOx and Al2O3 thickness is systematically evaluated for the Al2O3/GeOx/Ge MOS interfaces formed by pre-PO. It is found that additional slow traps for electrons can be generated during the post-PO process near the conduction band side of Ge. It is also found that the main slow traps for electrons and holes in the Al2O3/GeOx/Ge MOS interfaces can locate near the GeOx/Ge interfaces and the Al2O3...

(Invited) MOS Interface Defect Control in Ge/III-V Gate Stacks

One of the most critical issues for realizing high performance Ge/III-V CMOS, which can be regarded as one of the promising device structures in the future technology nodes, is to establish the gate stack technologies simultaneously satisfying many requirements such as thin EOT, low interface state density (Dit), low slow trap density (Dtrap), high channel mobility and high gate insulator reliability. For this purpose, basic understanding of Ge/III-V MOS interfaces including physical origins of interface defects and the influence on channel mobility is indispensable. In order to realize low Dit, high channel mobility and thin EOT for Ge MOSFETs, we proposed an interfacial layer (IL) formation process employing ECR plasma post oxidation to form ultrathin GeOx through thin ALD Al2O3 [1, 2] or HfO2/Al2O3 [3]. By using the HfO2/Al2O3/GeOx/Ge gate stacks, Ge n- and p-MOSFETs (EOT of 0. 76 nm) with high electron (690 cm2/Vs) and hole (550 cm2/Vs) peak mobility were obtained. However, one of the most difficult challenges for the present GeOx-based ILs is the existence of high Dtrap [4, 5]. The slow traps can exist near GeOx/Ge interfaces, because the trapping characteristics are almost insensitive to the thickness of GeOx and Al2O3 [6]. Recently, inclusion of Y atoms into GeOx has been reported to effectively suppress Dtrap [7, 8]. We are currently working for the reduction in Dtrap by suing the ALD AlYO3/GeOx or Y2O3/GeOx interfaces [9, 10]. While the impact is still limited at present, further improvement in Dtrap is expected. For III-V MOS interface control, understanding of III-V MOS interface defects and establishment of the MOS interface defect control technologies have not been fully obtained yet. There still remain many issues, such as (1) higher Dit and Dtrap at InGaAs MOS gate stacks with Al2O3-based ILs than in Si and Ge MOS gate stacks (2) inferior MOS interface properties on Sb-based materials such as GaSb, GaAsSb and InGaSb (3) poor MOS gate stack reliability [5, 11, 12]. We studied the impact of ALD La2O3/InGaAs MOS interfaces on the performance of InGaAs MOSFETs. It was found that La2O3/InGaAs MOSFETs exhibit lower S. S. and lower carrier trapping properties, while have lower mobility than Al2O3/InGaAs MOSFETs because of higher fixed oxide charge density. Also, it was experimentally found that ALD La2O3 films with thermal budget lower than 300 oC have ferroelectricity in W/La2O3/InGaAs MOS and W/La2O3/W MIM structures. The steep slope characteristics due to the negative capacitance effect have been demonstrated in W/La2O3(15nm)/InGaAs MOSFETs [13]. We also found that BHF/HF pre-treatment is more effective for reduction of the fast interface state density at ALD Al2O3/InxGa1-xAs with higher In content (x=0.7 and 1) in comparison with conventional (NH4)Sy pre-treatment [14, 15]. It was suggested through the XPS analyses that the reduction in Dit is attributable to the dominance of As dangling bonds on Dit with higher In content and the effective passivation of oxygen atoms with these dangling bonds. For GaSb and GaAsSb MOS interface control, ultrathin InAs and InGaAs surface passivation layers have been found to be effective in reducing the fast interface state density [16, 17]. However, the detailed studies on further reduction in Dit and Dtrap and understanding of the relationship between the channel mobility and the interface properties are still strongly needed for Sb-based MOS devices. This work was partly supported by JST-CREST and the Grant in-Aid for Scientific Research through the MEXT (26249038). The authors would like to thank Drs. M. Yokoyama, H. Yamada and T. Yamamoto in Sumitomo Chemical Corporation, and Drs. M. Mitsuhara, H. Sugiyama, T. Hoshi and H. Yokoyama in NTT for their collaborations.

HYSTERESIS-LIKE FLATBAND VOLTAGE INSTABILITIES IN Al/Ta2O5-SiO2/Si STRUCTURES AND THEIR CONNECTION WITH J-V CHARACTERISTICS

Flatband and current-voltage instabilities in unstressed Al/Ta2O5-SiO2/Si structures were studied in details. It has been found that, after an initial run left on fresh samples, both C-V and J-V characteristics exhibit repeatable patterns. Precisely repeatable counterclockwise hysteresis-like loop in C-V characteristics occurs, while no significant hysteretic behaviour is observed in static J-V characteristics. The reduced instability in J-V characteristics is explained by mutual compensation of two opposite effects owing to the presence of trapped positive charges on slow traps in the interfacial SiO2-like layer: (i) flatband voltage shift and (ii) lowering of Fowler-Nordheim tunnelling barrier for holes injected from the Si substrate. Correct determination of equivalent oxide thickness and fast interface state densities requires using the C-V curves obtained during the runs right, because progressive trapping on slow states occurs during the runs left. Value of the oxide charge is to be determined using the value of the flatband voltage obtained from the run left (after an initial run right), since it corresponds to the state of empty slow traps.

Effect of Post Plasma Oxidation on Ge Gate Stacks Interface Formation

One of the key challenges for Ge gate stack is to achieve an improved interface quality between Ge and the high-K dielectric. In order to overcome this limitation, various interface treatments like ozone pre-gate treatment and ozone ambient annealing (1), nitridation of Ge surface (2),formation of a GeO2 layer between Ge and high-K dielectric using ECR plasma technique (3) and formation of an ultra-thin SiO2/GeO2bilayer have been tried. It has recently been reported that slot plane antenna(SPA) microwave plasma treatment helps to improve the EOT and enhances the oxide quality by reducing impurities and leakage current when the dielectric is exposed during or after deposition (4). Moreover SPA oxidation possesses the unique property of having low electron temperature, which makes it a very low damage process compared to other techniques,either inductively coupled plasma(ICP) and electron cyclotron resonance(ECR) plasma (5). In this study we investigated the impact of SPA plasma oxidation (SPAO) treatment in improving the interface quality when MOS capacitors were fabricated on 300mm p-type Ge substrates. SPAO plasma treatments were performed at different steps in the high-k deposition process. The substrate was initially subjected to a dry chemical oxide removal (COR) process. Subsequently, three different sets of samples were prepared with the exposure of SPAO plasma at following locations (Fig.1): CASE-1: SPAO plasma treatment after Al2O3(1nm)/ZrO2(3.5nm) deposition; CASE-2: SPAO plasma treatment was carried out in between Al2O3(1nm) and ZrO2(3.5nm) deposition; CASE-3: the Ge substrate was exposed to SPAO plasma treatment after COR and prior to Al2O3(1nm)/ ZrO2(3.5nm) layer deposition. Al2O3(1nm) and ZrO2(3.5nm) layers were deposited by atomic layer deposition. Capacitance-voltage at multi-frequencies,current-voltage and conductance measurements were performed at room temperature. Parameters like flatband voltage (Vfb), equivalent oxide thickness(EOT), interface state density(Dit),and leakage current were estimated accurately after quantum mechanical corrections and eliminating the series resistance effect. As shown in Fig. 2 lowest fast interface state density is achieved when SPAO plasma treatment was performed after Al2O3 and prior to ZrO2 deposition (CASE-2). A comparable Dit is also observed when plasma exposure was done after the entire gate stack deposition (CASE-1) (Fig.2). From different experimental results significant degradation to both the dielectric quality and interface was observed when SPAO is performed just after COR (CASE-3).

(Invited) MOS Interface Control Technologies for Advanced III-V/ Ge Devices

One of the most critical issues for III-V/Ge MOSFETs, which have been regarded as a promising CMOS structure under sub 10 nm regime, is formation of superior gate stacks satisfying the requirements of thin EOT, excellent MOS interface quality enabling high channel mobility and low S factor and high reliability. As a result, MOS interface control engineering is still of paramount importance. In this presentation, we focus on viable III-V/Ge gate stack technologies by using ALD high-k films for realizing these requirements.Two types of III-V semiconductors, InGaAs- and GaSb-based materials, have currently stirred a strong interest for n- and p-MOSFETs, respectively. In addition, the GaSb-based materials have become important for tunnelling FET application. As for InGaAs gate stacks, the insertion of 0.2-nm-thick ultrathin Al2O3 inter-layer can effectively improve the HfO2/InGaAs interface properties, resulting in 1-nm-thick CET HfO2/Al2O3/InGaAs MOS gate stacks with low gate leakage of 2.4×10-2 A/cm2 [1]. The resent studies have revealed that ALD La2O3 gate stacks can yield lower Dit than the Al2O3 ones [2, 3], indicating that La2O3 can be a promising high k material for III-V gate stacks. On the other hand, we have found that the InGaAs gate stacks using La2O3 only can include a large amount of slow traps. We present that ultrathin La2O3 interface control layers combined with Al2O3 and HfO2 can optimize both fast interface state density and slow trap density near the MOS interfaces.As for GaSb gate stacks, much higher Dit of Al2O3/GaSb MOS interfaces than that of Al2O3/InGaAs MOS interfaces severely degrades the device performance. Any thermal processing significantly is observed to increase Dit at Al2O3/GaSb interfaces [4]. It is shown that InAs passivation can effectively improve the MOS interface properties and the thermal stability [5]. As a result, 2.5-nm-thick InAs passivation can provide the peak hole mobility of 159 cm2/Vs for Al2O3/InAs/GaSb pMOSFETs [6]. In addition, surface treatment for InAs/GaSb hetero-structures by buffered HF, instead of conventional (NH4)2Sx, can further improve Dit at the MOS interfaces with Al2O3 [7].As for Ge gate stacks, we have presented ultrathin EOT Al2O3/GeOx/Ge and HfO2/Al2O3/GeOx/Ge gate stacks, fabricated by a plasma post oxidation method [8, 9]. HfO2/Al2O3/GeOx/Ge gate stacks with EOT of 0.76 nm have yielded (100) Ge p- and n-MOSFETs with high peak mobility of 546 cm2/Vs and 690 cm2/Vs, respectively [9]. We evaluated limiting factors of electron and hole mobility in Ge n- and p-MOSFETs. In a high Ns region the Ge MOS channel mobility is significantly degraded by surface roughness scattering as well as trapping of free electrons and holes into interface states inside the conduction and valence bands [10, 11]. The mobility in the high Ns region can be improved by reduction in surface roughness through a layer-by-layer plasma oxidation process [10]. Also, atomic Deuterium annealing can reduce Dit inside the bands, resulting in higher effective mobility [12]. However, the decrease in slow trap density for the Ge MOS gate stacks is a strong concern. While we observed the decrease in slow trap density near the valence band edge of Ge for ALD AlYO3/GeOx/Ge gate stacks formed by plasms post oxidation [13], the reduction in slow trap density for n-MOSFETs has not been obtained yet. Further optimization of Ge gate stacks is strongly needed for obtaining sufficient reliability in Ge CMOS.This work was partly supported by JST-CREST, the Grant in-Aid for Scientific Research through the MEXT (26249038), and the Innovation Research Project on Nano electronics Materials and Structures from NEDO. The authors would like to thank Drs. H. Yamada and O. Ichikawa in Sumitomo Chemical Corporation, and Drs. H. Yokoyama and M. Mitsuhara in NTT for their collaborations.

Interface Properties of 4H-SiC (<inline-formula> <tex-math notation="LaTeX">$11\bar {2}0$ </tex-math></inline-formula>) and (<inline-formula> <tex-math notation="LaTeX">$1\bar {1}00$ </tex-math></inline-formula>) MOS Structures Annealed in NO

Interface properties of 4H-SiC (112̅0) and (11̅00) walls, the absence of junction FET resistance, and the higher metal-oxide-semiconductor (MOS) structures annealed in nitric oxide are characterized by conductance, high-low, and C-ψ <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">s</sub> methods. Compared with 4H-SiC (0001) MOS structures, generation of very fast interface states by nitridation is much smaller in 4H-SiC (112̅0) and (11̅00). The effective mobility of planar MOSFETs fabricated on Al+-implanted p-body doped to 1×10 <sup xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">17</sup> cm <sup xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">-3</sup> is 10 <sup xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">3</sup> cm <sup xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">2</sup> /Vs on (11̅00), 92 cm <sup xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">2</sup> /Vs on (112̅0), and 20 cm <sup xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">2</sup> /Vs on (0001). The mobility-limiting factors are discussed on the basis of experimental results. The high channel mobilities for (112̅0) and (11̅00) MOSFETs can be correlated with the lower density of fast interface states generated by nitridation.

Study of the layer-substrate interface in nc-Si-SiO2-p-Si structures with silicon quantum dots by the method of temperature dependences of photovoltage

Layers grown by magnetron deposition of Si and SiO2 on a ptype silicon substrate and containing silicon nanocrystals in the oxide matrix have been studied by the method of temperature dependences of the capacitive photovoltage. The effect of the substrate orientation and natural oxidation preceding hightemper� ature annealing that results in the formation of Si nanocrystals in the SiO2 matrix on the layer-substrate inter� face characteristics is studied. The density of fast interface states trapping majority carriers was estimated. It is found that structural changes occur at the layer-substrate interface in the case of a (111) substrate and are caused by stresses appearing upon cooling. It was shown that natural oxidation of the deposited layer, preced� ing hightemperature annealing, causes an in crease in the charge trapped in the oxide.

Conduction, dielectric and interface properties of Al2O3 films on GaAs deposited by the e-beam evaporation technique

We report the results of resistivity, conduction mechanism, dielectric and interface properties of 750 and 1500 Å thick Al2O3 films deposited by the e-beam evaporation technique for surface passivation of GaAs-based devices. The typical near-zero bias leakage currents were varying from 85 fA to 6 pA corresponding to a resistivity variation of 3.6 × 1011 to 8.8 × 1011 Ω cm for 750 Å films. Similarly for 1500 Å films, the corresponding currents were varying from 85 fA to 3 pA indicating a resistivity variation of 1.5 × 1011 to 6.6 × 1012 Ω cm. The 750 Å films showed typically almost constant current densities of under 5 × 10−8 A cm−2 compared to varying (1.2–7.5)×10−8 A cm−2 for 1500 Å films. These observations were further corroborated by conduction mechanism results. Although the 750 Å films showed trends of Frenkel–Poole (FP) conduction for medium electric field strengths with lesser variation, the 1500 Å films also showed FP conduction but with more variation and scatter in data. Additionally, we report the results for the estimates of dynamic dielectric constant estimated from the FP conduction dominated region. The average value for 750 Å films was 2.17 compared to 4.43 for 1500 Å films. The static dielectric constant, interface properties were measured by the capacitance–voltage (CV) technique. The results indicate that a stable interface is possible by using the e-beam evaporation technique contrary to reports available in the literature. The range of values (including the data of both the films) obtained for dielectric constant, fixed charge density and fast interface state density were 3.6–4.6, (0.7–1.4) × 1012 cm−2 and (0.5–1) × 1013 cm−2 eV−1 respectively for these films.

Oxidant prepulsing of Ge (100) prior to atomic layer deposition of Al2O3: In situ surface characterization

We investigate the effects of H2O oxidant pulsing of Ge (100) substrates prior to Al2O3 atomic layer deposition (ALD) to synthesize metal-oxide-semiconductor devices. The prepulsing reduces the hysteresis in capacitance-voltage measurements from 490 to 30 mV at the flatband voltage and appears to reduce the density of fast interface states while causing a small increase in the midgap interface state density. Real-time x-ray photoelectron spectroscopy during prepulsing revealed the dynamic evolution of Ge–O bonding states and the formation of a surface layer with ∼70% hydroxyl termination which appears to produce a less defective interfacial region after subsequent Al2O3 ALD.

Improved interface properties of Al2O3 optical coatings on GaAs deposited by e-beam

We report the results of the improved surface passivation of GaAs using Al2O3 films deposited by the e-beam evaporation technique. A low and stable density of the negative fixed interface charge density of ∼1 × 1010 cm−2 and the fast interface state density of <3 × 1011 cm−2 eV−1 were obtained for the said films. Furthermore, using dc I–V measurements near zero bias, the typical leakage currents varying from 4 to 90 pA range were measured. The lowest near zero bias current was 0.5 pA which indicates a resistivity of 3.6 × 1011 Ω cm for our Al2O3 films, which is comparable to the values reported in the literature. To assess the uniformity of these films, a large number of devices from the 2 inch wafer were measured. It was observed that in general the shape of C–V curves remains the same except that there is only a 15% variation in accumulation capacitance across the whole wafer. This suggests a variation of dielectric constant from 4 to 4.5, which is indicative of acceptable film uniformity. Similarly, resistivity varied by three orders of magnitude from ∼3.0 × 108 to ∼3 × 1011 Ω cm.

Probing Point Defects in Stacks of Ultrathin High-k Metal Oxides on Semiconductors by Electron Spin Resonance: The Si/HfO2 vs the Ge/HfO2 System

Combined electron spin resonance and electrical analysis of (100)Si/HfO2 and (100)Ge/HfO2 interfaces reveals dramatic differences in their interface defect properties. No interfacial Ge dangling bond type defects could be revealed. The observed paramagnetic defects do not correlate with the slow acceptor states dominating the Ge/insulator trap spectrum, and are resistant to passivation. The dangling bond type defects observed, upon hydrogen detachment, at the (100)Si/HfO2 interfaces are the trivalent Si defects common for Si/SiO2 interfaces, Pb0 and Pb1 centers. The density of the Pb0 is higher than in the (100)Si/SiO2 structures and is sensitive to the deposition process. However, the density can be significantly reduced by annealing of the Si/HfO2 structures in O-containing ambient, likely through re-establishing the Si/SiO2 interface. The density of fast interface states closely follows the variations in the Pb0 center density, suggesting it as the dominant contribution to the fast interface states.

Si dangling-bond-type defects at the interface of (100)Si with ultrathin HfO2

Electron spin resonance analysis of (100)Si/HfO2 interfaces prepared by chemical vapor deposition of the oxide using three chemically different precursors reveals that the trivalent Si defects common for Si/SiO2 interfaces—Pb0 and Pb1 centers—are universally observed upon hydrogen detachment. The density of the Pb0 is higher than in the (100)Si/SiO2 structures and is sensitive to the deposition process. However, the density can be significantly reduced by annealing of the Si/HfO2 structures in O-containing ambient, likely through re-establishing the Si/SiO2 interface. Also, the Pb-type centers can be entirely passivated by hydrogen already at 400 °C. The density of fast interface states closely follows the variations in the Pb0 center density, suggesting it as the dominant contribution to the fast interface states.

Electron Spin Resonance Characterization of Defects at Interfaces in Stacks of Ultrathin High-κ Dielectric Layers on Silicon

ABSTRACTElectron spin resonance (ESR) analysis of (100)Si/SiOx/ZrO2, (100)Si/Al2O3 and Si/HfO2 structures with nm-thin dielectric layers deposited by different chemical vapor deposition procedures reveals, after hydrogen detachment, the presence of the trivalent Si dangling-bond-type centers Pb0, Pb1 as prominent defects in all entities. This Pb0, Pb1 fingerprint, generally unique for the thermal (100)Si/SiO2 interface, indicates that the as-deposited (100)Si/metal oxides interface is basically Si/SiO2-like. Though sensitive to the deposition process, the Pb0 density is found to be substantially larger than in standard (100)Si/SiO2. As probed by the Pb- type center properties, the Si/dielectric interfaces of all structures are under enhanced (unrelaxed) stress, typical for low temperature Si/SiO2 growth. Standard quality thermal Si/SiO2 properties in terms of Pb signature may be approached by appropriate annealing (≥ 650°C) in vacuum in the case of (100)Si/SiOx/ZrO2. Yet, O2 ambient appears required for Si/Al2O3 and Si/HfO2. It appears that Si/high-κ metal oxide structures with device grade quality interfaces can be realized with sub-nm thin SiOx interlayers. The density of fast interface states closely matches the Pb0 density variations, suggesting the center as the dominant fast interface trap. They may be efficiently passivated in H2 at 400 °C.

Electrical characterization of ultrathin oxides of silicon grown by N2O plasma assisted oxidation

The ultrathin (2.0–3.5 nm) oxides of silicon have gained renewed importance in view of ultra large scale integration (ULSI) of the silicon devices. In the present investigation, the ultrathin oxides are grown on (100) oriented p-type single side polished silicon using N20 plasma assisted oxidation in a PECVD reactor at 200°C. The oxide growth as a function of oxidation time is studied. The oxidation growth conforms to the reaction limited regime. In order to understand the electrical quality of Si/ultrathin SiO2 interface, Al-thin SiO2-Si tunnel capacitors are fabricated and their capacitance-voltage (C-V) and current-voltage (I–V) characteristics are studied. The effect of annealing on these oxides (termed as “post oxidation annealing”) has also been studied. The C-V characteristics of tunnel capacitors with “as grown” oxide showed a frequency dependence, possibly due to the presence of large fast interface state density. These fast interface states are observed to decrease with increasing oxidation time. The tunnel capacitors that the oxides undergone “post oxidation annealing” (POA) at 350°C in N2 ambient for 20 minutes have shown practically no frequency dependence of the C-V characteristics; this observation along with the data on I-V characteristics confirms that POA reduces the interface state density considerably. The forward and reverse currents of POA capacitors are observed to decrease considerably indicating the reduction in the trap assisted tunneling transport process across the tunnel insulator.

On the number of fast interface states of standard CMOS technologies

In recent publications about MOS devices, a fast interface state (IS) density has been found for standard thermal oxides, which is much higher than previously expected. This high number of fast interface states was shown to have a strong impact on the effective mobility in state of-the-art MOSFET's with high channel doping concentrations. This calls into question the validity of the standard procedure for mobility data extraction and of all device simulations in which fast interface states are neglected. In contrast to those results our investigations of standard MOS devices fabricated by three different manufactures do not yield such a high interface state density. Our results show that fast interface states can still be neglected for modeling state-of-the-art CMOS technologies and previously extracted mobility data are still valid although fast interface states have been ignored.

Non-quasistatic simultaneous HF/LF-CV measurements for rapid characterization of MOS structures

We report rapid, non-quasistatic CV (capacitance–voltage) measurements for a comprehensive characterization of MOS structures. The purpose is to speed up and simplify the characterization of simple MOS test structures in a process line environment. This approach replaces the time-consuming successive application of several CV tools by one accurate and rapid technique. Contrary to quasistatic CV measurements, the use of faster gate voltage ramp rates enables a drastic reduction of the total time for the data acquisition for the characterization of high quality silicon MOS structures. The simultaneous measurement of the high frequency (HF)- and the low frequency (LF)-MOS capacitance from deep depletion toward accumulation in a non-quasistatic mode permits the determination of the density of fast interface states D it( E) from midgap to the flatband energy level, the generation lifetime τ g( x g), and the doping profile N( x d). The doping profile is corrected for voltage stretch out due to the generated inversion charge and recharges of interface traps. To speed up the relaxation process for the determination of the generation lifetime, a gate voltage ramp was used after pulsing into deep depletion, instead of a constant voltage. Driving the MOS capacitor from deep depletion toward accumulation with a linear gate voltage ramp causes a rapid relaxation of the depleted MOS capacitor to the equilibrium state. To calculate the generation active depletion width x g, the equilibrium depletion width in inversion x f must be known. x f can be conveniently determined from the sharply marked equilibrium point at the transition from generation to recombination. Consequently no extra measurement time is required for the determination of x f. The technique proposed is also applicable for the characterization of MOS capacitors with very thin oxides below 10 nm.

Stress induced degradation features of very thin gate oxides

The degradation features of very thin gate oxide after Fowler–Nordheim stress have been studied. Bulk oxide, cathodic and anodic regions have been analysed from the charge build-up point of view, as well as the stress induced generation of Si/SiO 2 fast interface state density. A physical interpretation of experimental results has been proposed, involving two types of stress induced positive charge building up at interface regions. It is shown that a critical oxide thickness exists, under which the degradation mechanisms could be considerably different.

Characterisation of Dielectric Damage in MOS Capacitors by a New Current Transient Measurement Technique

AbstractWith the requirement for reduced dielectric thickness and improved durability in silicon MOS devices, new growth techniques and material composition are constantly being developed. An important part of this development is the electrical characterisation of the dielectric material and in particular the properties of the dielectric-semiconductor interface.This paper presents a study of damage caused to the dielectrics of MOS capacitors which have been subjected to either constant current stressing or RF plasma etching. The density and energy position of fast interface states and fixed oxide charges were measured using standard capacitance-voltage techniques. These results are then compared with a new current transient technique, which has been developed to measure slow interface states having a range of response times. This new technique steps the surface Fermi level through the silicon bandgap and the resulting current transients provide information on trap response times at each energy position. The response time can then be related to the tunneling distance from the trap to the bulk silicon. This technique has provided important information about the energies and response times of traps generated in damaged dielectrics, and should prove to be a useful tool for damage evaluation in the future.

Surface potential dependence of interface state passivation in metal-tunnel oxide-silicon diodes

Interface state passivation during de biased post metallization annealing at ∼ 350°C was studied in very thin oxide, ∼ 31 Å, aluminum-tunnel oxide- 〈1 1 1〉 p-type silicon structures. Capacitance-voltage and tunnel current- voltage measurements were used after the anneals to monitor the passivation of interface states. It was found that the passivation process of interface states in the as-manufactured devices is directly dependent on the surface potential but not on the average oxide electric field or the tunnel current. A negative gate voltage increases the passivation rate, whereas a positive gate voltage decreases it as compared to unbiased annealing. The interface states resemble P b centres, which are dangling bonds on trivalently bonded Si atoms at the interface. The present observations are found to agree well with theoretical calculations by Edwards (1991) on the surface potential dependence of the passivation of P b centers by H 2. It is possible to find an optimum time and voltage for annealing, roughly 1000 s and − 1.2 V in our case, for simultaneously minimizing the dc tunnel current, flatband voltage shifts and the density of fast interface states in these diodes.