Fast Fourier Transform Size Research Articles

P-LDPC coded image transmission with OFDM over underwater acoustic channel

Underwater environment is still an attractive area to explore and exploit by human beings. However, underwater characteristics limit communications due to harsh channel conditions, and efficient channel codes are essential to deploy. This study presents an underwater system based on protograph low-density parity check (P-LDPC) codes and orthogonal frequency division multiplexing (OFDM) for image transmission. The system proves a successful reconstruction of P-LDPC coded images with different levels of comparison. The performance of the proposed system is evaluated using nine objective measures such as bit error rate (BER) and peak signal to noise ratio (PSNR). Firstly, the proposed system performance is evaluated with different block lengths of P-LDPC code. Then, the implemented system shows a coding gain of approximately 1.75 dB for applying P-LDPC when compared to polar with cyclic redundancy check at 0.0001 BER. Additionally, image subjective assessment is obtained to demonstrate how the P-LDPC outweighs polar and turbo product codes in terms of estimated image quality. Lastly, further investigation is performed to study the effect of varying fast Fourier transform (FFT) size and cyclic prefix (CP) length on image reserved quality. The results show that the received image is better reconstructed for larger FFT sizes since that produce longer CP and symbol duration, and that in turn helps the system to combat the multipath fading introduced by the underwater channel.

LoFFT: Low-Voltage FFT Using Lightweight Fault Detection for Energy Efficiency

Operating at reduced voltage is an effective technique for improving the energy efficiency of computing. However, the approach is constrained by its exacerbated sensitivity to Process, Voltage, and Temperature (PVT) variations, which under throughput constraints challenges finding the energy minimizing voltage-frequency operating point. Commonly utilized design approaches for adaptive voltage scaling are based on timing slack measurement or speculation techniques that require adding extra hardware, e.g., Error Detection Sequence (EDS) circuits, that substantially increase the design complexity, and are not applicable for already fabricated designs. In this paper, instead of circuit-level techniques, a low-cost algorithmic error detection method is proposed as the enabler for reduced voltage operation of Fast Fourier Transform (FFT) accelerators.Without requiring neither gate-level nor circuit-level modifications, the method works based on an intrinsic property of the Fourier transform, i.e., Parsevalfs identity. The method is demonstrated on a System-on-Chip (SoC) that integrates a Field-Programmable Gate Array (FPGA) made to operate at reduced voltages. The fault detection capability is profiled using the demonstration test bench, implemented both as software and as hardware. In the experiments, a.43% reduction in power consumption was achieved without sacrificing the throughput and reliability. The overheads of the proposed fault detection approach scale sub-linearly with respect to FFT size and are ≤10% for 1024-point FFT.

A 60-Mode High-Throughput Parallel-Processing FFT Processor for 5G/4G Applications

This article presents a 60-mode high-throughput parallel-processing memory-based fast Fourier transform (FFT) processor for fifth-generation (5G)/4G applications. The proposed architecture adopts a multi-FFT parallel-processing scheme to significantly reduce the idle computation cycles of small point FFT due to the deep pipeline. The proposed scheme can narrow the throughput gap between different FFT sizes. In conjunction with the parallel processing scheme, a configurable 16-parallelism butterfly unit is proposed to support a maximum of five radix-3, four radix-4, three radix-5, two radix-8, or one radix-9 operation in one cycle. Furthermore, this article demonstrates conflict-free memory access with a parallel method based on fusion shift combined with a hopping-based method to simplify the data arrangement at different radix stages. According to the orthogonal frequency division multiplexing (OFDM) application characteristics, our processor is extended to support many additional commonly used functions, such as zero padding, cyclic prefix insertion, and 7.5-kHz frequency shift, which can simplify the system call in 5G/4G applications. The FFT processor has been successfully integrated into a small-cell base station baseband system-on-chip (SoC) and taped out at the TSMC 12-nm technology. The implementation result reveals that the die area of the proposed processor is 0.374 mm2 with a power consumption of 235.5 mW at 1 GHz, and the processor supports a balanced throughput up to 3.92 GS/s at all 60-mode, which is better than that of the state-of-the-art (SOTA) designs.

Design Space Exploration of Single-Lane OFDM-Based Serial Links for High-Speed Wireline Communications

The 4-level pulse-amplitude modulation (PAM-4) with an analog-digital converter (ADC)-based receiver (RX) has become the most commonly employed modulation for ultra-high-speed serial links with the data rate above 100 Gb/s. To support the data rate of 200 Gb/s, orthogonal frequency division multiplexing (OFDM) has been studied recently as one of the possible modulation schemes in the next-generation serial links. The OFDM can feature high bandwidth efficiency without increasing the equalization complexity, leading to a reduced maximum signal amplitude attenuation and lower required DAC/ADC conversion rates given sufficient DAC/ADC resolutions such that the BER is not primarily limited by the data converters’ resolution. This paper presents system-level modeling results of OFDM-based wireline serial links, with a particular emphasis on the impacts of the fast Fourier transform (FFT) processor’s tap count on the serial link performance. The relationship among the cyclic prefix (CP), FFT tap count, and the link bit-error-rate (BER) are thoroughly explained. The analysis explains that the power consumption of a partially-serial FFT processor improves with a larger kernel FFT size, and simulation results show that the BER performance improves with the FFT size where an optimal CP length exists given the FFT size.

Design and Implementation of AGU based FFT Pipeline Architecture

Present it is most needful task to get various applications with parallel computations by using a Fast Fourier Transform (FFT) and the derived outputs should be in regular format. This can be achieved by using an advanced technique called Multipath delay commutator (MDC) Pipelining FFT processor and this processor will be capable to perform the computation of a different data streams at a time. In this paper the design and implementation of AGU based Pipelined FFT architecture is done Caluclation of a butterfly is done within 2 cycles by the instructions proposed. A Data Processing Unit (DPU) is employed in this pipeline architecture and supports the instructions & an FFT Adress Generation Unit (FAGU) caluclates butterfly input & output data adresses automatically. The DPU proposed sysyem requires less area compared to commericial DSP chips. Futhermore, the proposed FAGU reduces the number of FFT computation cycles. The FFT design architecture will have real data paths. With various FFT sizes, different radix & various parallesim levels, the FFT can be mapped to the pipeline architecture. The most attractive feature of the pipelined FFT architecture is it consists of bit reversal operation so it requires little number of registers and better throughput.

2-D Systolic Array architecture of CBNS based Discrete Hilbert Transform Processor

This paper proposes an optimized design of Discrete Hilbert Transform (DHT) processor using Complex Binary Number System (CBNS). The conventional implementation of DHT based on the “divide and conquer” approach involves two separate computational units for the real and imaginary parts, which requires a large silicon area and increases the path delay. In contrast, incorporation of CBNS in transformation techniques facilitates complex-valued signal processing through a single computational unit.The CBNS-DHT processor has been designed using the standard computational method of Fast Fourier Transform (FFT). The 2-D Systolic Array architecture along with a novel processing element has been proposed for CBNS based Complex-valued FFT (CFFT) and Inverse FFT (CIFFT) computations. The architecture of CBNS-CFFT/CIFFT has been extended to develop the CBNS-DHT processor on the Zynq-7000 family, XC7Z020-CLG484 FPGA platform. A comparative performance analysis of CBNS-DHT and Normal Binary Number System (NBNS)-DHT highlights the efficiency of CBNS-DHT in terms of VLSI parameters — silicon area, path-delay and memory utilization. CBNS-CFFT shows significant improvement in path delay and area consumption as compared to NBNS-CFFT for both Twiddle Factors and FFT size, which proves that CBNS based CFFT and DHT processor design is more efficient in terms of speed and area requirements.

Low-Complexity Doppler Compensation Algorithm for Underwater Acoustic OFDM Systems With Nonuniform Doppler Shifts

The Doppler effect severely degrades the orthogonality of orthogonal frequency division multiplexing (OFDM) systems, and is a severe problem in the underwater acoustic (UWA) communications, leading to nonuniform Doppler shifts for all subcarriers. In order to alleviate Doppler effect, resampling technique by oversized fast Fourier transform (FFT) can achieve fast and accurate resampling in frequency domain. Nevertheless, the accuracy of this conventional FFT based approach depends on the FFT size, which in turn increases receiver complexity. In order to overcome this problem, the Doppler compensation model in frequency domain is simplified by Taylor series expansion in this letter. Based on the simplified model, we propose the Doppler compensation algorithm by using FFT and interpolation to achieve higher compensation accuracy. Simulation results demonstrate that the proposed algorithm shows very similar bit error rate (BER) performance with that of Chirp Z-transform (CZT) based method. However, the complexity of our proposed algorithm is about half of CZT based method. Further, our proposed low-complexity Doppler compensation algorithm can also be applied to the sampling frequency offset (SFO) correction in terrestrial OFDM communication systems.

The Architectural Optimizations of a Low-Complexity and Low-Latency FFT Processor for MIMO-OFDM Communication Systems

Fast Fourier Transform (FFT) processor is a paramount signal processing component in MIMO-OFDM wireless communication systems. Furthermore, novel applications introduced in 5G incur much more rigorous requirements for FFT designs including complexity, latency, and re-configurability. This paper presents the VLSI architecture design and circuit implementation of a FFT processor that is jointly optimized for low-latency, low-complexity, and configurability. Specifically, the proposed architecture processes two data streams concurrently and supports power-of-two FFT sizes from 64 to 2048 symbols. Moreover, a novel data-processing sequence is presented so that data streams are processed in a time-multiplexing manner and an efficient hardware-sharing architecture can be designed. In addition, a highly efficient I/O reorder mechanism is proposed so that the memory elements are shared between processing stages and the efficiency for utilizing memory components is enhanced. Based on the architectural optimizations, two FFT processors are realized. The ultra-low latency design achieves a latency of 4 μs with 41% area reduction compared to the comparable designs. On the other hand, the ultra-low complexity structure achieves a latency of 25 μs with 24% area reduction compared to the state-of-the-art implementations.

Sampling frequency offset compensation in non-Hermitian symmetric optical OFDM

Non-Hermitian symmetric optical orthogonal frequency-division multiplexing (NHS-OFDM) can make the best use of fast Fourier transform (FFT) functions. Hence, hardware implementation of NHS-OFDM has a low complexity when maintaining the same bandwidth granularity. And the similar peak-to-average power ratio (PAPR) and bit error rate (BER) performances can be obtained in comparison with the conventional Hermitian symmetric optical orthogonal frequency-division multiplexing (HS-OFDM). However, the sampling clock frequency offset (SFO) between digital-to-analog converters (DAC) and analog-to-digital converters (ADC) always exists in asynchronous HS/NHS-OFDM systems. It will degrade BER performance seriously without compensation. In this paper, the mechanism of SFO in NHS-OFDM is analyzed and discussed. The inter-symbol differential detection (ISDD) with residual phase compensation (RPC) is applied for SFO compensation (SFOC) in the NHS-OFDM system. Moreover, enhanced residual phase estimation (ERPE) is also proposed to improve the tracking speed and accuracy of residual phase estimation. The optimal FFT size for NHS-OFDM is first identified in both additive white Gaussian noise (AWGN) channel and a 20-km standard single-mode fiber (SSMF) link. The BER performance of the ISDD with RPC/enhanced RPC (ERPC) enabled HS/NHS-OFDM is investigated by means of both numerical simulation and offline experiments. With the help of the ISDD with RPC/ERPC methods, the SFO can be compensated. Also, a slight improvement in BER performance can be achieved with the ERPC method compared to the RPC method. And the BER performance penalties can be ignored in the presence of SFO up to 200 ppm.

Selecting FFT Word Length for an OFDM Receiver That Supports Undersampling

In this paper, we focus on Orthogonal Frequency Division Multiplexing (OFDM) transceivers where undersampling is employed by the receiver Analog/Digital Converter (ADC) when sparse information is exchanged. Several Fast Fourier Transform (FFT) symmetry properties are exploited to allow the substitution of specific input values by others that have already been sampled by the ADC. Several architectures have been proposed in the literature for efficient FFT implementations in terms of power, speed and hardware resources. The FFT input/output values, twiddle factors, etc., are complex numbers with their real and imaginary parts being represented using fixed point format. A tradeoff has to be made between rounding error and complexity. The optimal minimum FFT word length is investigated by combining the undersampling and the rounding error. A configurable new FFT architecture has been developed in hardware description language to test the error model with various FFT sizes, word lengths and Quadrature Amplitude Modulations (QAM). A system designer can take into account the sparseness of the input data and define the desired rounding and undersampling error relation. Τhe developed error model would then predict the required word length and ADC resolution with average Root Mean Square Error (RMSE) less than 1.

PARALLEL PIPELINED MULTI RADIX VARIABLE LENGTH FAST FOURIER TRANSFORM ARCHITECTURE

There is an enormous demand for high speed data communication or high speed internet using Long Term Evolution (LTE) or LTE-Advanced communication methods. To achieve the high speed data rate in the receiver side, it is necessary to achieve high throughput in the Fast Fourier transform (FFT) architecture. Hence there is demand to improve the throughput of the FFT architectures used for high speed data communication. The FFT architecture is designed and optimized for LTE-A applications. However, the high throughput has been achieved by sacrificing hardware resources of the Field Programmable Gate Array (FPGA). Many fixed and variable length FFT processors are proposed by the researchers with improved performance focusing either on algorithmic modifications, novel architectural optimizations or radix selection. Among these FFT processors, the goal and main objectives of this paper are: 1. To design and implement a pipelined FFT architecture to give high throughput for LTE-A MIMO applications 2. To develop an intellectual property (IP) core for FFT computation with variable FFT size 3. To propose a parallel implementation to increase the performance of LTE-A baseband processing system. In an Orthogonal Frequency Division Multiplexing (OFDM) baseband communication system, FFT operation is one of the highest computationally serious tasks which directly influence the communication system performance factor. The baseband hardware has to be capable as well as efficient enough to calculate FFT in specific timing restrictions. Thus, the parallel pipelined multi radix Variable Length FFT architectures for LTE-A Multiple-Input-Multiple-Output (MIMO) applications have been designed. The proposed FFT architecture delivers a throughput of 550 MSPS at the maximum clock rate of 550 MHz. The proposed FFT support the FFT length of 64, 128, 256, 512, 1024 and 2048 for LTE-Advanced MIMO standard. The proposed FFT architecture has been implemented in Xilinx Artix-7 FPGA device and the performance metrics have been analysed. Even though the proposed FFT architecture consumes additional Block-RAMs (BRAM) and quite an amount of Xilinx-Xtreme Digital Signal Processor (DSP)/ DSP48 resources, the Power Delay Product (PDP) of the proposed FFT is excellent compared to the existing FFT architectures. The proposed multi radix mixed 2/3/5 parallel pipelined 2048 point FFT architectures exhibits very less latency of 11.382 µs at 550 MHz clock frequency compared to the existing system with the latency of 56.88 µs at 200 MHz clock frequency. Moreover, the designed FFT architecture utilizes 96 Xilinx Xtreme DSP blocks 25040 clock cycles to complete the FFT operation with an excellent throughput of 2200 MSPS with FFT computation time of 45.528 µs at the clock frequency of 550 MHz for the 4x4 MIMO- OFDM architecture. Therefore, the designed FFT provides high throughput rate in order to meet the modern wireless standard specifications. The proposed FFT architecture outperforms well in terms high throughput, low latency and better PDP with extra hardware as trade-off for both for Single FFT and for MIMO technology.

Design of an Area-Efficient Various N-point Support radix-2/22 FFT using Modified Butterfly Units

Fast Fourier Transform (FFT) acts as an element in the high-speed signal processing application, which involves the following subsequent operations, namely complex addition, complex subtraction and complex multiplication. Due to the complex multiplication operation, the FFT structures lead to more hardware demand. Hence, this work introduces an area-efficient various N-point support radix-2 and radix-22 FFT structure by using proposed modified butterfly units and radix-2/22 butterfly unit. The proposed modified butterfly units are used to reduce the number of complex multipliers effectively. For this reason, it is using for certain conditions in FFT design instead of existing radix-2/22 butterfly unit. Further, the proposed design supported to perform various size of FFT in a single architecture without increasing the extra element demand. Moreover, the proposed FFT structure designed and implemented using a Xilinx Virtex-6 Field-Programmable Gate Array (FPGA) device (6vcx75tff484-2) and Cadence tool with 45nm CMOS technology. The implementation results demonstrate that the proposed N-point (N=16, 32 and 64) DIF-FFT design attains the less hardware complexity when compared with existing multi-mode FFT design. Then the proposed area-efficient 16-point, 32-point and 64-point radix-2 FFT architectures reduce the total area by 20.99%, 11% and 4.9% respectively. As well, the proposed area-efficient 16-point, 32-point and 64-point radix-22 FFT architectures reduce the total area by 32%, 19% and 11% respectively.

Low-Complexity Joint 2-D DOA and TOA Estimation for Multipath OFDM Signals

The multiple signal classification (MUSIC) algorithmis computationally expensive in the application to joint two-dimensional (2-D) direction-of-arrival (DOA) and time-of-arrival (TOA) estimation based on uniform circular array (UCA) using orthogonal frequency-division multiplexing (OFDM) signal. This letter proposed an efficient way to compute the 3-D spatial-temporal spectrum. We extended the manifold separation technique, by which we obtained the 3-D discrete Fourier transform (DFT) form of the spectrum. On this basis, we proposed two 2-D DOA and TOA estimators called FFT-MUSIC and Two-step FFT-MUSIC. The former computed the spectrum by large size fast Fourier transform (FFT) to reduce the grid error in searching DOAs and TOAs. The latter roughly located the DOAs and TOAs by relatively small size FFT, followed by the subspace-based technique for a fine-grained searching within a local grid. Simulation results showed that both estimators can reduce the computation cost by one to two orders of magnitude, as compared to their conventional counterparts, while maintaining a similar accuracy.

Design and Implementation of Flexible and Reconfigurable SDF-Based FFT Chip Architecture With Changeable-Radix Processing Elements

In this paper, we propose a flexible and reconfigurable changeable-radix fast Fourier transform (FFT) hardware architecture. It aims to support 48 different FFT sizes and up to 4096 FFT points, which are defined in current 3GPP-LTE communication system. The built-up design structure is primarily constructed on a radix-52 basis of single-path delay feedback FFT and up to 18 various changeable radixes of FFT processing. A design technique of switchable FIFO usage approach is developed to efficiently manage FIFO arrangement for 48 FFT modes. In addition, a design technique of coarse and fine rotating is designed to effectively reduce twiddle-factor circuit area. By using TSMC 40-nm CMOS technology, an FFT ASIC implementation only has a core area occupation of 0.414 mm2 and consumes 49.8 mW in average at maximal working frequency of 526.32 MHz. This innovative design work is competitive as compared to current state-of-the-art works, especially in terms of circuit area cost and power/energy performance evaluation.

On the Impact of Fixed Point Hardware for Optical Fiber Nonlinearity Compensation Algorithms

Nonlinearity mitigation using digital signal processing has been shown to increase the achievable data rates of optical fiber transmission links. One especially effective technique is digital back propagation (DBP), an algorithm capable of simultaneously compensating for linear and nonlinear channel distortions. The most significant barrier to implementing this technique, however, is its high computational complexity. In recent years, there have been several proposed alternatives to DBP with reduced computational complexity, although such techniques have not demonstrated performance benefits commensurate with the complexity of implementation. In order to fully characterize the computational requirements of DBP, there is a need to model the algorithm behavior when constrained to the logic used in a digital coherent receiver. Such a model allows for the analysis of any signal recovery algorithm in terms of true hardware complexity which, crucially, includes the bit-depth of the multiplication operation. With a limited bit depth, there is quantization noise, introduced with each arithmetic operation, and it can no longer be assumed that the conventional DBP algorithm will outperform its low complexity alternatives. In this work, DBP and a single nonlinear step DBP implementation, the \textit{Enhanced Split Step Fourier} method (ESSFM), were compared with linear equalization using a generic software model of fixed point hardware. The requirements of bit depth and fast Fourier transform (FFT) size are discussed to examine the optimal operating regimes for these two schemes of digital nonlinearity compensation. For a 1000 km transmission system, it was found that (assuming an optimized FFT size), in terms of SNR, the ESSFM algorithm outperformed the conventional DBP for all hardware resolutions up to 13 bits.

Doppler Shift Estimation and Compensation in High Speed MIMO-OFDM VANETs

Abstract: Motions in vehicular ad hoc networks (VANETs) cause Doppler Frequency Shifts (DFSs) which are described by frequency dispersions in the received signals. Although the VANETs channels are perturbed by noise sources such as multipath delay spread, shadowing and interference, a DFS due to the high speed vehicular mobility is a major cause of high bit-error rates (BER). Schemes for estimating and compensating DFSs in VANETs with medium to high speed mobility have been reported in the recent literature. However, significant computational complexity with some methods configured in MIMO-OFDM systems has rendered them non-attractive in full-scale deployment of high speed VANETs. The research question that remains unanswered is what scheme can be proposed to estimate and compensate for the DFS at a reduced computational complexity when MIMO-OFDM systems and high speed mobility conditions are considered? This paper answers this question by proposing a pilot-assisted DFS estimator and compensator based on the general complex exponential basis expansion matrix (BEM) modelling. The proposed method realizes a low computational complexity DFS estimator and compensator in the linear order of the Fast Fourier Transform (FFT) size as compared to the DFS uncompensated MIMO-OFDM systems whose computational complexity has been noted to be in a quadratic order of the FFT size. Numerical results indicate that the proposed BEM method demonstrates a better BER performance than the conventional approaches under the same MIMO configurations for moderately high vehicular speeds.

A Variable-Size FFT Hardware Accelerator Based on Matrix Transposition

Fast Fourier transform (FFT) is the kernel and the most time-consuming algorithm in the domain of digital signal processing, and the FFT sizes of different applications are very different. Therefore, this paper proposes a variable-size FFT hardware accelerator, which fully supports the IEEE-754 single-precision floating-point standard and the FFT calculation with a wide size range from 2 to 220 points. First, a parallel Cooley–Tukey FFT algorithm based on matrix transposition (MT) is proposed, which can efficiently divide a large size FFT into several small size FFTs that can be executed in parallel. Second, guided by this algorithm, the FFT hardware accelerator is designed, and several FFT performance optimization techniques such as hybrid twiddle factor generation, multibank data memory, block MT, and token-based task scheduling are proposed. Third, its VLSI implementation is detailed, showing that it can work at 1 GHz with the area of 2.4 mm2 and the power consumption of 91.3 mW at 25 °C, 0.9 V. Finally, several experiments are carried out to evaluate the proposal’s performance in terms of FFT execution time, resource utilization, and power consumption. Comparative experiments show that our FFT hardware accelerator achieves at most $18.89\times $ speedups in comparison to two software-only solutions and two hardware-dedicated solutions.

VLSI Design and Implementation of Reconfigurable 46-Mode Combined-Radix-Based FFT Hardware Architecture for 3GPP-LTE Applications

This paper presents a reconfigurable fast Fourier transform (FFT) hardware architecture, supporting 46 different FFT sizes defined in 3GPP-LTE applications. Our proposed design concept is mainly based on combined radix-5, radix-32, and radix24 single-path delay feedback FFT design approaches. In addition, in order to elaborate our hardware design, we also develop three design techniques, such as reconfigurable processing kernel with seven types (RPK-ST), efficient FIFO management scheme, and single-table approximation method. In an ASIC implementation with TSMC 40-nm CMOS technology, our 46-mode reconfigurable FFT chip only occupies a core area of 0.36 mm2, dissipates 48.46 mW, and operates up to clock frequency of 500 MHz. As compared with the other state-of-the-art works, our work delivers high-quality design results in the aspects of area- and energy-related performance indexes, providing a constructive FFT design prototyping for 3GPP-LTE systems.

Reconfigurable VLSI design of a changeable hybrid-radix FFT hardware architecture with 2D-FIFO storing structure for 3GPP LTE systems

Abstract This paper presents a reconfigurable Fast Fourier Transform (FFT) hardware architecture for 3GPP LTE systems. In the main FFT computing process, a novel processing kernel engine is proposed to support four configuration types of changeable hybrid-radix FFT operations. Also, in the data storage manipulation, a smart 2D-FIFO structure is used to flexibly handle efficient reading/writing data access for 36 different FFT sizes. In addition to a field-programmable gate array prototyping design approach, we provide application-specific integrated circuit implementation via TSMC 90-nm CMOS technology. The developed FFT chip only occupies a core area of 1 . 416 mm 2 , consumes 24.2 mW of power, and reaches maximum speed of 111.11 MHz.

A Flexible CO-OFDM Using Reconfigurable Multi-Precision FFT

To improve flexibility, energy efficiency, and speed of elastic optical orthogonal frequency division multiplexing systems, a reconfigurable multi-precision fast Fourier transform (FFT) is presented. The minimum required FFT word length for different criteria—namely, the bit error rate (BER), FFT size, modulation format, and optical signal-to-noise ratio—is determined using simulations. At run time, system performance is improved significantly by using a reconfigurable multi-precision FFT, while the target BER is satisfied. The proposed design is synthesized on an FPGA, and the results show that both energy efficiency and processing speed are improved about 79% and 78%, respectively, compared with the conventional design.