Fast Fourier Transform Processor Research Articles

A novel hybrid fast Fourier transform processor in 5G+ and bio medical applications

To address the growing demand for real-time and high-performance signal processing, Field-Programmable Gate Array (FPGA) technology provides an influential platform for implementing Fast Fourier Transform (FFT) algorithms. The existing topologies of FFT processors encounters challenges related to high power consumption, limiting their viability for energy-efficient applications. In this research work, a hybrid radix encoder with two-stage operand trimming logarithmic appropriate multiplier and optimized truncated Kogge-stone adder based 2048-point, 4096-point FFT processor for FPGA implementation is designed by focusing on high throughput with minimal consumption of power. This processor is engineered to handle FFTs ranging from 16 to 4096 points catering to both biomedical applications and upcoming 5G technology. The proposed/introduced framework attains a high throughput (78.036 Gbps), and maximum signal to noise ratio (30 dB), low power consumption (26.49 mW), minimum delay (0.12 ns), minimum area (547 μm2), bit error rate (0.1) and minimum execution time (0.223 ms) than the traditional approaches.

The High Time Resolution Universe Pulsar survey – XVIII. The reprocessing of the HTRU-S Low Lat survey around the Galactic Centre using a Fast Folding Algorithm pipeline for accelerated pulsars

ABSTRACT The HTRU-S Low Latitude survey data within 1° of the Galactic Centre (GC) were searched for pulsars using the Fast Folding Algorithm (FFA). Unlike traditional Fast Fourier Transform (FFT) pipelines, the FFA optimally folds the data for all possible periods over a given range, which is particularly advantageous for pulsars with low-duty cycles. For the first time, a search over acceleration was included in the FFA to improve its sensitivity to binary pulsars. The steps in dispersion measure (DM) and acceleration were optimized, resulting in a reduction of the number of trials by 86 per cent. This was achieved over a search period range from 0.6 to 432-s, i.e. 10 per cent of the observation time (4320s), with a maximum DM of 4000 pc cm−3 and an acceleration range of ±128 m s−2. The search resulted in the re-detections of four known pulsars, including a pulsar that was missed in the previous FFT processing of this survey. This result indicates that the FFA pipeline is more sensitive than the FFT pipeline used in the previous processing of the survey within our parameter range. Additionally, we discovered a 1.89-s pulsar, PSR J1746-2829, with a large DM, located 0.5 from the GC. Follow-up observations revealed that this pulsar has a relatively flat spectrum (α = −0.9 ± 0.1) and has a period derivative of ∼1.3 × 10−12 s s−1, implying a surface magnetic field of ∼5.2 × 1013 G and a characteristic age of ∼23 000 yr. While the period, spectral index, and surface magnetic field strength are similar to many radio magnetars, other characteristics such as high linear polarization are absent.

Advancements in Spaceborne Synthetic Aperture Radar Imaging with System-on-Chip Architecture and System Fault-Tolerant Technology

With the continuous development of satellite payload and system-on-chip (SoC) technology, spaceborne real-time synthetic aperture radar (SAR) imaging systems play a crucial role in various defense and civilian domains, including Earth remote sensing, military reconnaissance, disaster mitigation, and resource exploration. However, designing high-performance and high-reliability SAR imaging systems that operate in harsh environmental conditions while adhering to strict size, weight, and power consumption constraints remains a significant challenge. In this paper, we introduce a spaceborne SAR imaging chip based on a SoC architecture with system fault-tolerant technology. The fault-tolerant SAR SoC architecture has a CPU, interface subsystem, memory subsystem, data transit subsystem, and data processing subsystem. The data processing subsystem, which includes fast Fourier transform (FFT) modules, coordinated rotation digital computer (CORDIC) modules (for phase factor calculation), and complex multiplication modules, is the most critical component and can achieve various modes of SAR imaging. Through analyzing the computational requirements of various modes of SAR, we found that FFT accounted for over 50% of the total computational workload in SAR imaging processing, while the CORDIC modules for phase factor generation accounted for around 30%. Therefore, ensuring the fault tolerance of these two modules is crucial. To address this issue, we propose a word-length optimization redundancy (WLOR) method to make the fixed-point pipelined FFT processors in FFT modules fault tolerant. Additionally, we propose a fault-tolerant pipeline CORDIC architecture utilizing error correction code (ECC) and sum of squares (SOS) check. For other parts of the SoC architecture, we propose a generic partial triple modular redundancy (TMR) hardening method based on the HITS algorithm to improve fault tolerance. Finally, we developed a fully automated FPGA-based fault injection platform to test the design’s effectiveness by injecting errors at arbitrary locations. The simulation results demonstrate that the proposed methods significantly improved the chip’s fault tolerance, making the SAR imaging chip safer and more reliable. We also implemented a prototype measurement system with a chip-included board and demonstrated the proposed design’s performance on the Chinese Gaofen-3 strip-map continuous imaging system. The chip requires 9.2 s, 50.6 s, and 7.4 s for a strip-map with 16,384 × 16,384 granularity, multi-channel strip-map with 65,536 × 8192 granularity, and multi-channel scan mode with 32,768 × 4096 granularity, respectively, and the system hardware consumes 6.9 W of power to process the SAR raw data.

Real-Time Laser Interference Detection of Mechanical Targets Using a 4R Manipulator

In this study, a laser interferometric sensing measurement (ISM) system based on a 4R manipulator system is developed to achieve detection of mechanical targets, which aims to realize the real-time, online detection of workpieces with high precision during processing. The 4R mobile manipulator (MM) system is flexible and can move in the workshop, aiming to preliminarily track the position of the workpiece to be measured and locate it at millimeter level. The reference plane of the ISM system is driven by piezoelectric ceramics with the spatial carrier frequency realized and the interferogram obtained by a charge coupled device (CCD) image sensor. The subsequent processing of the interferogram includes fast Fourier transform (FFT), spectrum filtering, phase demodulation, tilt elimination for wave-surface, etc., so as to further restore the surface shape of the measured surface and obtain the surface quality indexes. A novel cosine banded cylindrical (CBC) filter is used to improve the FFT processing accuracy, and a bidirectional extrapolation and interpolation (BEI) technique is proposed for the preprocessing operation of real-time interferograms before FFT processing. Compared with the results from a ZYGO interferometer, the real-time online detection results show the reliability and practicability of this design. The relative error of peak-valley value reflecting the processing accuracy can reach about 0.63%, with the root-mean-square value reaching about 1.36%. Some possible applications of this work include the surface of mechanical parts in the process of online machining, the end face of shaft-like structures, annular surfaces, etc.

A 60-Mode High-Throughput Parallel-Processing FFT Processor for 5G/4G Applications

This article presents a 60-mode high-throughput parallel-processing memory-based fast Fourier transform (FFT) processor for fifth-generation (5G)/4G applications. The proposed architecture adopts a multi-FFT parallel-processing scheme to significantly reduce the idle computation cycles of small point FFT due to the deep pipeline. The proposed scheme can narrow the throughput gap between different FFT sizes. In conjunction with the parallel processing scheme, a configurable 16-parallelism butterfly unit is proposed to support a maximum of five radix-3, four radix-4, three radix-5, two radix-8, or one radix-9 operation in one cycle. Furthermore, this article demonstrates conflict-free memory access with a parallel method based on fusion shift combined with a hopping-based method to simplify the data arrangement at different radix stages. According to the orthogonal frequency division multiplexing (OFDM) application characteristics, our processor is extended to support many additional commonly used functions, such as zero padding, cyclic prefix insertion, and 7.5-kHz frequency shift, which can simplify the system call in 5G/4G applications. The FFT processor has been successfully integrated into a small-cell base station baseband system-on-chip (SoC) and taped out at the TSMC 12-nm technology. The implementation result reveals that the die area of the proposed processor is 0.374 mm2 with a power consumption of 235.5 mW at 1 GHz, and the processor supports a balanced throughput up to 3.92 GS/s at all 60-mode, which is better than that of the state-of-the-art (SOTA) designs.

Comparative Accuracy Study Of LDV Profile-Sensor Acquisition Modes And Particle Diameters

The laser Doppler velocity profile sensor (LDV-PS) system offers the possibility to measure flow velocities with high spatial resolution and is therefore a promising method for the investigation of flows with high velocity gradients. The present experimental study revolves around the interplay between a broad range of chosen LDV-PS acquisition parameters, the dynamic velocity range within the observed measurement volume, and the accuracy of the velocity and position estimation from an application perspective. In the chosen set-up, thin wires of different diameters rotate at varying velocity levels and are captured instead of tracer particles by the applied system. It is observed that constant sample rate and number for the Fast Fourier Transform (FFT) evaluation of the detected burst signal allow straightforward measurements of unknown velocity profiles, but imply a velocity-dependent spatial measurement uncertainty. In contrast, velocity-adjusted acquisition settings allow to acquire particle bursts with equal signal resolution and length effecting a constant measurement accuracy at all velocity levels when adjusted appropriately. The position standard deviation is furthermore observed to increase with the wire diameter.Hence, the size of the scattering object should be chosen appropriately small during calibration and measurement. The gained knowledge offers the possibility to adapt the evaluation parameters more specifically to a given measurement problem.Consequently, measurements can be conducted in flows with small velocities with a high spacial resolution, when the FFT parameters and processing routines are adjusted accordingly, small particles are chosen and vibrations in the set-up are avoided.

Efficient Cached 64 Point FFT Processor Using Floating Point Arithmetic for OFDM Application

Presently Fourth generation and other wireless systems are focused area for the research and development in the communication field. Fast Fourier Transform (FFT) & Inverse FFT (IFFT) are required for Orthogonal frequency division multiplexing in the integral part of modulation/demodulation modules that occupies more area and power. This paper presents low power and area efficient Cached memory for Fast Fourier Transform (FFT) processor using floating point arithmetic for OFDM application. To store computational permutations each butterfly unit needs one memory. So if considering higher radix of FFT processor, memory requirement increases, it yields to more power consumption and more density occupancy. In this proposed cached 64 point radix 2^6 SDF architecture for reducing the arithmetic hardware complexity of complex multipliers and complex adders present in butterfly structure to obtain low power and less memory requirement. The proposed system is synthesized by using CADENCE RTL COMPLIER and is implemented in ENCOUNTER RTL TO GDSII SYSTEM” using 90nm CMOS technology with a supply voltage of 1V. Synthesis results shows that the proposed design is efficient in terms of gate count, area and power consumption.

Universal Filtered Multicarrier Receiver Complexity Reduction to Orthogonal Frequency Division Multiplexing Receiver

The Universal Filtered Multicarrier (UFMC) waveform technology is one of the promising waveforms for 5G and beyond 5G networks. Owing 2N-point Fast Fourier Transform (FFT) processor at the UFMC receiver, the computational and implementation complexity is two times more than the conventional Orthogonal Frequency Division Multiplexing (OFDM) receiver system. In this paper, we proposed a simplified UFMC receiver structure to reduce computational complexity as well as hardware requirements. The received UFMC symbol simplified exactly to its equivalent after performing 2N-point FFT and decimation operations. In which, the mathematical model of the frequency-domain UFMC signal is rederived after processing through 2N-point FFT and decimator, and the simplified signal is generated with an N-point FFT. Accordingly, the 2N-point FFT processor and decimator are replaced with a single N-point FFT processor. This approach reduces the 50% computational complexity at the FFT processor level hence the hardware and processing time. The computational complexity of the proposed receiver model is approximately equivalent to the OFDM receiver. Additionally, analyzed the mathematical model for the simplified UFMC receiver and the comparative performance of the UFMC system with the conventional model.

Design Space Exploration of Single-Lane OFDM-Based Serial Links for High-Speed Wireline Communications

The 4-level pulse-amplitude modulation (PAM-4) with an analog-digital converter (ADC)-based receiver (RX) has become the most commonly employed modulation for ultra-high-speed serial links with the data rate above 100 Gb/s. To support the data rate of 200 Gb/s, orthogonal frequency division multiplexing (OFDM) has been studied recently as one of the possible modulation schemes in the next-generation serial links. The OFDM can feature high bandwidth efficiency without increasing the equalization complexity, leading to a reduced maximum signal amplitude attenuation and lower required DAC/ADC conversion rates given sufficient DAC/ADC resolutions such that the BER is not primarily limited by the data converters’ resolution. This paper presents system-level modeling results of OFDM-based wireline serial links, with a particular emphasis on the impacts of the fast Fourier transform (FFT) processor’s tap count on the serial link performance. The relationship among the cyclic prefix (CP), FFT tap count, and the link bit-error-rate (BER) are thoroughly explained. The analysis explains that the power consumption of a partially-serial FFT processor improves with a larger kernel FFT size, and simulation results show that the BER performance improves with the FFT size where an optimal CP length exists given the FFT size.

Design and Implementation of AGU based FFT Pipeline Architecture

Present it is most needful task to get various applications with parallel computations by using a Fast Fourier Transform (FFT) and the derived outputs should be in regular format. This can be achieved by using an advanced technique called Multipath delay commutator (MDC) Pipelining FFT processor and this processor will be capable to perform the computation of a different data streams at a time. In this paper the design and implementation of AGU based Pipelined FFT architecture is done Caluclation of a butterfly is done within 2 cycles by the instructions proposed. A Data Processing Unit (DPU) is employed in this pipeline architecture and supports the instructions & an FFT Adress Generation Unit (FAGU) caluclates butterfly input & output data adresses automatically. The DPU proposed sysyem requires less area compared to commericial DSP chips. Futhermore, the proposed FAGU reduces the number of FFT computation cycles. The FFT design architecture will have real data paths. With various FFT sizes, different radix & various parallesim levels, the FFT can be mapped to the pipeline architecture. The most attractive feature of the pipelined FFT architecture is it consists of bit reversal operation so it requires little number of registers and better throughput.

Novel method of multi-frequency flicker to stimulate SSVEP and frequency recognition

This work uses the multi-frequency flicker to stimulate SSVEP, which is different from earlier studies that using single-frequency flicker as flash stimulators. Usually, the frequency recognition of SSVEP were converted into command output with the widely used Fast fourier transform (FFT). In the experiment, seven subjects stared at the six groups of LED stimulators with two or more different and independent flicker frequencies. Three electrodes placed at Oz-A1 and Fpz (Ground) used to measure Electroencephalography (EEG) signals. After processing the EEG signal, the frequency recognition of SSVEPs were converted into command output with the FFT and the proposed novel method (NM). The results of 28-second and every 4-second segmented EEG signals were interfered by external noise that cannot to recognize the correct signals after FFT processing. On the contrary, these unrecognizable signals can clearly recognized the maximum ρ value after using NM processing. In addition, the combinations of multi-frequency flicker provide the more stimulation options to apply to BCI control. This work uses only one channel of the EEG signal and the proposed novel method (NM) is simpler and have higher recognition rate than widely used FFT method.

FPGA Implementation of an Efficient FFT Processor for FMCW Radar Signal Processing

This paper presents the design and implementation results of an efficient fast Fourier transform (FFT) processor for frequency-modulated continuous wave (FMCW) radar signal processing. The proposed FFT processor is designed with a memory-based FFT architecture and supports variable lengths from 64 to 4096. Moreover, it is designed with a floating-point operator to prevent the performance degradation of fixed-point operators. FMCW radar signal processing requires windowing operations to increase the target detection rate by reducing clutter side lobes, magnitude calculation operations based on the FFT results to detect the target, and accumulation operations to improve the detection performance of the target. In addition, in some applications such as the measurement of vital signs, the phase of the FFT result has to be calculated. In general, only the FFT is implemented in the hardware, and the other FMCW radar signal processing is performed in the software. The proposed FFT processor implements not only the FFT, but also windowing, accumulation, and magnitude/phase calculations in the hardware. Therefore, compared with a processor implementing only the FFT, the proposed FFT processor uses 1.69 times the hardware resources but achieves an execution time 7.32 times shorter.

Exploring the CORDIC Algorithm and Clock-Gating for Power-Efficient Fast Fourier Transform Hardware Architectures

This work explores hardware-oriented optimizations for the CORDIC (COordinate Rotation Digital Computer) algorithm investigating the power-efficiency improvements employing N-point Fast Fourier Transform (FFT) hardware architectures. We introduced three hardware-oriented optimizations for the CORDIC: (a) improving the signal extension, (b) removing the angle accumulation and (c) eliminating the redundancies in the iterations, both unnecessary when processing the FFT processing. Fully sequential FFT architectures of 32, 64, 128, and 256 points were synthesized employing ST 65 nm standard cell libraries. The results show up to 38% of power savings on average when using our best CORDIC optimization proposal to the FFT architecture comparing to the explicit multiply-based butterfly version. Moreover, when combining our best CORDIC optimization with the clock-gating technique, the power savings rises to 78.5% on average for N-point FFT.

Design of FFT processor using low power Vedic multiplier for wireless communication

Digital Signal Processing (DSP) is a very significant and active research area. High throughput is a requirement for most wireless communication systems. The critical bottleneck that affects communication ability is the Fast Fourier Transform (FFT), which is the essence of most modulators. Currently, Floating point FFT processors have been used in Radar signal processing, fast convolution, Spectrum estimation and OFDM based modulators/demodulators. Efficient VLSI based architectures are required for real-time FFT processing. The multiplication limits the performance in terms of throughput of FFT. Consequently, there is a need for high speed and low power multiplier architectures with minor truncation error. The present paper presents a modified binary floating-point multiplier using Vedic mathematics and a modification in the previously published Vedic multiplier circuit has been proposed. The entire design has been implemented in Verilog HDL. Synthesis and simulations are done using Xilinx ISE Design Suite 14.5.The performance evaluation in terms of speed and area occupied is compared with the previously reported Vedic multiplier architectures. Using 90 nm technologies, the Power Delay Product (PDF) of the proposed Vedic multiplier gets reduced through KSA by 86.41% compared to the multipliers. The Vedic adder power is reduced by 45.9% when it is compared with the carry look-ahead adder. The overall power delay product is reduced around 55–60% through the FFT processor by using Vedic mathematics.

Energy Efficient Floating Point Fft/Ifft Processor For Mimo-Ofdm Applications

There are several methods to accomplish Fast Fourier Transform and Inverse Fast Fourier Transform processor for multiple inputs multiple output-orthogonal frequency division multiplexing applications. It requires high performance and low power implementation methodologies for reducing the hardware complexity and cost. In conventional fixed point arithmetic calculation is complex to utilize because the dynamic range of computations must be limited in order to overcome overflow and under flow problems. This paper presents floating point arithmetic optimization technique to implement radix-2 butterfly structures for the reduction of complex multipliers presented. Implementations of 32 bit floating point multiplier and floating point adder are presented by using single precision and compare the synthesis results with conventional system. In order to reduce the error we used floating point arithmetic for the butterfly structure. Energy efficient multiplier based on modified booth algorithm is used in radix-2 butterflies. By adopting this architecture the FFT/IFFT implementation using Xilinx FPGA Vertex-7 will improve the 25% logic utilization and the reduction in space utilization. Using arithmetic reduction the power delay product for radix 2 butterfly is reduced by 2.5% compared to normal implementation.

An FPGA-Based Four-Channel 128k-Point FFT Processor Suitable for Spaceborne SAR

Spaceborne synthetic aperture radar (SAR) plays an important role in many fields of national defense and the national economy, and the Fast Fourier Transform (FFT) processor is an important part of the spaceborne real-time SAR imaging system. How to meet the increasing demand for ultra-large-scale data processing and to reduce the scale of the hardware platform while ensuring real-time processing is a major problem for real-time processing of on-orbit SAR. To solve this problem, in this study, we propose a 128k-point fixed-point FFT processor based on Field-Programmable Gate Array (FPGA) with a four-channel Single-path Delay Feedback (SDF) structure. First, we combine the radix-23 and mixed-radix algorithms to propose a four-channel processor structure, to achieve high efficiency hardware resources and high real-time performance. Secondly, we adopt the SDF structure combined with the radix-23 algorithm to achieve efficient use of storage resources. Third, we propose a word length adjustment strategy to ensure the accuracy of calculations. The experimental results show that the relative error between the processor and the MATLAB calculation result is maintained at about 10−4, which has good calculation accuracy.

A novel parallel prefix adder for optimized Radix-2 FFT processor

The Fast Fourier Transform (FFT) is the basic building block for DSP applications where high processing speed is the critical requirement. Resource utilization and the number of computational stages in Radix-2 FFT structure implementation can be minimized by improving the performance of utilized multiplier and adder blocks. This work proposes a hardware design of an efficient Radix-2 FFT architecture using optimized multiplier and novel Parallel prefix (PP) adder. The designed FFT architecture results in low power and area with an increase in operation speed in comparison to the existing architectures. Our proposed Radix 2 FFT implementation results in 18.218 ns (6.030 ns logic delay and 12.118 ns router delay) in comparison with 24.003 ns delay for Wallace multiplier using Kogge Stone PP adder (M1P1), 24.162 ns delay for Wallace multiplier using Brent Kung PP adder (M2P2), 24.889 ns delay for Wallace multiplier using Landner Fischer PP adder (M3P3) and 22.827 ns delay for Wallace multiplier using Han Carlson PP adder (M4P4) algorithm. The proposed adder and hence the FFT processor can be used in different applications where high speed, low power, and less area is required. The novel PP architecture results in a 20.19% improvement in comparison with other state-of-art techniques.

Demonstration of a 47.8 GHz High-Speed FFT Processor Using Single-Flux-Quantum Technology

A fast Fourier transform (FFT) is an algorithm that computes the discrete Fourier transform (DFT) of a sequence at high speed. FFT can convert a signal from time domain to frequency domain, and is wildly used in digital signal processing field. In this paper, a high-speed, low-power FFT processor is demonstrated up to 47.8GHz with the measured power consumption of 5.3mW, using single-flux quantum (SFQ) logic. This is the first complete FFT processor implementation using superconducting technology, performing 8-point 7-bit FFT in a bit-serial computing manner. The test chip fabricated using a 1.0 μm 9-layer process consists of 17 455 Nb/AlO <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">x</sub> /Nb Josephson junctions (JJs), rendering itself the largest superconducting digital circuit capable of iterative data computing. The correct operation of the chip has been experimentally confirmed at a maximum operating frequency of 47.8GHz (word speed 8GHz) by conducting on-chip high-speed testing.

A Modified MFCC for Improved Wavelet-Based Denoising on Robust Speech Recognition

Research on the current speech recognition system leads to the creation of a noise-resistant system. The Mel Frequency Cepstral Coefficients (MFCC) extraction method becomes a popular method in the speech recognition system. In this paper, the MFCC's weakness of noise interference is the main reason underlies the accomplishment of a robust speech recognition system. Development was carried out by improving the denoising performance using a wavelet transform. Modifications were carried out by analyzing the weakness of the wavelet denoising process on the recognition system using the MFCC method. The analysis was conducted at one of the MFCC stages, the Fast Fourier Transform (FFT) stage. The proposed method was conducted by performing the denoising process using Wavelet only on the noise-related data based on the FFT process' analysis results. The study utilized speech data in the form of eleven isolated words in English added with noise with several different characteristics. Results showed that the proposed method was capable of generating a better accuracy than conventional wavelet denoising methods on the signal to noise ratio (SNR) of 10dB, 15dB, and 20dB using a Fejer Korovkin 6 wavelet type. The highest accuracy increase of the proposed method was in signal to noise ratio (SNR) of 15dB with a rise of 4.63%, followed by a 3.96% increase at 20dB intensity, and 2.3% at 10dB intensity. The performance of the proposed method is then compared with other methods. The results show that the proposed method has the best performance on clean speech and noisy speech at SNR intensities of 10dB, 15dB, and 20dB.

A novel addressing algorithm of radix-2 FFT using single-bank dual-port memory

PurposeThis paper aims to present a single-block memory-based FFT processor design with a conflict-free addressing scheme for field-programmable gate arrays FPGAs with dual-port block memories. This study aims for a single-block dual-port memory-based N-point radix-2 FFT design that uses memory locations and spending minimum clock cycle.Design/methodology/approachA new memory-based Fast Fourier Transform (FFT) design that uses a dual-port memory block is proposed. Dual-port memory allows the design to perform two memory reads and writes in a single clock cycle. This approach achieves low operational clock and smallest memory simultaneously, excluding some small overhead for exceptional address changes. The methodology is to read from while writing to a memory location, eliminating the need for excess memory and additional clock cycles.FindingsWith the minimum memory size and the simplest architecture, radix-2 FFT and single-memory block are used. The number of clock pulses spent for all FFT operations does not provide much advantage for low-point FFT operations but is important for high-point FFT operations. With the developed algorithm, N memory is used, and the number of clock pulses spent for all FFT stages is (N/2 +1)log2N for all FFT operations.Originality/valueThis is an original paper, which has simultaneously in whole or in part been submitted anywhere else.