Fast Fourier Transform Architecture Research Articles

A Novel Area-Power Efficient Design for Approximated Small-Point FFT Architecture

Fast Fourier transform (FFT) is an essential algorithm in digital signal processing and advanced mobile communications. With the continuous development of modern technology, the area-power efficient hardware implementation of FFT has attracted a lot of attention. In this article, a novel design for FFT implementation is proposed. The number of resource-expensive multiplications in our design is decreased by a twiddle factor merging technique that reduces the hardware area. Subsequently, a common subexpression sharing scheme is applied to reuse the hardware resources to further save the hardware area. In addition, a magnitude-response aware approximation algorithm is proposed for applications where the transformation accuracy can be compromised a little bit for lesser hardware area and power dissipation. Logic synthesis shows that the proposed 16-point FFT architecture can save hardware area and power dissipation on application-specific integrated circuit (ASIC) by up to 65.7% and 53.1% compared with recently published designs. Similarly, the proposed 32-point FFT architecture achieves up to 58.8% reduction on hardware area and 60.0% reduction on power dissipation on ASIC.

Design of an Area-Efficient Various N-point Support radix-2/22 FFT using Modified Butterfly Units

Fast Fourier Transform (FFT) acts as an element in the high-speed signal processing application, which involves the following subsequent operations, namely complex addition, complex subtraction and complex multiplication. Due to the complex multiplication operation, the FFT structures lead to more hardware demand. Hence, this work introduces an area-efficient various N-point support radix-2 and radix-22 FFT structure by using proposed modified butterfly units and radix-2/22 butterfly unit. The proposed modified butterfly units are used to reduce the number of complex multipliers effectively. For this reason, it is using for certain conditions in FFT design instead of existing radix-2/22 butterfly unit. Further, the proposed design supported to perform various size of FFT in a single architecture without increasing the extra element demand. Moreover, the proposed FFT structure designed and implemented using a Xilinx Virtex-6 Field-Programmable Gate Array (FPGA) device (6vcx75tff484-2) and Cadence tool with 45nm CMOS technology. The implementation results demonstrate that the proposed N-point (N=16, 32 and 64) DIF-FFT design attains the less hardware complexity when compared with existing multi-mode FFT design. Then the proposed area-efficient 16-point, 32-point and 64-point radix-2 FFT architectures reduce the total area by 20.99%, 11% and 4.9% respectively. As well, the proposed area-efficient 16-point, 32-point and 64-point radix-22 FFT architectures reduce the total area by 32%, 19% and 11% respectively.

Area–Time–Power Efficient FFT Architectures Based on Binary-Signed-Digit CORDIC

Fast Fourier transform (FFT) is a significant technique in the digital signal processing (DSP). The intrinsic weak point of the primary designs of FFT was the use of multipliers. CORDIC is the most prevalent method to replace the multipliers of FFTs. In order to enhance the speed of CORDIC, redundant binary signed-digit (BSD) encodings can be utilized, so-called BSD-CORDIC. The main goal of this paper is to improve the efficiency of BSD-CORDIC-based FFT. The redundant improved composed (RIC) CORDIC is proposed as a novel BSD-CORDIC. The main idea behind the RIC CORDIC lies in prior determination of the required iterations in such a way that the maximum number of iterations is reduced, which results in speedup and decrease in hardware resources. Also, some of the iterations still can be skipped, which leads to further reduction in the power consumption. The synthesis results demonstrate that the FFT based on the RIC BSD-CORDIC enhances speed, power consumption, and area overhead.

Two Parallel Pipelined FFT Architecture After Third Stage for Low Complexity and Latency

Complexity is the major issue in the development of pipelined Fast Fourier Transform (FFT) structure. A novel parallel pipelined FFT design constructed for low complexity and Latency. The proposed structure efficiently uses pipeline and parallel pipeline in the design. The first three stages of the structure follow the pipelining and from fourth stage there are two parallel paths simultaneously compute four complex additions, the first three single path stages that reduces complexity, parallel pipeline stages at the end of structure also reduces the Latency. The proposed structure is an optimized solution to reduce the trade-off between Latency and complexity. The comparative performance of the proposed structure with several other existing structures shows that it has Low latency with small cost of hardware.

FPGA Implementation of Radix-2 based FFT Architecture for Real-Valued signal processing

This paper investigates the various pipelined FFT architectures based on radix-2, radix-22 & radix-23 algorithms. The implemented FFTs are designed by employing techniques such as folded transform and register minimization. It maximizes the utilization of hardware resource and reduces the number of adders. It requires less area and achieves high throughput and low latency. For higher values of N, the FFT (Fast Fourier Transform) architecture has many butterfly structures which has been optimized. The FFT outputs are usually obtained in a bit reversed order and a new approach for reordering the bit-reversed orders has been proposed.

Implementation of FFT Architecture using Various Adders

In 1965 a technique called Fast Fourier Transform (FFT) was invented to find the Fourier Transform. This paper compares three architectures, the basic architecture/ non-reduced architecture of FFT, decomposed FFT architecture without retiming and decomposed FFT architecture with retiming. In each case, the adder used will be Ripple Carry Adder (RCA) and Carry Save Adder (CSA). A fast Fourier transform (FFT) calculates the discrete Fourier transform (DFT) or the inverse (IDFT) of a sequence. Fourier analysis transforms a signal from time to frequency domain or vice versa. One of the most burgeoning use of FFT is in Orthogonal Frequency Division Multiplex (OFDM) used by most cell phones, followed by the use in image processing. The synthesis has been carried out on Xilinx ISE Design Suite 14.7. There is a decrease in delay of 0.824% in Ripple Carry Adder and 6.869% in Carry Save Adder, further the reduced architecture for both the RCA and CSA architectures shows significant area optimization (approximately 20%) from the non-reduced counterparts of the FFT implementation.

Compact and high‐throughput parameterisable architectures for memory‐based FFT algorithms

Designers must carefully choose the best-suited fast Fourier transform (FFT) algorithm among various available techniques for the custom implementation that meets their design requirements, such as throughput, latency, and area. This article, to the best of authors' knowledge, is the first to present a compact and yet high-throughput parameterisable hardware architecture for implementing different FFT algorithms, including radix-2, radix-4, radix-8, mixed-radix, and split-radix algorithms. The designed architectures are fully parameterisable to support a variety of transform lengths and variable word-lengths. The FFT algorithms have been modelled and simulated in double-precision floating-point and fixed-point representations using authors' custom-developed library of numerical operations. The designed FFT architectures are modelled in Verilog hardware description language and their cycle-accurate and bit-true simulation results are verified against their fixed-point simulation models. The characteristics and implementation results of various FFT architectures on a Xilinx Virtex-7 FPGA are presented. Compared to recently published works, authors' memory-based FFT architectures utilise less reconfigurable resources while maintaining comparable or higher operating frequencies. The ASIC implementation results in a standard 45-nm CMOS technology are also presented for the designed memory-based FFT architectures. The execution times of FFTs on a workstation and a graphics processing unit are compared against authors' FPGA implementations.

Low power VLSI implementation of real fast Fourier transform with DRAM-VM-CLA

In recent years, Fast Fourier Transform (FFT) plays a vital role in signal processing application for converting time domain to frequency domain. This paper presents Real FFT architecture which is implemented in radix-2 Decimation- in-Frequency (DIF). Instead of using more number of Random Access Memory (RAM), single Dual port RAM (DRAM) is used to store the intermediate data results. In Processing Element (PE), normal multiplier and adder has been used in previous works. In this paper, Vedic Multiplier (VM) and Carry Lookahead Adder (CLA) is used for improving the Real FFT operation and it is implemented in Verilog code. Application Specified Integrated Circuits (ASIC) and Field Programmable Gate Array (FPGA) performances are evaluated for all the architectures. In DRAM-VM-CLA architecture, LUT, flip flop, slices, and frequency are improved in FPGA performance as well as area, power, and delay are improved in ASIC performance. In ASIC 180 nm technology, 81.14% of area, 45.98% of delay, and 89.77% of Area Delay Product (ADP) is minimized in DRAM-VM-CLA as well as 72.64% of area, 5.44% of delay, and 74.10% of ADP is reduced in ASIC 45 nm technology.

Hardware Implementation of FFT/IFFT Algorithms Incorporating Efficient Computational Elements

Fast Fourier Transform (FFT) and Inverse Fast Fourier Transform (IFFT) computations involve quite a large number of complex multiplications and complex additions. Optimizing the FFT processing elements in terms of complex multiplication reduces area and power consumption. In this paper, complex multipliers in the FFT processors are replaced by area and power efficient approximate multipliers. Approximate arithmetic computation appears to be effective solution for the systems that exhibit an intrinsic error tolerance. The computational errors arising because of approximation can be considered as trade-off for the significant gains in power and area. Approximate 8- and 16-bit multipliers are used in radix-2 butterfly unit which is the crucial computational component in FFT/IFFT processing. The designed FFT/IFFT processing units are analyzed, synthesized and simulated in Altera Cyclone II EP2C35F672C6 Field Programmable Gate Array (FPGA) device. Experimental results show that the proposed 16-point FFT architecture incorporating approximate complex multiplier achieves an area and power efficiency of 33.47% and 1.8% respectively compared to accurate 16-point FFT processor. The 8-point and 16-point Decimation In Time (DIT)—FFT incorporating approximate computational elements operate at a speed of 26.69 Gbps and 46.20 Gbps, respectively.

DESIGN OF FFT ARCHITECTURE USING KOGGE STONE ADDER

An efficient Fast Fourier Transform (FFT) algorithm is used in the Orthogonal Frequency Division Multiplexing (OFDM) applications in order to compute the discrete Fourier transform. Also, a Single Path Delay Feedback (SDF) which is pipeline FFT architecture is used for faster performance to achieve high throughput. In conventional method, the FFT design has high delay and power due to time taken by the multiplication part. To decrease the delay, Kogge Stone Parallel Prefix Adder (KSPPA) is used with booth multiplier. As SDF is a simpler approach to realize FFT in different length, 64-point Radix-4 SDF-FFT algorithm using KSPPA in the booth multiplier is discussed in this study. The system is implemented in Xilinx 12.4 ISE and simulated using MODELSIM 6.3c. Results show that the system reduces the delay and power.

Signal-to-noise Ratio Study on Pipelined Fast Fourier Transform Processor

Fast Fourier transform (FFT) processor is a prevailing tool in converting signal in time domain to frequency domain. This paper provides signal-to-noise ratio (SNR) study on 16-point pipelined FFT processor implemented on field-programable gate array (FPGA). This processor can be used in vast digital signal applications such as wireless sensor network, digital video broadcasting and many more. These applications require accuracy in their data communication part, that is why SNR is an important analysis. SNR is a measure of signal strength relative to noise. The measurement is usually in decibles (dB). Previously, SNR studies have been carried out in software simulation, for example in Matlab. However, in this paper, pipelined FFT and SNR modules are developed in hardware form. SNR module is designed in Modelsim using Verilog code before implemented on FPGA board. The SNR module is connected directly to the output of the pipelined FFT module. Three different pipelined FFT with different architectures were studied. The result shows that SNR for radix-8 and R4SDC FFT architecture design are above 40dB, which represent a very excellent signal. SNR module on the FPGA and the SNR results of different pipelined FFT architecture can be consider as the novelty of this paper.

High‐throughput and compact FFT architectures using the Good–Thomas and Winograd algorithms

This study presents two hardware architectures for the efficient implementation of fast Fourier transform (FFT) based on the combined Good–Thomas and Winograd Fourier transform algorithms. The combined algorithms require fewer multiplications compared with the other FFT algorithms by eliminating twiddle factor multiplications. Two hardware architectures are presented: one is a fully-pipelined architecture using multi-dimensional Chinese remainder theorem for a high-throughput implementation and the other is a time-multiplexed architecture, which utilises the folding transformation for the compact realisation of short-length Winograd Fourier transforms. Both designs are fully-parameterisable and have been verified against their synthesisable Verilog descriptions. The characteristics and the implementation results of the two hardware architectures on a Xilinx field-programmable gate array are presented. To the best of the authors' knowledge, this study presents the first hardware realisation of FFT based on the combined Good–Thomas and Winograd FFT algorithms. The application of the proposed FFT architectures in the physical layer of the long-term evolution wireless standard is discussed.

Variable length mixed radix MDC FFT/IFFT processor for MIMO‐OFDM application

This study presents a variable length multi-path delay commutator fast Fourier transform (FFT)/inverse FFT (IFFT) architecture for a multiple input multiple output orthogonal frequency division multiplexing system. It supports the FFT/ IFFT lengths of 512/256/128/64 samples to process each symbol carried by eight spatial streams and achieves a speed of 160 MHz to meet the IEEE 802.11ac timing requirements. A resource scheduling methodology to minimise the hardware complexity of the design is proposed and adopted in the architecture presented. A novel stagger word length strategy is also proposed and applied to achieve the better accuracy with lesser hardware. Here, the signal to quantisation noise ratio of 57.23 dB is obtained. The twiddle coefficient storage space is significantly compressed to achieve the coefficient generation with reduced hardware. The design is implemented using the TSMC-65 nm complementary metal oxide semiconductor technology with a supply voltage of 1 V at 160 MHz. The implementation results show that the architecture has a gate count of 3,48,013 with power consumption of 105.1 mW and area of 0.492 mm2. The hardware complexity and performance of the design are compared with earlier reported architectures. It is observed that the proposed design achieves better performance in terms of hardware complexity and normalised energy for the given specifications.

Embedded DRAM-Based Memory Customization for Low-Cost FFT Processor Design

In this paper, we present embedded dynamic random access memory (eDRAM)-based memory customization techniques for low-cost fast Fourier transform (FFT) processor design. The main idea is based on the observation that the FFT processor has regular and predictable memory access patterns, and it can be efficiently exploited for memory customization using eDRAM. The memory customization approaches are applied to both of the pipelined and memory-based FFT architectures. In the pipelined architecture, the read wordline (RWL) coupling write assist and data packing schemes are employed to reduce the redundant RWL and wordline driving, respectively, in column-interleaved memory arrays. The memory address decoder is also simplified with thermometer code by exploiting the sequential access patterns. For the memory-based architecture, the modified cached-memory structure is employed in addition to the techniques used in the pipelined FFT architecture. The hardware implementation results of 2k-point FFT with a 0.11- $\mu {\mathrm{ m}}$ CMOS technology show that the proposed eDRAM-based pipelined and cached-memory FFTs achieve 26.8% and 33.2% power savings over the static RAM-based FFT design, respectively.

Implementation of Fingerprint Based Biometric System Using Optimized 5/3 DWT Architecture and Modified CORDIC Based FFT

The real-time biometric systems are used to authenticate persons for wide range of security applications. In this paper, we propose implementation of fingerprint-based biometric system using Optimized 5/3 DWT architecture and Modified CORDIC-based Fast Fourier Transform (FFT). The Optimized 2D-DWT architecture is designed using Optimized 1D-DWT architectures, Memory Units and novel Controller Unit which is used to scan rows and columns of an image. The database fingerprint image is applied to the proposed Optimized 2D-DWT architecture to obtain four sub-bands of LL, LH, HL and HH. The efficient architecture of FFT is designed by using Modified CORDIC processor which generates twiddle factor angles of range $$0^{\circ }$$ – $$360^{\circ }$$ using Pre-processing Unit and Comparator Block. Further, the LL sub-band coefficients are applied to the Modified CORDIC based FFT to generate final fingerprint features. The test fingerprint features are obtained by repeating the same procedure and are used to match the database fingerprint image features using Euclidean Distance. The performance parameters of proposed architecture in terms of area utilization, speed and accuracy is compared with existing architecture to validate the obtained results.

8-Point RADIX-8 Pipelined FFT Using SDF

Fast Fourier Transform (FFT) operation is one of the most important fundamental operations in the digital signal processing systems. A new pipelined Radix-8 based Fast Fourier Transformation (FFT) architecture is designed for performing frequency transformation techniques. The objective of this design is to improve the speed and to reduce the area, delay and power. Radix-8 FFT, which is used to improve the speed of functioning by reducing the computational path. In the proposed new architecture named as ―Radix-8 SDF FFT‖. In this architecture, the numbers of stages are reduced to 75%. The SDF FFT is to increasing the processing speed of architecture. The performance evaluation of Radix-8 SDF FFT architecture is determined through Very Large Scale Integration (VLSI) system design environment. In the VLSI system design, less area utilization, low power consumption and high speed are the main parameters. Hence, the main goal of proposed architecture is to reduce hardware complexity, power consumption and increasing both speed and throughput of the system. Applications: Mobile Ad-hoc Network (MANET), Orthogonal Frequency Division Multiplexing (OFDM) System.

An area-efficient and low-power 64-point pipeline Fast Fourier Transform for OFDM applications

In an orthogonal frequency division multiplexing (OFDM) based wireless systems, Fast Fourier Transform (FFT) is a critical block as it occupies large area and consumes more power. In this paper, we present an area-efficient and low power 16-bit word-width 64-point radix-22 and radix-23 pipelined FFT architectures for an OFDM-based IEEE 802.11a wireless LAN baseband. The designs are derived from radix-2k algorithm and adopt a Single-Path Delay Feedback (SDF) architecture for hardware implementation. To eliminate the complex multipliers and read-only memory (ROM) which is used for internal storage of twiddle factor coefficients, the proposed 64-point FFT employs a Canonical Signed Digit (CSD) complex constant multiplier using adders, multiplexers and shifters. The complex constant multiplier (CCM) is modified using common sub-expression sharing block that reduces the area of the design. The proposed radix-22 and radix-23 pipelined FFT architectures are modeled and implemented using TSMC 180nm CMOS technology with a supply voltage of 1.8V. The implementation results show that the proposed architectures significantly reduces the hardware cost and power consumption in comparison to existing 64-point FFT architectures.

An efficient pipelined architecture for real-valued Fast Fourier Transform

ABSTRACTReal-valued Fast Fourier Transform (FFT) plays an important role in today’s digital world because of the fact that most of the signals contain real values. The FFT computation of real signals using conventional techniques requires more hardware space with high power consumption, which is the most important task for a researcher while designing VLSI architectures. This can be eradicated by clearly analysing the symmetric property of the real-valued signals. In this paper, we have adopted the symmetric property and designed an efficient pipelined architecture for 16-point DIF FFT. The pipeline scheme reduce the processing time at the cost of some registers and in order to contribute efficiently for power reduction we have modified the complex multiplier with reduced internal real multipliers which are in turn replaced by an modified canonic signed digit multiplier (CSDM) with resource-sharing technique. The complete module is synthesised and simulated using Xilinx ISE 14.1 with the target device is Virtex-5 xc5vlx110T. The experimental results verify that our implemented design is more efficient in terms of speed, area and power when comparing with similar works.

Simulation of 32-Point Split-Radix Multipath Delay Commutator (SRMDC) based FFT Architecture

Background: Fast Fourier Transform (FFT) processor is the important method in Orthogonal Frequency Division Multiplexing (OFDM) communication systems. Split-Radix Fast Fourier Transform (SRFFT) estimates the least number of multiplications compared to other FFT algorithm; hence SRFFT is the best for the implementation of low power FFT processor. Methods: In this paper, the proposed “pipelined 32-point Split-Radix Multi-path Delay Commutator (SFMDC) FFT” architecture is designed. The MDC architecture has advantages in reducing the low chip area and lower power consumption. The SR-FFT algorithm has changing the numbers of butterfly elements in successive stages. The 32-point SR-MDC FFT architecture is to determine the frequency transformation techniques. The Split-Radix FFT algorithm is based on radix-2 and radix-4 algorithm and it is related to mixed radix FFT. Findings: The performance evaluation of proposed architecture is determined through VLSI System. Less area, low power consumption and high speed are the main parameters in this design. The proposed structure provides high throughput rate and low hardware complexity. Improvements: The goal of this proposed work is to reduce the slices and LUTs and power consumption and also to enhance the performances of the FFT processor than the existing method. The proposed method has been evaluated by using ModelSim 6.3C and synthesis results has been validated by using Xilinx Plan ahead 12.4.

VLSI based Pipelined Architecture for Radix-8 Combined SDF-SDC FFT

Background: Fast Fourier Transform (FFT) operation is one of the most important fundamental operations in the digital signal processing systems. In this paper, a new pipelined Radix-8 based Fast Fourier Transformation (FFT) architecture is designed for performing frequency transformation techniques. The objective of this paper is to improve the speed and to reduce the area, delay and power. Methods: Radix-8 FFT, which is used to improve the speed of functioning by reducing the computational path. In the proposed new architecture named as “Radix-8 combined SDF-SDC FFT”. In this architecture, the numbers of stages are reduced to 75%. The first two stages are designed using Single path delay feedback and the last two stages are designed using single-path-delay Commutator. The combined SDF-SDC FFT is to increasing the processing speed of architecture. In the proposed “pipelined Radix-8 combined SDF-SDC FFT’’ is designed in this article. Findings: In the existing Radix-8 SDF FFT, the number of stages is increased. In order to reduce the number of stages, Radix-8 combined SDF-SDC FFT has been proposed. The performance evaluation of Radix-8 combined SDF-SDC FFT architecture is determined through Very Large Scale Integration (VLSI) system design environment. In the VLSI system design, less area utilization, low power consumption and high speed are the main parameters. Hence, the main goal of proposed architecture is to reduce hardware complexity, power consumption and increasing both speed and throughput of the system. Applications: Mobile Ad-hoc Network (MANET), Orthogonal Frequency Division Multiplexing (OFDM) System, Telecommunication networking system are considered as the important applications of proposed radix-8 combined SDF-SDC FFT.