High‐throughput and compact FFT architectures using the Good–Thomas and Winograd algorithms

Abstract

This study presents two hardware architectures for the efficient implementation of fast Fourier transform (FFT) based on the combined Good–Thomas and Winograd Fourier transform algorithms. The combined algorithms require fewer multiplications compared with the other FFT algorithms by eliminating twiddle factor multiplications. Two hardware architectures are presented: one is a fully-pipelined architecture using multi-dimensional Chinese remainder theorem for a high-throughput implementation and the other is a time-multiplexed architecture, which utilises the folding transformation for the compact realisation of short-length Winograd Fourier transforms. Both designs are fully-parameterisable and have been verified against their synthesisable Verilog descriptions. The characteristics and the implementation results of the two hardware architectures on a Xilinx field-programmable gate array are presented. To the best of the authors' knowledge, this study presents the first hardware realisation of FFT based on the combined Good–Thomas and Winograd FFT algorithms. The application of the proposed FFT architectures in the physical layer of the long-term evolution wireless standard is discussed.