Fast Erase Research Articles

Reliability and Processing Effects of Bandgap-Engineered SONOS (BE-SONOS) Flash Memory and Study of the Gate-Stack Scaling Capability

In this paper, the reliability properties of bandgap-engineered SONOS (BE-SONOS) devices with various processing methods are extensively studied. BE-SONOS employs a multilayer O1/N1/O2/N2/O3 stack, where O1/N1/O2 serves as a bandgap-engineered tunneling barrier that provides an efficient hole-tunneling erase but eliminates the direct-tunneling leakage. BE-SONOS can overcome the fundamental limitation of the conventional SONOS, for which fast erase speed and good data retention cannot be simultaneously achieved. In this paper, a comprehensive understanding of BE-SONOS reliability is reported, including the processing effects of the critical ONO barrier (O1/N1/O2), the trapping layer (N2), and the top blocking oxide (O3). Moreover, the capability of dielectric scaling is also evaluated. Lower P/E voltages, good P/E cycling endurance, and data retention are maintained when N2 and O3 are further scaled to 60 . The results in this paper provide design and processing guidelines for optimizing the performance and reliability of BE-SONOS flash memory devices.

A novel high-/spl kappa/ SONOS memory using TaN/Al/sub 2/O/sub 3//Ta/sub 2/O/sub 5//HfO/sub 2//Si structure for fast speed and long retention operation

A novel high-/spl kappa/ silicon-oxide-nitride-oxide-silicon (SONOS)-type memory using TaN/Al/sub 2/O/sub 3//Ta/sub 2/O/sub 5//HfO/sub 2//Si (MATHS) structure is reported for the first time. Such MATHS devices can keep the advantages of our previously reported TaN/HfO/sub 2//Ta/sub 2/O/sub 5//HfO/sub 2//Si device structure to obtain a better tradeoff between long retention and fast programming as compared to traditional SONOS devices. While at the same time by replacing hafnium oxide (HfO/sub 2/) with aluminum oxide (Al/sub 2/O/sub 3/) for the top blocking layer, better blocking efficiency can be achieved due to Al/sub 2/O/sub 3/'s much larger barrier height, resulting in greatly improved memory window and faster programming. The fabricated devices exhibit a fast program and erase speed, excellent ten-year retention and superior endurance up to 10/sup 5/ stress cycles at a tunnel oxide of only 9.5 /spl Aring/ equivalent oxide thickness.

Charge-trapping device structure of SiO2∕SiN∕high-k dielectric Al2O3 for high-density flash memory

We present a device structure of SiO2∕SiN∕Al2O3 (SANOS). The use of a high-k dielectric material, specially Al2O3, in the blocking oxide concentrates the electric fields across the tunnel oxide and SiN, and releases it across the blocking oxide under program and erase mode. This effect leads to lower program and erase voltage as well as faster erase speed than the conventional SiO2∕SiN∕SiO2 (SONOS) device. Moreover, it is shown that the fast erase operation is performed even at a thicker tunnel oxide over 30Å where the hole direct tunneling current through the tunnel oxide is reduced significantly and thus the SANOS device has the excellent bake retention.

Influence of Sn doping upon the phase change characteristics of Ge2Sb2Te5

Phase change optical recording, which is employed in rewritable CDs and DVDs, is based on a reversible phase transformation. A focused laser is utilized to switch between an amorphous and a crystallization state. The time limiting step is the erasure process, i.e. the recrystallization. Hence faster materials are required. To this end, doping of Ge2Sb2Te5 has been suggested. In [1] the influence of Sn doping on the phase change characteristics on Ge2Sb2Te5 is reported. For this Sn doped Ge2Sb2Te5 film, ultra- fast erasing (<10 ns) is demonstrated, which is correlated with a single NaCl structure phase and a reduced activation barrier for crystallization. The first author, Ke Wang, is currently working as a Hum- boldt fellow at RWTH Aachen, where he studies ultra-fast chalcogenide alloys for phase change optical storage. This issue also contains the Editor's Choice “Synthesis of single-crystalline β-Ga2O3 nanoribbons” by Z. X. Yang et al. [2].

SONOS 구조를 갖는 멀티 비트 소자의 프로그래밍 특성

In this paper, the programming characteristics of the multi-bit devices based on SONOS structure are investigated. Our devices have been fabricated by 0.35 <TEX>$\mu\textrm{m}$</TEX> complementary metal-oxide-semiconductor (CMOS) process with LOCOS isolation. In order to achieve the multi-bit operation per cell, charges must be locally frapped in the nitride layer above the channel near the source-drain junction. Programming method is selected by Channel Hot Electron (CUE) injection which is available for localized trap in nitride film. To demonstrate CHE injection, substrate current (Isub) and one-shot programming curve are investigated. The multi-bit operation which stores two-bit per cell is investigated. Also, Hot Hole(HH) injection for fast erasing is used. The fabricated SONOS devices have ultra-thinner gate dielectrics and then have lower programming voltage, simpler process and better scalability compared to any other multi-bit storage Flash memory. Our programming characteristics are shown to be the most promising for the multi-bit flash memory.

Flash memory: towards single-electronics

Since their invention in 1984, flash memories have evolved from single device components to megabit nonvolatile memory (NVM) arrays. Flash memories were born from the need to find easily scalable replacements for EPROMs (erasable programmable read only memory) and EEPROMs (electrically erasable programmable read only memory). Unlike EPROMs and EEPROMs, flash memory cells provide single-cell electrical program and fast simultaneous block electrical erase. Thus, a small cell size is combined with a fast in-system erase capability.

Observation of fast erase due to enhanced generation of holes caused by electron impact ionization

This letter describes an enhanced erase mechanism in flash memory cells due to impact ionization induced generation of holes. The increased population of holes is initiated by the impact ionization of electrons in the collector-base region of a parasitic bipolar transistor. Electrons injected from the emitter (drain) of a parasitic n-p-n bipolar transistor into the base (substrate) can drift to the collector (source) where the high electrical field in the collector-base space charge region causes impact ionization and carrier multiplication. The impact ionization generated holes that gain enough energy to overcome the oxide barrier can be injected into the floating gate, resulting a very fast erase.

Effect of substrate bias on the performance and reliability of the split-gate source-side injected flash memory

The effects of the substrate bias on the characteristics of split-gate EEPROM/Flash memory cells have been investigated. It is experimentally demonstrated that applying negative substrate bias (NSB) can improve the programming and erasing speed significantly. The improvements can be attributed that NSB effectively increase the needed electrical fields for fast programming and erasing, respectively. Furthermore, the cycling endurance is improved considerably if NSB is applied for programming and erasing operation both.

A simple and efficient self-limiting erase scheme for high performance split-gate flash memory cells

This paper presents a fast self-limiting erase scheme for split-gate flash EEPROMs. In this technique the conventional erasing is rapidly followed by an efficient soft programming to correct for over-erase within the given voltage pulsewidth. The typical erasing time is about 400 ms and the final erased threshold voltage is accurately controlled via the base level read mode voltage within 0.3 V. The proposed scheme can he used for high throughput erasing in low voltage, high density, multilevel operation split-gate flash memory cells.

Performance of the 3-D PENCIL flash EPROM cell and memory array

A promising new 3-D Programmable Erasable Nonvolatile CylIndricaL (PENCIL) flash EPROM cell that offers significant area and performance advantages over conventional planar approaches has been implemented in a novel memory array. The 3-D PENCIL cell is a vertical device formed on the sidewalls of an etched silicon pillar. The cell is a single transistor stacked gate structure with the floating gate and control gate completely surrounding the pillar. Current flows vertically from the bit line contact at the top of the pillar to the source lying at the bottom of the pillar. When implemented in a novel self-aligned array, the cell size approaches the square of the minimum pitch and has an area less than half that of the conventional NOR type structure. The cell and array architecture also promise to be highly scalable. Experimental data reveals that the cells have up to 3/spl times/ larger read current than comparable planar cells, are suitable for 5 V only operation and have fast program and erase speeds at moderate voltage levels. Uniformity and endurance characteristics are also promising.< <ETX xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">&gt;</ETX>

Design and simulation of a high reliability non-volatile CMOS EEPROM memory cell compatible with scaling-down trends

Abstract A simple but high-reliability non-volatile electrically-programmable and erasable memory cell (EEPROM) based on a non-avalanche injection mechanism is presented. This memory cell is composed of a double gate CMOS inverter. Circuit design allows fast programming and erasing (tb < 20 ms) with a single supply voltage of 5 V (at MOSFET channel length L = 2 um and width = 20 μ). It employs a non-avalanche injection mechanism which guarantees a minimized oxide and interface degradation which leads to higher reliability and better operation stability. The EEPROM circuit latches the input data owing to the bidirectional hot carrier gate current. In this EEPROM, the majority of drawbacks of recent memories such as poor stability, long programming time, low reliability and the necessity of using two power supplies are removed. We then introduce a powerful simulation technique to compute V0(t), the output voltage, during programming and erasing cycles and also the programming time tb Computations have indicated good compatibility of the present EEPROM with the recent scaling-down trends in VLSI technology.

Germanium supersaturation during the crystallization of amorphous Te–Ge–Sn thin films

The structure and phase relations of Te–Ge–Sn thin films are examined with application to erasable optical storage media. Free energy data from the literature predict that the region of the Te–Ge–Sn phase diagram between Ge, Sn, and the TeGe–TeSn pseudobinary consists of one two-phase field [α–Ge and Te50 (GexSn1−x)50] and one three-phase field (α–Ge, β–Sn, and TeSn). Electron diffraction from five different Te–Ge–Sn films annealed at 623 K experimentally confirms this prediction. One composition from the two-phase field is deposited as a tri-layer film with the structure 150 nm SiO2/75 nm Te36.3Ge47.4Sn16.3/150 nm SiO2 on a grooved disk substrate, and the microstructure resulting from low-power (12 mW) CW and higher-power (∽50 mW) pulsed laser exposure is studied by transmission electron microscopy and electron diffraction. Of particular significance is that laser-induced crystallization produces a single-phase structure consisting of the Te–Ge–Sn compound phase which is supersaturated with respect to the excess Ge. This supersaturation leads to a disordering of the equilibrium NaCl-type structure of this phase. Crystallization of a micron-sized amorphous spot on a ∼200 ns time scale occurs by a diffusionless process. The fast erase times required by a phase-change optical recording application can thus be achieved in off-stoichiometric compound compositions by way of a nonequilibrium crystallization process.

PHASE CHANGE OPTICAL STORAGE - A CRITICAL ASSESSMENT

Recently there has been renewed interest in phase transformation based optical storage technology. Included among the many reasons for this interest has been the achievement of : (1) fast erase in conjunction with data stability, (2) demonstration of direct overwrite with good erasability, and in the last couple of years, (3) good progress in increasing the cyclability of the media. Direct overwrite has been demonstrated at media speeds from 1.25 to 22m/s. More than 2×106 cycles have been achieved with low BER. In addition, phase change media exhibits strong signal response at wavelengths shorter than 830nm and requires a much simpler optical head. In this paper we review past progress and assess the current status.

A 16 kbit electrically erasable PROM using n-channel Si-gate MNOS technology

A 16 kbit high performance EEPROM (electrically erasable PROM) is developed using n-channel Si-gate MNOS technology. The memory cell consists of an MNOS transistor and an addressing transistor connected in series. This cell structure and advanced processing technologies, including high temperature hydrogen anneal, realize high speed, high packing density, long data retention, and no read cycle limitations when compared to conventional p-channel Al-gate MNOS memories. The 16 kbit chip shows improved features: fast access time of 140 ns, fast program time of 1 ms, fast erase time of 100 ms, and low power dissipation of 210 mW. New high voltage devices and circuits are used to obtain high breakdown voltage, resulting in a wide margin for the program voltage supply pin. This device, fully pin-compatible with the 16 kbit EPROM (UV erasable PROM), outperforms currently used EPROMs as well as conventional MNOS memories in almost all respects.

Display applications of field-enforced phase transition in PLZT ceramics

Abstract Experiments to determine the applicability of field-enforced reversible transitions between antiferroelectric and ferroelectric phases in PLZT 7.9/70/30 ceramic to flat panel picture display devices reveal that the ceramic has three remarkable advantages over ordinary ferroelectric phase PLZT ceramics. They are: (1) the high transparency of the antiferroelectric PLZT 7.9/70/30 ceramic makes possible a higher contrast display material, (2) the absence of remanent polarization when no electric field is applied makes possible a faster erase display material, and (3) the linear relation between the field-induced scattered light intensity and the simultaneously induced ferroelectric polarization makes possible the control of gray-scale in a display by controlling the polarization charge switched.

Infrared laser addressing of media for recording and displaying of high-resolution graphic information

Projection display systems which use a scanned infra-red laser beam to thermally record graphic information on different media may offer a useful alternative to CRT and other display systems. Three different types of thermal-recording projection display systems are reviewed. Laser micromachining of thin bismuth film has proved to be a very simple and efficient way to obtain instant high-quality images which are also permanent. Variable amplitude light pulses produced by an intracavity modulated laser beam were used to write these images. With an average laser power of 20 mW, 8×10 mm2facsimile type continuous-tone images, with a resolution of 1300×2000 resolvable elements, were recorded in 4 s. Thermal writing on liquid crystals offers a unique and simple way to record and display high-quality high-resolution graphic images with the capabilities of fast total or local erase. A CW Nd:YA1G laser was used to write graphic and alphanumeric-type information on cholesteric and smectic-type liquid-crystal light valves. High quality black and white images with a resolution of 2000×2000 picture elements were recorded within 30×30 mm2of liquid-crystal cell frames. With 4 mW of laser power, images were recorded at a rate of 104resolvable elements per second. A contrast ratio of 7:1 was obtained with the cholesteric-type liquid-crystal light valve. The stored image was electrically erased in about 0.1 s. In smectic-type light valves, the contrast ratio was better than 10:1 and local erase was achieved by the application of an electric field while the laser beam locally heated the erased area.

Steroid effects on the substrate profile of a liver esterase

1. 1. Two synthetic steroids, 17-acetoxy-6α-trifluoromethylpregn-4-ene-3, 20 dione and 17-acetoxy-3β(β-carboxypropionyloxy)-6-trifluoromethyl-pregn-5-ene-20-one, were found to cause liver enlargement in rats and hypertrophy of the smooth endoplasmic reticulum. 2. 2. Evidence is now presented that the same two compounds cause a widening of the substrate specificity of a particular “fast esterase” zone. This is detected by starch electrophoresis of liver homogenate from adult treated rats. It is also shown that this wider specificity is normal in the young liver. 3. 3. The results are discussed from the point of view of hormones as inducers of enzymes and as regulators of gene action.

Serum esterases of Apodemus sylvaticus and Mus musculus

1. 1. The serum esterase patterns of adult (and, in the case of females, non-gravid) Apodemus sylvaticus and Mus musculus were compared by starch gel electrophoresis. The number of esterase fractions resolved was 23 in Apodemus and 19 in Mus. 2. 2. Tentative homologies between fractions of the two sera are suggested on tha basis of combined similarities in mobility, relative intensity (with a variety of ester substrates) and response to a series of inhibitors. 3. 3. Apodemus has more intense total esterolytic activity, and this is mainly due to a cluster of fast esterase fractions which are more numerous, more intense and more diversified than the corresponding region in Mus. It would appear tha evolutionary divergence has centred on this group more than in other parts of the esterase complement of the two species.