Fast Architecture Research Articles

Faster diffusion model with improved quality for particle cloud generation

Building on the success of PC-JeDi we introduce PC-Droid, a substantially improved diffusion model for the generation of jet particle clouds. By leveraging a new diffusion formulation, studying more recent integration solvers, and training on all jet types simultaneously, we are able to achieve state-of-the-art performance for all types of jets across all evaluation metrics. We study the trade-off between generation speed and quality by comparing two attention based architectures, as well as the potential of consistency distillation to reduce the number of diffusion steps. Both the faster architecture and consistency models demonstrate performance surpassing many competing models, with generation time up to two orders of magnitude faster than PC-JeDi and three orders of magnitude faster than . Published by the American Physical Society 2024

Optimizing RNNs for EMG Signal Classification: A Novel Strategy Using Grey Wolf Optimization.

Accurate classification of electromyographic (EMG) signals is vital in biomedical applications. This study evaluates different architectures of recurrent neural networks for the classification of EMG signals associated with five movements of the right upper extremity. A Butterworth filter was implemented for signal preprocessing, followed by segmentation into 250 ms windows, with an overlap of 190 ms. The resulting dataset was divided into training, validation, and testing subsets. The Grey Wolf Optimization algorithm was applied to the gated recurrent unit (GRU), long short-term memory (LSTM) architectures, and bidirectional recurrent neural networks. In parallel, a performance comparison with support vector machines (SVMs) was performed. The results obtained in the first experimental phase revealed that all the RNN networks evaluated reached a 100% accuracy, standing above the 93% achieved by the SVM. Regarding classification speed, LSTM ranked as the fastest architecture, recording a time of 0.12 ms, followed by GRU with 0.134 ms. Bidirectional recurrent neural networks showed a response time of 0.2 ms, while SVM had the longest time at 2.7 ms. In the second experimental phase, a slight decrease in the accuracy of the RNN models was observed, standing at 98.46% for LSTM, 96.38% for GRU, and 97.63% for the bidirectional network. The findings of this study highlight the effectiveness and speed of recurrent neural networks in the EMG signal classification task.

Robust Myocardial Perfusion MRI Quantification with DeepFermi.

Stress perfusion cardiac magnetic resonance is an important technique for examining and assessing the blood supply of the myocardium. Currently, the majority of clinical perfusion scans are evaluated based on visual assessment by experienced clinicians. This makes the process subjective, and to this end, quantitative methods have been proposed to offer a more user-independent assessment of perfusion. These methods, however, rely on time-consuming deconvolution analysis and are susceptible to data outliers caused by artifacts due to cardiac or respiratory motion. In our work, we introduce a novel deep-learning method that integrates the commonly used Fermi function with a neural network architecture for fast, accurate, and robust myocardial perfusion quantification. This approach employs the Fermi model to ensure that the perfusion maps are consistent with measured data, while also utilizing a prior based on a 3D convolutional neural network to generalize spatio-temporal information across different patient data. Our network is trained within a self-supervised learning framework, which circumvents the need for ground-truth perfusion labels that are challenging to obtain. Furthermore, we extended this training methodology by adopting a technique that ensures estimations are resistant to data outliers, thereby improving robustness against motion artifacts. Our simulation experiments demonstrated an overall improvement in the accuracy and robustness of perfusion parameter estimation, consistently outperforming traditional deconvolution analysis algorithms across varying Signal-to-Noise Ratio scenarios in the presence of data outliers. For the in vivo studies, our method generated robust perfusion estimates that aligned with clinical diagnoses, while being approximately five times faster than conventional algorithms.

Fast Hardware Implementation for Extended GCD of Large Numbers in Redundant Representation

The extended greatest common divisor (XGCD) of large numbers is a commonly used and computing-intensive operation in cryptography. The growing demands for high-speed cryptography applications urge for fast XGCD implementation. However, it is challenging to design fast architectures for XGCD because of its complex operations and tight data dependency. In this paper, we propose a low-latency and high-efficiency architecture for XGCD by using a modified extended k-ary algorithm in redundant data representation. We modify the original k-ary algorithm by adopting a parameter δ to reduce computing delay and applying a hardware-friendly method to Bézout coefficients. The redundant signed digit (RSD) representation is selected to avoid carry propagation and achieve high clock frequency. We devise high-parallel and low-latency architectures for the proposed algorithms with k = 2, 4, and 8. The designs are coded in SystemVerilog and synthesized using TSMC 28-nm CMOS technology. The implementation results show that for the data bit width of 1024, the design with k = 8 achieves the shortest latency among different values of k, which is about 1.5x faster than the prior art and only needs 472 ns.

Verification and Validation of ITER Interlock System Fast Architecture According to IEC 61508 Standard

The ITER Interlock Control System (ICS) requires the application of the IEC 61508 standard for all mission-critical (known as investment protection) control functions. Such functions must detect the events of the integrated physical processes and distribute them to the actuators with hard real-time constraints on the order of milliseconds or even microseconds. Systems able to achieve these timing requirements are often bespoke FPGA-based solutions, which are a well-known challenge to IEC 61508 processes. However, to minimize the variety of components and simplify the procurement process for an international supplier base, ITER decided to standardize the use of Commercial Off-The-Shelf (COTS) devices. The COTS selected for the ICS was the FPGA-based CompactRIO NI 9159 chassis (and several adapter I/O modules), provided by National Instruments (NI). This COTS requires the use of a high-level language (LabVIEW-FPGA) and the associated integrated development tools to develop the FPGA functionality. Therefore, it is necessary to ensure the required assurance that a COTS device is of sufficient quality, fit for purpose, and can be properly integrated into an investment protection control loop with the necessary level of systematic capability during the development process. This paper describes in detail the method ITER uses to perform the verification and validation according to the IEC 61508 standard recommendations, for the logic configuration generated by LabVIEW-FPGA for these COTS, after the compilation of high-level language sources designed during the development.

DuFNet: Dual Flow Network of Real-Time Semantic Segmentation for Unmanned Driving Application of Internet of Things

The application of unmanned driving in the Internet of Things is one of the concrete manifestations of the application of artificial intelligence technology. Image semantic segmentation can help the unmanned driving system by achieving road accessibility analysis. Semantic segmentation is also a challenging technology for image understanding and scene parsing. We focused on the challenging task of real-time semantic segmentation in this paper. In this paper, we proposed a novel fast architecture for real-time semantic segmentation named DuFNet. Starting from the existing work of Bilateral Segmentation Network (BiSeNet), DuFNet proposes a novel Semantic Information Flow (SIF) structure for context information and a novel Fringe Information Flow (FIF) structure for spatial information. We also proposed two kinds of SIF with cascaded and paralleled structures, respectively. The SIF encodes the input stage by stage in the ResNet18 backbone and provides context information for the feature fusion module. Features from previous stages usually contain rich low-level details but high-level semantics for later stages. The multiple convolutions embed in Parallel SIF aggregate the corresponding features among different stages and generate a powerful global context representation with less computational cost. The FIF consists of a pooling layer and an upsampling operator followed by projection convolution layer. The concise component provides more spatial details for the network. Compared with BiSeNet, our work achieved faster speed and comparable performance with 72.34% mIoU accuracy and 78 FPS on Cityscapes Dataset based on the ResNet18 backbone.

SNAS: Fast Hardware-Aware Neural Architecture Search Methodology

Recently, automated neural architecture search (NAS) emerges as the default technique to find a state-of-the-art (SOTA) convolutional neural network (CNN) architecture with higher accuracy than manually designed architectures for image classification. In this article, we present a fast hardware-aware NAS methodology, called S3NAS, reflecting the latest research results. It consists of three steps: 1) supernet design; 2) Single-Path NAS for fast architecture exploration; and 3) scaling and post-processing. In the first step, we design a supernet, superset of candidate networks with two features: one is to allow stages to have a different number of blocks, and the other is to enable blocks to have parallel layers of different kernel sizes (MixConv). Next, we perform a differential search by extending the Single-Path NAS technique to support the MixConv layer and to add a latency-aware loss term to reduce the hyperparameter search overhead. Finally, we use compound scaling to scale up the network maximally within the latency constraint. In addition, we add squeeze-and-excitation (SE) blocks and h-swish activation functions if beneficial in the post-processing step. Experiments with the proposed methodology on four different hardware platforms demonstrate the effectiveness of the proposed methodology. It is capable of finding networks with better latency–accuracy tradeoff than SOTA networks, and the network search can be done within 4 h using TPUv3.

Efficient FPGA Parallelization of Lipschitz Interpolation for Real-Time Decision-Making

One of the main open challenges in the field of learning-based control is the design of computing architectures able to process data in an efficient way. This is of particular importance when time constraints must be met, as, for instance, in real-time decision-making systems operating at high frequencies or when a vast amount of data must be processed. In this respect, field-programmable gate array (FPGA)-based parallel processing architectures have been hailed as a potential solution to this problem. In this article, a low-level design methodology for the implementation on FPGA platforms of Lipschitz interpolation (LI) algorithms is presented. The proposed design procedure exploits the potential parallelism of the LI algorithm and allows the user to optimize the area and energy resources of the resulting implementation. Besides, the proposed design allows to know in advance a tight bound of the error committed by the FPGA due to the representation format. Therefore, the resulting implementation is a highly parallelized and a fast architecture with an optimal use of the resources and consumption and with a fixed numerical error bound. These facts flawlessly suit the desirable specifications of learning-based control devices. As an illustrative case study, the proposed algorithm and architecture have been used to learn a nonlinear model predictive control law applied to self-balance a two-wheel robot. The results show how computational times are several orders of magnitude reduced by employing the proposed parallel architecture, rather than sequentially running the algorithm on an embedded ARM-CPU-based platform.

An Area Energy-Efficient VLSI Architecture using Hybrid Wide-Operand adder

Consumer electronics markets have raised demand for high-speed, low- power adders with big operands for use in new portable systems. Traditional fast adder architectures, such as parallelprefix adders, consume a lot of power when I have a lot of operands. One of the most promising ways for achieving a trade-off between delay and power consumption for the addition of big operands is the hybrid design. This reduces the area of the summation blocks at the significant positions without sacrificing speed. Furthermore, My provides a new hybrid adder architecture for large operands, based on the conceptthat in large parallel- prefix adders, the least significant carriers are produced considerably sooner than the most significant ones. As a result, the authors avoid incorporating fast architectures associated with the application of carries to the final summing leastsignificant bits, which has no effect on the critical path. of the carries is generated and propagated within the proposed adder's carry network to reduce delay. VLSI implementation results using 45- nm-TSMC technology reveal that the suggested adder saves more than 12% of energy and reduces the area-delay-product by more than 5% when compared to state-of-the-art other operand adders. The post- synthesis results of the proposed adder reported is much fasterthan the CS3A for 32-,64- and 128- bit architecture respectively. Moreover, it has a lesser area, lower power dissipation and smaller delay than the adder. Also, the proposed adder achieves the lowest ADP and PDP than the existing adder techniques.

Fast asymmetric encryption and decryption of SimpleMatrix scheme for Internet of Things

Asymmetric cryptography plays an essential role in many areas, including cloud computing, big data, blockchain, and the Internet of Things (IoT). However, most of them are based on the difficulty of factorizing large numbers or discrete logarithm problems, which are not secure to quantum computer attacks. SimpleMatrix is a new multivariate encryption scheme based on simple matrix multiplications, which can resist quantum computer attacks. Because of the low speed and demands of large finite fields, SimpleMatrix is limited in applications that use small finite fields. As a result, it is critical to improve the efficiency of SimpleMatrix to make its applications broader. In this paper, we speed up the encryption and decryption of SimpleMatrix by building efficient small finite field arithmetics based on Field-Programmable Gate Arrays (FPGAs) technology. We propose a fast architecture for encryption and decryption of SimpleMatrix based on table look-up based composite field multiplications and inversions and fast Gauss–Jordan elimination for solving systems of linear equations in a composite field. We test and verify the hardware architecture of SimpleMatrix on an FPGA, and the experimental results confirm our estimates and comparisons show that our design is much faster than other implementations. Thus, the hardware architecture can be used in FPGA-based systems of cloud computing, IoT, etc., for accelerating encryption and decryption.

Design of FFNN architecture for power quality analysis and its complexity challenges on FPGA

As we all know, power quality (PQ) issues are a major concern these days. Field programmable gate array (FPGA) are essential in PQ analysis, particularly in smart meters for data processing, storage, and transmission. One of the most significant advantages of FPGA is its reconfigurability, with vast hardware resources that can be used to implement complex as well as time-critical data processing units. Because the FPGA architecture supports fixed point arithmetic, data loss occurs in the data path unit, necessitating the realization of the PQ event detection module, and classification model to be more accurate than software implementation algorithms. The majority of the work reported, with feed forward neural network (FFNN) structure occupying large number of multipliers and adders for classification, most of the work reported has not addressed to minimize the data path resources for FFNN instead have addressed in improving classification accuracy. Based on these issues, this paper addresses the implementation challenges in FFNN architecture design by proposing improved and fast architectures. The proposed FFNN architecture design using optimum resources. The FFNN based classifier are designed to perform PQ event detection and classification with 99.5% accuracy. The FFNN processor operates at maximum frequency of 238 MHz.

Methods to develop high throughput hardware architectures for HEVC Deblocking Filter using mixed pipelined-block processing techniques

This paper presents four highly efficient hardware architectures for Deblocking Filter (DBF) which can be used in High-Efficiency Video Coding (HEVC) encoder or decoder. Mixed pipelined and block processing techniques are used in these architectures to achieve high throughput while consuming minimum possible area. In these proposed architectures, the coding tree unit with 64 × 64 blocks of pixels in a frame are processed in the form of 32 × 32 blocks of pixels. Once the deblocking filtering process completes, these pixels will be stored in block memory via output buffer. Experimental results on Application Specific Integrated Circuit (ASIC) and Field Programmable Gate Array (FPGA) platforms demonstrate that the proposed hardware architecture has a throughput improvement of 69% to 83% at the expense of slightly increased gate count compared to the previously known architectures of DBF. With 180 nm technology library, the fastest architecture out of the four achieves a throughput of 162 FPS (Frames per second) at an operating frequency of 250 MHz.

Spintronics-compatible Approach to Solving Maximum-Satisfiability Problems with Probabilistic Computing, Invertible Logic, and Parallel Tempering

The search of hardware-compatible strategies for solving NP-hard combinatorial optimization problems (COPs) is an important challenge of today s computing research because of their wide range of applications in real world optimization problems. Here, we introduce an unconventional scalable approach to face maximum satisfiability problems (Max-SAT) which combines probabilistic computing with p-bits, parallel tempering, and the concept of invertible logic gates. We theoretically show the spintronic implementation of this approach based on a coupled set of Landau-Lifshitz-Gilbert equations, showing a potential path for energy efficient and very fast (p-bits exhibiting ns time scale switching) architecture for the solution of COPs. The algorithm is benchmarked with hard Max-SAT instances from the 2016 Max-SAT competition (e.g., HG-4SAT-V150-C1350-1.cnf which can be described with 2851 p-bits), including weighted Max-SAT and Max-Cut problems.

Igwo-Ss: Improved Grey Wolf Optimization Based on Synaptic Saliency for Fast Neural Architecture Search in Computer Vision

Igwo-Ss: Improved Grey Wolf Optimization Based on Synaptic Saliency for Fast Neural Architecture Search in Computer Vision

Spectral–Spatial Transformer Network for Hyperspectral Image Classification: A Factorized Architecture Search Framework

Neural networks have dominated the research of hyperspectral image classification, attributing to the feature learning capacity of convolution operations. However, the fixed geometric structure of convolution kernels hinders long-range interaction between features from distant locations. In this article, we propose a novel spectral–spatial transformer network (SSTN), which consists of spatial attention and spectral association modules, to overcome the constraints of convolution kernels. Also, we design a factorized architecture search (FAS) framework that involves two independent subprocedures to determine the layer-level operation choices and block-level orders of SSTN. Unlike conventional neural architecture search (NAS) that requires a bilevel optimization of both network parameters and architecture settings, the FAS focuses only on finding out optimal architecture settings to enable a stable and fast architecture search. Extensive experiments conducted on five popular HSI benchmarks demonstrate the versatility of SSTNs over other state-of-the-art (SOTA) methods and justify the FAS strategy. On the University of Houston dataset, SSTN obtains comparable overall accuracy to SOTA methods with a small fraction (1.2%) of multiply-and-accumulate operations compared to a strong baseline spectral–spatial residual network (SSRN). Most importantly, SSTNs outperform other SOTA networks using only 1.2% or fewer MACs of SSRNs on the Indian Pines, the Kennedy Space Center, the University of Pavia, and the Pavia Center datasets.

The Impact of Interstitial Diseases Patterns on Lung CT Segmentation.

Lung segmentation represents a fundamental step in the development of computer-aided decision systems for the investigation of interstitial lung diseases. In a holistic lung analysis, eliminating background areas from Computed Tomography (CT) images is essential to avoid the inclusion of noise information and spend unnecessary computational resources on non-relevant data. However, the major challenge in this segmentation task relies on the ability of the models to deal with imaging manifestations associated with severe disease. Based on U-net, a general biomedical image segmentation architecture, we proposed a light-weight and faster architecture. In this 2D approach, experiments were conducted with a combination of two publicly available databases to improve the heterogeneity of the training data. Results showed that, when compared to the original U-net, the proposed architecture maintained performance levels, achieving 0.894 ± 0.060, 4.493 ± 0.633 and 4.457 ± 0.628 for DSC, HD and HD-95 metrics, respectively, when using all patients from the ILD database for testing only, while allowing a more effficient computational usage. Quantitative and qualitative evaluations on the ability to cope with high-density lung patterns associated with severe disease were conducted, supporting the idea that more representative and diverse data is necessary to build robust and reliable segmentation tools.

Segmentation of the Scaphoid Bone in Ultrasound Images

Abstract For the percutaneous fixation of scaphoid fractures, navigated approaches have been proposed to facilitate screw placement. Based on ultrasound imaging, navigation can be carried out in a cost-effective and fast manner, furthermore avoiding harmful radiation. For this purpose, a fast and efficient architecture for the automated segmentation of scaphoid bone in ultrasound volume images is needed. Methods: For 2D segmentation of the scaphoid, two architectures are taken into account: 2D nnUNet and Deeplabv3+. These architectures are trained and evaluated on a newly created dataset consisting of 67 annotated in-vivo ultrasound volume images (4576 slice images). Results: In terms of Dice coefficient, the 2D nnUNet achieves 0.67 compared to 0.57 for the Deeplabv3+. In terms of distance metrics, the 2D nnUNet shows an average symmetric surface distance error of 0.66mm, while the Deeplabv3+ achieves 0.55mm. Conclusion: Fast and accurate segmentation of the scaphoid in ultrasound volumes is feasible. Both architectures show competitive results.

A Reconfigurable Memory based Fast VLSI Architecture for Histogram Computation

Histogram computation is the crucial task used in processing so many image guided applications like pattern recognition, image segmentation etc. Image registration is one of the fundamental techniques for pre-processing of the images. Registration is the process of overlaying multiple images to geometrically align them. In medical Image processing, the improper registration can have negative impact on the analysis of the image which influences the final diagnosis. The accurate result of image registration is obtained by matching of multimodal images. Mutual Information is one of the commonly used techniques to find the similarity measurement between multi-modal images. Measurement of similarity requires a computation of histogram of individual images and joint histogram between the images. The hardware implementation of histogram computation has advantages in terms of flexible design, low power consumption, high speed, less execution time than the software implementation. This paper proposed a parallel algorithm for histogram computation. A memory based pipeline architecture is designed for implementing the proposed algorithm. The hardware mapping of the algorithm on FPGA is proposed and simulating them using Xilinx software tools.

FPGA‐based implementation of floating point processing element for the design of efficient FIR filters

Numerous applications based on very large scale intergration (VLSI) architecture suffer from large size components that lead to an error in the design of the filter during the stages of floating point arithmetic. Hence, it is necessary to change the architectural model that increases the design complexity and the time delay effect. The issue encountered in the VLSI architectures for finite impulse response (FIR) filter is the increased number of components, especially delay elements. For the VLSI architecture reconfigured with reduced register usage, this article provides the floating point processing element (FPPE) implementation with Cross-Folded Shifting. The proposed FIR filter system reduces the number of components in the circuit which increases the complexity and high delay rate in the logical operation. The system has a comparatively reduced delay rate and power consumption. Hence, an efficient fast architecture based on the FPPE method is developed in this paper.

Abstract PO-029: CliP: A model-based method for subclonal architecture reconstruction using regularized maximum likelihood estimation

Abstract Background Subpopulations of tumor cells characterized by mutation profiles may confer differential fitness to treatment and prognosis across cancers. Understanding subclonal architecture has the potential to provide biological insight into tumor evolution and advance the precision treatment of cancers. Recent methods comprehensively integrate single nucleotide variants (SNVs) and copy number alterations (CNAs) to reconstruct subclonal architecture using whole-genome sequencing (WGS) data from bulk tumor samples. However, most methods follow a Bayesian framework and require extensive computational resources, a prior knowledge of the number of subclones, as well as ad hoc post-analysis data processing. Altogether this creates a bottleneck in processing time in large-scale studies. Objectives The primary objective of this study is to introduce a fast and accurate subclonal architecture reconstruction method, which utilizes a model-based clustering approach and addresses all the limitations above. Methods We introduce a novel model-based clustering method: Clonal structure identification through pairwise penalization (CliP). CliP assumes the number of reads observed with variant alleles follows a binomial model, which is a function of mutation cellular prevalence (CP), copy number aberrations, and tumor purity. We propose to minimize a penalized likelihood of this model with a SCAD penalty on CPs across pairs of mutations. The optimization problem is then efficiently solved via Alternating Direction Method of Multipliers (ADMM). As a subclonal reconstruction algorithm, CliP attempts to infer the population structure of heterogeneous tumors, and is the first method to utilize a regularized maximum likelihood framework in subclonal reconstruction, therefore benefiting from its computational efficiency in parameter estimation. Results Rigorous and extensive simulation results demonstrate that CliP is 100 times faster than MCMC-based algorithms without decreased performance. Unlike previous models, the CliP model is applicable to regions with or without CNAs. Furthermore, CliP generates subclonal structure without prior knowledge or post-processing. In an application to WGS data from Pan-Cancer Analysis of Whole Genomes (PCAWG), it only took 8 hours to process 2,500 tumor samples. Conclusion Since CliP executes quickly, it is ultimately suitable for 1) processing large datasets with thousands of samples and 2) participation in a group of methods to generate consensus calls. As the sizes of datasets continue to grow, CliP represents an important step towards fast and accurate subclonal reconstruction. Citation Format: Yujie Jiang, Kaixian Yu, Hongtu Zhu, Wenyi Wang. CliP: A model-based method for subclonal architecture reconstruction using regularized maximum likelihood estimation [abstract]. In: Proceedings of the AACR Virtual Special Conference on Tumor Heterogeneity: From Single Cells to Clinical Impact; 2020 Sep 17-18. Philadelphia (PA): AACR; Cancer Res 2020;80(21 Suppl):Abstract nr PO-029.