Fan-Out Wafer Level Packaging Process Research Articles

A Novel 2D/3D X-ray Microscopy Alignment and Inspection Solution for Thermocompression Bonding (TCB) in a Highly Integrated Flip Chip Fan-Out Wafer Level Package (FO-WLP)

As packaging drives to extend the capabilities of Moore’s Law via heterogenous integration, numerous bonding technologies have emerged as potential pathways, allowing for integration of both a variety of devices in the lateral space as well as vertical integration of chips via stacking. As vertical integration on interposer becomes more complex due to shrinking CDs and increasing die layers, alignment and shape control in the bonding process becomes critical. Thermocompression bonding (TCB) is particularly well-suited for larger die, where localized reflow allows a better control of chip gap height and tilt throughout the bonding process. TCB systems require both high accuracy and repeatability in all dimensions to provide a reliable system in package. While a 2D system can provide a plan view assessment of a single bond layer between two chips, it falls short in characterizing the critical z-dimension in a highly integrated chip stacking scenario. Therefore a robust solution is needed for both system alignment validation in the x,y plane as well as a capability to explore gap height and bump quality/buried issues in high aspect ratio TSV. This paper will explore an x-ray application of a stacked 15-layer die-to-interposer structure to qualitatively validate overall health of the TSV (bond, pad, fill) via a nondestructive volumetric method as well as quantitatively evaluate stacked die for via/ball/pad alignment to determine overall alignment shift during the bonding process. In the test vehicle for a flip chip FO-WLP process flow first presented by IMEC, a silicon (Si) bridge is utilized to connect the logic and through-package via dies with a bump pitch of 20µm for the logic die interconnect. This is done by carefully aligning the logic dies on the carrier and then placing the through-package dies aligned to the carrier and logic dies. In the final step, a high accuracy placement and stacking TCB tool attaches the Si bridge. To perform an accurate assessment for bump alignment and bond quality, an initial high-resolution 3D x-ray scan is performed on a 1.5mm3 region of interest with over 2,000 individual projections at a 1.4µm voxel resolution with a 4x objective, taking approximately two hours. The dataset is put through a deep-learning algorithm which generates an AI model. This model is then applied to a faster scan of 15 minutes with a 1.4µm voxel resolution for the same field of view (FOV) on a nearby array and the data is collected and processed. To verify alignment of the entire sample, data is collected on the tightest pitch (in this case 20µm) oriented in both the vertical (x) and horizontal (y) plane in the through-silicon via (TSV) region. The z-plane is analyzed and processed by computer vision algorithms, and individual interconnects are then quantified and sorted for solder height (z), width (x,y) and TSV misalignment (deviation from expected center, x1y1 → x2y2). To validate the model, a high-resolution uncorrected 20h scan and a 15min scan based on deep learning are collected for the same region of interest (ROI). The data is comparable. Furthermore, the global misalignment data between both datasets demonstrates similar misalignment propagating through the 15-layer stack.

Selective Copper Electrodeposition for Redistribution Layer by Varying Concentration and Agitation of Janus Green B

A fine-pitch redistribution layer (RDL) for high-performance devices in a fan-out wafer-level package (FOWLP) is required in semiconductor packaging technology. The damascene process for fine-pitch RDL has been studied for several years, which has been introduced to overcome the etching problems. Although surface planarization for removing overburden is necessary for the damascene process in RDL, it adds high cost to the FOWLP process. Selective Cu electrodeposition is a method used to prevent overburden. Janus Green B (JGB) is utilized as a leveler in Cu electrodeposition and has properties that depend on concentration and agitation. These properties affected the Cu deposition rate according to the pattern position. Thus, the electrochemical properties of JGB were investigated based on the concentration of JGB and agitation. Furthermore, the effect of JGB on the crystalline structure of the Cu film was examined. Additionally, changes in the growth behavior of the Cu nuclei caused by JGB were observed during the initial stage of chronoamperometry. Based on these results, selective Cu electrodeposition was successfully performed on the patterned substrate using the difference in the concentration of JGB and agitation.

Novel Temporary Bonding Film Adapted to Xenon Flash Lamp De-bonding System for FOWLP Application

Temporary bonding film (TBF) is one of the key materials for assembly process of fan out wafer level package (FOWLP). In this paper, we have proposed a novel TBF and xenon flash lamp de-bonding system. The TBF was mainly composed of cross-linkable and low-polarity polymers to meet the various requirement for not only easy peeling-off after assembly but also stability against thermal and chemical environment exposed in FOWLP process. In order to evaluate applicability of the developed material, die-first/face up test wafer was assembled. As a result, it was found that the TBF has high stability and can be de-bonded by xenon light irradiation. In addition, the die shift through assembly process was within the estimated range. These results offer that the developed TBF is practically applicable for FOWLP assembly process.

Experimental and simulative study of warpage behavior for fan-out wafer-level packaging

Controlling warpage effects in fan-outwafer-level packaging (FO-WLP) is of key importance for realizing reliable and cost-efficient system in packages (SiPs). However, warpage effects can occur during the manufacturing process, caused by a combination of different processing temperatures, different materials, and the changing properties of the materials (e.g. polymerization and related cure shrinkage). One approach to controlling warpage could be realized by assessing a numerical simulation workflow of the FO-WLP process chain, in which the relevant material properties and geometry are used as input. Since there are many different steps included in the FO-WLP process, accompanied by complex material behavior, this workflow is not straight-forward. In the present paper, the first FO-WLP processing steps are investigated in detail by performing extensive thermo-mechanical material characterization, temperature-dependent warpage measurements, and numerical simulations. The investigation focuses on two epoxy mold compound (EMC) materials with completely different physical properties.The warpage measurements of bi-material (EMC and silicon) samples reveal an irreversible effect after passing certain processing temperatures, which are significant for final warpage at room temperature. A new approach to measuring the coefficient of thermal expansion (CTE) is discussed, using a temperature profile based on the temperature in the process, instead of the three identical temperature ramps suggested by the typical standards. This new approach makes it possible to determine possible shrinkage effects. Within the simulation model, the hysteresis effect observed in the experiment is taken into account by adding a shrinkage strain as well as changing the CTE values during the process. A very good agreement between the experiment and simulation is achieved, which is shown for several demonstrators with different epoxy mold compound materials and thicknesses.

Investigation of Warpage for Multi-Die Fan-Out Wafer-Level Packaging Process.

This paper focuses on characterizing the evolution of warpage, effects of epoxy molding compound (EMC), and effects of carrier 2 (the second carrier in the process) of 12 inch RDL-first multi-die fan-out wafer-level packaging (FOWLP) during the manufacturing process. The linear viscoelasticity properties of EMC and polyimide (PI) were characterized using dynamic mechanical analysis (DMA) in the frequency domain at different temperatures., The elastic and viscoelastic model were used for PI and EMC, the finite element analyses (FEA) of the cured structure were carried out and the results were compared with the test results. The viscoelastic properties of the EMC in the FEA could predict the wafer warpage more accurately. The FEA and experiments were used to investigate the evolution of warpage. The molding had a great influence on the warpage. The effects of the EMC and carrier 2 were also investigated with FEA. The wafer warpage could be reduced by lowering the thickness of the EMC, increasing the thickness of carrier 2, and selecting EMC and carrier 2 with a matched coefficient of thermal expansion (CTE).

A Hybrid Antenna in Package Solution Using FOWLP Technology

Abstract Widespread millimeter wave applications have promoted rapid development of system in package (SiP) and antenna in package (AiP). Most AiP structures take the form of flip chip onto antenna substrate, where signal interconnect losses are introduced by solder bumps. The integration may be unavailable for chips with fine pad pitches. Fan-out wafer level package (FOWLP) with antenna patterning on redistributed layers (RDL) is another method for millimeter wave AiP. In this project, a hybrid integration AiP structure is developed. The microwave monolithic integrated circuit (MMIC) chip and antenna unit are integrated with chip-first FOWLP process. Multilayer organic substrate with fine pitch RDL interconnections meets the requirements of wideband antenna design. Modified coplanar waveguide is adopted to feed 2 × 2 aperture array formed on RDL layer. Package warpage is measured using Shadow Moire techniques. The antenna forms an aperture-coupled stacked patch array with bandwidth 25% and gain 8.5dBi for 60 GHz digital communication system. The proposed approach is a convenient hybrid integration solution adopting FOWLP process for millimeter wave AiP systems.

Warpage Simulation During Fan-Out Wafer-Level Packaging Process with Uncertainty of Material Properties.

Along with the reduction in semiconductor chip size and enhanced performance of electronic devices, high input/output density is a desired factor in the electronics industry. To satisfy the high input/output density, fan-out wafer-level packaging has attracted significant attention. While fan-out wafer-level packaging has several advantages, such as lower thickness and better thermal resistance, warpage is one of the major challenges of the fan-out wafer-level packaging process to be minimized. There have been many studies investigating the effects of material properties and package design on warpage using finite element analysis. Current warpage simulations using finite element analysis have been routinely conducted with deterministic input parameters, although the parameter values are uncertain from the manufacturing point of view. This assumption may lead to a gap between the simulation and the field results. This paper presents an uncertainty analysis of wafer warpage in fan-out wafer-level packaging by using finite element analysis. Coefficient of thermal expansion of silicon is considered as a parameter with uncertainty. The warpage and the von Mises stress are calculated and compared with and without uncertainty.

Effect of Thermal Cycling on the Thermal and Mechanical Properties of Dielectric Materials

Photosensitive polymers or dielectric materials such as polyimides (PIs) have been used in fan-out wafer-level packaging process (FOWLP) as a redistribution layer for quite some time. In the condensed 2-D and 3-D packaging processes, the dielectric materials are applied multiple times to create as many as four or five redistribution layers. At the end of the process, the first layer may experience up to four times of heat cycles in which the polymer properties may change. However, the effect of heat cycles on properties of dielectric film as well as their contributions to the wafer-level warpage is still unclear. To understand the changes of materials’ properties after several heat cycles, the thermal and thermo-mechanical properties of negative-tone and positive-tone types of dielectric films are characterized by using the thermomechanical analysis (TMA), dynamic mechanical analysis (DMA), and thermogravimetric analysis (TGA). The glass transition temperature ( ${T}_{g}$ ), coefficient of linear thermal expansion (CTE), and modulus (storage, ${E}'$ , and loss, ${E}''$ ) are analyzed and compared. In addition, the morphology of the films before and after heat cycles is also analyzed.

Novel glass substrates for minimizing thermal stress development during electronic device packaging process

Abstract Glass can be utilized for support or career substrate in large size packaging process since it has excellent mechanical and optical properties. However, the thermal stress caused by a mismatch of coefficient of thermal expansion (CTE) causes an unneglectable warpage during a thermal process. In order to overcome this thermal stress issue, we have developed novel glasses that have finely tuned CTE characteristics to fit each packaging process. In this paper, we will report on a glass substrate whose CTE is perfectly matched with that of Si, and a series of glass substrates whose CTEs are controlled in sub-ppm order and within the range of 3.3 ~ 12.0 ppm/°C. To evaluate the effect of glass CTE on the thermal stress management, the warpage behavior of Si wafer after glass wafer bonding were investigated by both numerical simulation and experiment. Both results indicate that a small CTE mismatch can cause an unneglectable wafer warpage during the thermal process. Thus sub-ppm order control of glass CTE is essential for minimizing thermal stress development in large size packaging process. The glass substrate with Si matched CTE is suitable for the process where glass and Si are contact directly, e.g. Si back grinding process or through glass via (TGV) technology. The series of glass substrates whose CTEs are finely controlled in a high range are useful when the packaging process utilizes high amount of resins, such as Fan-Out wafer level packaging process.