Fan-out Panel Level Packaging Research Articles

Fan-out panel-level package warpage and reliability analyses considering the fabrication process

With the continuous advancement of IC packaging technology, 3D and 2.5D packaging systems have emerged as the prevailing trends. The advantages of large area and high I/O density have made fan-out panel-level packaging (FOPLP) been considered as one of the best package types for 3D and 2.5D packaging applications. The discussions about FOPLP have been popular recently. Warpage and reliability of FOPLP are the main concerns of packaging engineers. However, it was found that warpage and reliability of FOPLP are strongly related to the fabrication process but not many research works have been published. Thus, reliability analysis procedure considering the residual stress of fabrication process was proposed in this paper to observe warpage and stress distribution during fabrication process. Then, this research procedure facilitates subsequent fatigue life calculations and predicts reliability of the package.First, the thermal stresses and warpage of the redistribution layer-first (RDL-first) process were conducted for an entire panel. Next, warpage and thermal stress analyses were conducted for a strip encapsulated with an epoxy molding compound (EMC) during compression molding. Then, a reliability analysis was conducted with an IC unit and incorporated the consideration of the residual stress induced during the fabrication processes.The compression molding analysis utilized the pressure–volume–temperature–cure (P–V–T–C) model to account for both the volume shrinkage caused by a thermal mismatch and the chemical shrinkage. Furthermore, dual shift factor model was used to model the viscoelastic behavior of EMC in this study during PMC analysis effectively.An observation of the stress distribution for an IC unit revealed that the maximum stress position was at the solder ball near the periphery, with a stress value of 147.309 MPa. The fatigue life calculated using the modified Coffin–Manson fatigue model was 417 cycles.

Using Outlier Control Technology with Feedforward Lithography to Address Die Shifting and Pattern Distortion Challenges in Fan-Out Panel-Level Packaging

Fan-out panel-level packaging (FOPLP) is a packaging technology able to meet the requirements of heterogeneous integration while reducing costs for manufacturers. However, FOPLP faces several significant process challenges. One of these is die shifting, which is a result of the reconstitution process in die-first FOPLP. Pattern distortion is another challenge, one caused by panel deformation in redistribution layer-first FOPLP. These issues cause die and patterns to move away from their nominal positions. If die shifting and pattern distortion are not well addressed during the lithography process, they will result in overlay errors and low overlay yield. Outlier control technology with feedforward lithography is proposed to address these die-shifting and pattern-distortion challenges. Outlier control is based on site-by-site corrections and uses an algorithm to recognize outliers in the substrate, eliminate their negative impacts and optimize overlay corrections to ensure good overlay yield. Additionally, feedforward lithography can further reduce the negative impact to throughput caused by the time lost addressing site-by-site corrections. In this study, we will discuss how die shifting and pattern distortion result in yield and throughput challenges for FOPLP. Then we will demonstrate outlier control technology with feedforward lithography on a test vehicle and how the integration of these two technologies addresses the challenges. We will also review the results of the demonstration and discuss the advantages of this strategy.

Development and Demonstration on Process-Oriented Warpage Simulation Methodology of Fan-Out Panel-Level Package in Multilevel Integration

Development and Demonstration on Process-Oriented Warpage Simulation Methodology of Fan-Out Panel-Level Package in Multilevel Integration

Double-sided numerical thermal modeling of fan-out panel-level MOSFET power modules

Double-sided packages for heat dissipation are an efficient thermal management mechanism for power semiconductor devices. A fan-out panel-level packaging (FOPLP), as one of the double-sided forms, exhibits excellent electro–thermal characteristics and provides low stray inductance and thermal resistance. Besides, the temperature at each point within the structure is closely related to its thermo–mechanical properties and device reliability. However, thermal resistance is limited in describing the temperature distribution. Finite element analysis (FEA) requires time-consuming construction of 3D models. Therefore, to depict the temperature distribution of FOPLP rapidly and accurately, a numerical heat transfer model was proposed for the double-sided package structure. The solution was obtained from the steady-state thermal balance Laplace equation using the separation of variables method. Several boundaries were analyzed to determine the specific parameters in the model. Finally, the temperature field predicted by the derived numerical model was compared with finite element simulation results. The proposed model was consistent with both Silicon (Si) and Silicon Carbide (SiC) FOPLP structures within the error of 15 % at the center of the device, which verified the validity and accuracy of the numerical model for double-sided heat dissipation. The proposed models and results could contribute to the development of effective thermal design tools for double-sided thermal power modules.

Multi-layer parallel transformer model for detecting product quality issues and locating anomalies based on multiple time‑series process data in Industry 4.0

Smart manufacturing systems typically consist of multiple machines with different processing durations. The continuous monitoring of these machines produces multiple time-series process data (MTPD), which have four characteristics: low data value density, diverse data dimensions, transmissible processing states, and complex coupling relationships. Using MTPD for product quality issue detection and rapid anomaly location can help dynamically adjust the control of smart manufacturing systems and improve manufacturing yield. This study proposes a multi-layer parallel transformer (MLPT) model for product quality issue detection and rapid anomaly location in Industry 4.0, based on proper modeling of the MTPD of smart manufacturing systems. The MLPT consists of multiple customized encoder models that correspond to the machines, each using a customized partition strategy to determine the token size. All encoders are integrated in parallel and output to the global multi-layer perceptron layer, which improves the accuracy of product quality issue detection and simultaneously locates anomalies (including key time steps and key sensor parameters) in smart manufacturing systems. An empirical study was conducted on a fan-out, panel-level package (FOPLP) production line. The experimental results show that the MLPT model can detect product quality issues more accurately than other methods. It can also rapidly realize anomalous locations in smart manufacturing systems.

(Invited) Improvements in Thermal Budget and Film Properties Using Low Pressure Cure Technology for Advanced 3D Integration Packaging

3D advanced integration with Fan-Out Wafer-Level Packaging (FOWLP) and Fan-Out Panel Level Packaging (FOPLP) offers multiple benefits: heterogenous chip design and stacking, increased interconnect density, and improved performance. However, it also brings new requirements for more compact form factors, low thermal budget materials and processing, and lower cost. The materials, process, and fabrication of heterogenous integration on redistribution layers (RDLs) consisting of metal and polymer dielectrics have become important enablers of the move to advanced packaging applications. To achieve the low-stress and low-cost benefits required by advanced integrated devices, thermal budgets must be reduced throughout the heterogenous integration flow -- including the dielectric curing step, which demands the use of low temperature processing and reduced cure times.In this presentation, the low temperature and low pressure thermal polymerization of dielectric polyimides used for redistribution layers (RDLs) is reviewed. Specifically, this presentation illustrates the significant impact of the low pressure cure process in reducing temperature (20° to 50° lower) and cure times (up to a 50% reduction) while providing better mechanical (elongation%, tensile strength, Young’s modulus), thermal (TG, Td 1%, Td 5%), and electrical (Dk, Df, dielectric breakdown strength - DBS) properties for different types of dielectric polyimides, including the Fujifilm LTC-9300 series, the Asahi BL-300 series, and the Toray LT-8300 and PW-1500 series. The post-curing polymerization ratio (FT-IR) and film stress were studied and are described. Finally, a proposed mechanism for the described dielectric polyimides’ polymerization under reduced pressure is discussed.Ongoing developments in design, materials, process and fabrication for FOWLP and FOPLP devices continue to drive progress in 3D heterogenous integration. This study of thermal processing of dielectric polyimides at low pressure and shorter time demonstrates a promising technique to improve overall process flow by reducing thermal budget, stress, and cost.

Inspection Solution for 2μm RDL from Wafer-Level to Panel-Level Fan-out Process

In the advanced packaging industry, both fan-out wafer-level packaging (FOWLP) and fan-out panel-level packaging (FOPLP) have grown quickly in recent years since they are compatible with largescale, low-cost manufacturing and are key enablers for ultra-thin and high-density packages. However, the commercialization of the fan-out process continues to face technical challenges with the rapid adoption of finer pitch and width of the Cu redistribution layer (RDL) in die-first or die-last integration approaches. AOI has been widely used in the advanced packaging industry as a major tool for defect inspection during various process steps. The conventional bright field and dark field imaging techniques suffer from a high nuisance rate for RDL inspection; in many cases, the RDL metal grain size could be larger than the defect of interest, and the interferences from underneath the pattern, such as bottom RDL layers or molding compounds, can increase the difficulties of defect detection. In this paper, we present Onto Innovation’s innovative fluorescence technology to enhance contrasts between organic material, such as polyimide, or photoresists and metals that enable fine-pitch RDL inspection with increased accuracy by eliminating nuisance defects. By using powerful fluorescence technology, in conjunction with higher resolution, high-definition inspection (HDI) technology, fine-pitch RDL defect inspections on both wafer-level and panel-level packaging were studied and shown to enable accelerated development cycles in the R&D stage, as well enable rapid yield enhancements in the HVM environment.

A Thin and Low-Inductance 1200 V SiC MOSFET Fan-Out Panel-Level Packaging With Thermal Cycling Reliability Evaluation

SiC MOSFET is mainly characterized by the higher electric breakdown field, higher thermal conductivity, and lower switching loss enabling high breakdown voltage, high-temperature operation, and high switching frequency. However, their performances are considerably limited by the high parasitic inductance and poor heat dissipation capabilities associated with existing wire-bonding packaging methods. To address this challenge, a 1200 V/136 A fan-out panel-level packaging (FOPLP) SiC MOSFET with a size of 8 <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">$\times$</tex-math> </inline-formula> <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">$\text{8}$</tex-math> </inline-formula> <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">$\times$</tex-math> </inline-formula> <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">$\text{0}.\text{75}$</tex-math> </inline-formula> mm was proposed. The electrical parameters of the devices were characterized experimentally. Both the static and dynamic parameters of the package matched the bare die values, which confirmed the functioning of the proposed packaging method for SiC MOSFET. The package parasitic inductance, thermal resistance, and soldering stress were analyzed through simulations. The reliability of the packages was evaluated by performing the thermal cycling test. The experimental results revealed that: 1) SiC MOSFET FOPLP had 0.36 nH drain–source parasitic inductance at 100 kHz, a 96% reduction compared with a conventional wire-bonded package; 2) double-sided cooling enabled the packages to exhibit a thermal resistance as low as 0.55 <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">$^{\circ}$</tex-math> </inline-formula> C/W; and 3) after 2000 thermal cycling cycles, drain–source ON-state resistance <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">$\textit{R}_{\text{DS\text{(}\text{on}\text{)}}}$</tex-math> </inline-formula> increased by less than 2%, which revealed the higher reliability of the package under thermal cycling.

Warpage Estimation and Demonstration of Panel-Level Fan-Out Packaging With Cu Pillars Applied on a Highly Integrated Architecture

Fan-out panel-level packaging (FO-PLP) has become a critical forward-looking technology because it can meet the demands for small size, high input/output counts, and multi-chip functions. Moreover, a three-dimensional stacked architecture called packaging-on-packaging can be achieved using the interconnects of Cu pillars. However, the serious warpage issue of FO-PLP during the manufacturing process causes many problems, such as assembly difficulty, low device reliability, and poor product yield. To address these problems, this study presents a process-oriented finite element analysis method to estimate the variation of the whole warpage resulting from the mismatch among the coefficients of thermal expansion of dissimilar materials during the fabrication procedures. Notably, the model construction of the complex redistribution layer in the proposed FO-PLP encounters a serious challenge when the simulated estimation is performed. Consequently, an equivalent mechanical characteristic extracted through simulation is adopted to redefine the material properties of RDL and Cu pillars separately. Moreover, modified Timoshenko bi-layered theory is employed with the process-oriented FEA of FO-PLP to clarify the stress-free temperature of the equivalent RDL. An actual FO-PLP vehicle with Cu pillars is fabricated and measured to demonstrate the reliability of the proposed simulation methodology. An average deviation of less than 10% is obtained between the simulated prediction and experiments. The results of factorial design indicate that the mechanical properties of dielectrics and RDL are the dominant factors and have an interactive effect on the warpage magnitude of FO-PLP.

Thermomechanical Oriented Reliability Enhancement of Si MOSFET Panel-Level Packaging Fusing Ant Colony Optimization With Backpropagation Neural Network

Considerable advancements in power semiconductor devices have resulted in such devices being increasingly adopted in applications of energy generation, conversion, and transmission. Hence, we proposed a Fan-Out Panel-Level Packaging (FOPLP) design for 30V Si based Metal Oxide Semiconductor Field Effect Transistor (MOSFET). To achieve superior reliability of the packaging, we applied the Nondominated Sorting Genetic Algorithm with elitist strategy (NSGA-II) and Ant Colony Optimization–Backpropagation Neural Network (ACO–BPNN) to optimize the design of redistribution layer (RDL) in FOPLP. We first quantified the thermal resistance and thermo-mechanical coupling stress of the designed package under thermal cycling loading. Next, NSGA-II and ACO–BPNN were used to optimize the size of the RDL blind via. Finally, the effectiveness of the proposed reliability optimization methods was verified by performing thermal shock reliability ageing tests on the prepared devices.

Multiscale warpage behaviour in a Fan-Out Panel during thermal cycles

In this work, the warpage of a panel in the context of fan-out packaging is analysed. On a panel size of 300 × 300 mm2 a die layout is molded and debonded from the temporary carrier. The resulting warpage is characterised temperature dependent using the Projection Moiré technique globally across the complete panel and locally on the scale of few dies. Globally, results are analysed with respect to the shape change of the warpage and residual warpage after thermal cycling. Locally the curvature of single dies is compared to the global curvature of the tunnel shaped warpage. This work is part of the investigations with the aim to describe and control the warpage effects in Fan-Out Panel Level Packaging.

Comparison of Mechanical Modeling to Warpage Estimation of RDL-First Fan-Out Panel-Level Packaging

To meet the requirements of low cost, thin vehicles, and multiple functions, the fan-out panel-level packaging (FO-PLP) is introduced to be one of the next-generation packaging technologies. However, the warpage issue of FO-PLP remains a critical concern during temperature cycling manufacturing processes. The utilization of finite-element analysis (FEA) to estimate the warpage of FO-PLP and to address the major mechanism of warp-induced failure is therefore crucial. Given that an increase in the structural complexity of packaging follows the advancement in technological development, the effect of redistribution layer (RDL) on packaging warp considered in FEA becomes greatly difficult. The complicated RDL might cause computational bottlenecks. For this reason, several equivalent material approaches composed of composite theory and simulation-based material testing approach are proposed and compared with resolve the abovementioned problem. The gravity effect is considered in the present process-oriented FEA to acquire accurate warpage. To perform the foregoing FEA, identifying how to determine the equivalent reference temperature at each step of manufacturing process is the key. In this article, three methods, namely, zero deformation approach, force equilibrium approach, and modified Timoshenko bimaterial approach, are proposed. To validate these methods, a comparison of warpage between the experimental measurement and simulation is conducted. The analytic results demonstrate that the modified Timoshenko approach has the best ability to evaluate the warpage of RDL-first FO-PLP among them due to the feasible assumption for the actual mechanical behavior of warpage. With regard to the extraction of equivalent material, the results indicate that the simulation-based material testing approach is more suitable to obtain the equivalent RDL. The estimated warpage has only a 0.9% deviation between the simulation and experiment when the modified Timoshenko bimaterial approach combined with the simulation-based material testing approach is adopted. Consequently, the RDL-induced warpage in FO-PLP can be accurately estimated through the presented simulation methodology.

A Quantitative Model to Understand the Effect of Gravity on the Warpage of Fan-Out Panel-Level Packaging

In this article, a universal and concise theoretical model is proposed to quantify the effect of gravity on packaging warpage by considering the competition between the thermal and chemical shrinkage of packaging materials and the flexural stiffness of packaging structures. Experimental study and finite element simulation for the warpage distributions of two fan-out panel-level packaging structures with sizes of 310 mm <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">$\times320$ </tex-math></inline-formula> mm are carried out to verify the effectiveness of the proposed model. Under the ideal gravity-free condition, the warpage is proportional to the square of the packaging structure size. Under the gravity effect, the warpage follows a brief quartic expression of the packaging structure size. The gravity can reduce the bending moment in the structure and thereby lead to the decrease of the total warpage. For larger-size structures, the effect of gravity on warpage is more pronounced. It is found that the predictions by the model fit well with both experimental and simulation results. The theoretical model in our work can provide an effective tool to predict the warpage with consideration of the gravity effect and will promote further development and design of large-scale packaging structures.

(Invited) Fan-out and Cu- Compatible Dielectric Processing of Low Temperature Polyimides for Next-Generation 3D Advanced IC Back End Applications

Fan-out (FO) wafer and panel level processing in advanced backend applications requires the curing of RDL (Redistribution Layers) or interconnect dielectrics at lower temperatures in order to manage stress and relevant warpage for multi-level or 3D processing. In addition, the need to transition to all-Cu interconnect has resulted in a temperature limit of 230°C for large numbers of end products. Most of these products employ the advanced packaging capabilities of heterogeneous and 3D integration, 3D stacking and system-in-package (SIP) technology, whereby a variety of chiplets and other components are stacked, delivering high compute density and high performance at low cost. Multi-layer RDLs are used to connect these dissimilar chips on organic, glass, silicon or fan-out substrates. Consequently, process technology for polyimide, photo imageable dielectric (PID) and photo sensitive polyimide (PSPI) must now enable a faster cure at lower temperatures to achieve lower stress, while also delivering better film properties.In this talk, the physical, mechanical, thermal, and electrical properties of different types of polyimide materials will be discussed as a function of different process parameters, under atmospheric and vacuum process conditions. The talk references a study in which a variety of low temperature RDL polyimides such as HD-7110, Asahi BL-301 and Fuji-LTC9320 were processed at a temperature of less than 230°C, and then compared to conventional polyimide HD-4100. Vacuum cure even at lower temperatures resulted in higher thermal stability, lower outgassing, and better thermal properties. In electrical characterization, vacuum cure showed better dielectric strength as well as a lower dissipation factor. These results are consistent with the assumption that cure under vacuum reduces the amount of volatile and volatilizable material remaining in the film after the cure process.The use of sub-atmospheric curing or annealing technology at low temperature improved both the quality and the performance of the cured polyimide films for RDL applications. These results are relevant to the multi-level metallization process of Fan Out Wafer Level Packaging (FOWLP) and Fan Out Panel Level Packaging (FOPLP), and therefore to 3D stack integration.

A Transformer using two RDL metal layers based on Fan-Out Panel Level Package Technology

Under the background that electronic products have been developing in the direction of being smaller, lighter and cheaper, the packaging of chip components has also been continuously improved. Fan-out panel-level package (FOPLP) is one of the latest development trends in microelectronics package, which can achieve higher productivity and lower costs. A planar toroidal spiral transformer is designed based on Fan-Out Panel Level Package technology. The transformer is constructed by two RDL layers provided by the packaging process. The size of the proposed transformer is 434um×434um. The simulated primary and secondary inductance is 2.5nH and 2.5nH respectively. The coupling factor of the transformer is 0.845. The quality factor of the transformer is higher than 800 during the entire working frequency range. The self-resonant frequency of the present transformer is 20 GHz. Compared to the on-chip counterpart, the transformer designed based on Fan-Out Panel Level Package technology can achieve higher coupling factor and quality factor. Therefore, the proposed transformer can save chip size and reduce the cost through avoiding using area hungry passive on chip transformer.

Fan-Out Panel-Level Packaging of Mini-LED RGB Display

In this study, the feasibility of mini-light-emitting diode (LED) RGB display fabricated by a chip-first fan-out panel-level packaging is investigated. Emphasis is placed on the design, materials, process, fabrication, and reliability of the mini-LED RGB display package on a printed circuit board (PCB). The mini-LEDs under consideration and their sizes are red ( 125 ×250 ×100 μm), green ( 130 ×270 ×100 μm), and blue ( 130 ×270 ×100 μm). The spacing among the RGB mini-LEDs is 80 μm, the pixel-to-pixel spacing is also ~ 80 μm, and the pixel pitch is 625 μm. The temporary glass panel for making the redistribution layers (RDLs) of the package is 515 ×510 ×1.1 mm in size. To increase the SMT assembly yield on the PCB, the mini-LEDs are grouped into 4( 2 ×2 pixels)-in-one surface mount device (SMD), that is, a total of 12 R, B, and G mini-LEDs. A PCB ( 132 mm ×77 mm) is designed and fabricated for the drop test of the mini-LED package. Thermal cycling of the mini-LED SMD PCB assembly is also performed by a nonlinear temperature- and time-dependent finite-element simulation.

Wafer Level Packaging Technology Applied to Pixel Detectors

Pixel technology is commonly used in the tracking systems of High Energy Physics detectors with physical areas that have largely increased in the last decades. To ease the production of several square meters of sensitive area, the possibility of using the industrial Wafer Level Packaging to reassemble good single sensor tiles from multiple wafers into a reconstructed full wafer is investigated. This process reconstructs wafers by compression molding using silicon charged epoxy resin. We tested high glass transition temperature low-stress epoxy resins filled with silica particles to best match the thermal expansion of the silicon die. These resins are developed and characterized for industrial processes, designed specifically for fan-out wafer-level package and panel-level packaging. In order to be compatible with wafer processing during the hybridization of the pixel detectors, such as the bump-bonding, the reconstructed wafer must respect challenging technical requirements. Wafer planarity, tile positioning accuracy, and overall thickness are amongst the main ones. In this paper the description of the process is given and preliminary results on a few reconstructed wafers using dummy tiles are reported. Strategies for Wafer Level Packaging improvements are discussed together with future applications to 3D sensors or CMOS pixel detectors.

Chip-Last (RDL-First) Fan-Out Panel-Level Packaging (FOPLP) for Heterogeneous Integration

Abstract In this investigation, the chip-last, RDL (redistribution-layer)-first, fan-out panel-level packaging (FOPLP) for heterogeneous integration is studied. Emphasis is placed on the materials, process, fabrication, and reliability of a heterogeneous integration of one large chip (10mm × 10mm) and two small chips (7mm × 5mm) by a FOPLP method on a 20mm × 20mm RDL-first substrate fabricated on a 515mm × 510mm temporary glass panel. Reliability test such as the drop test of the heterogeneous integration package on a PCB (printed circuit board) is performed and test results including failure analysis are presented. Some recommendations are also provided.

Investigation of Pillar–Concave Structure for Low-Temperature Cu–Cu Direct Bonding in 3-D/2.5-D Heterogeneous Integration

With the advantage of high surface-roughness tolerance, the pillar-concave Cu-Cu direct bonding without chemical-mechanical planarization (CMP) is investigated in detail, including the mechanism of thermal compensation, analysis of roughness, bonding strength, and bonding reliability. With the special design of Cu bond structure, excellent bonding results can be achieved under low thermal budget (150 °C for 1 min, atmosphere) with even high roughness of bonding surface. In addition, the pillar-concave scheme applied to fan-out panel-level package (FOPLP) has been demonstrated, showing the high feasibility of this scheme to realize applications in heterogeneous integration.

Chip-Last (RDL-First) Fan-Out Panel-Level Packaging (FOPLP) for Heterogeneous Integration

Abstract In this investigation, the chip-last, redistribution-layer (RDL)–first, fan-out panel-level packaging (FOPLP) for heterogeneous integration is studied. Emphasis is placed on the materials, process, fabrication, and reliability of a heterogeneous integration of one large chip (10 × 10 mm2) and two small chips (7 × 5 mm2) by an FOPLP method on a 20 × 20-mm2 RDL-first substrate fabricated on a 515 × 510 mm2 temporary glass panel. Reliability test such as the drop test of the heterogeneous integration package on a printed circuit board (PCB) is performed, and test results including failure analysis are presented. Some recommendations are also provided.