Process Sequence For Fabrication Research Articles

Impact of ion implantation and annealing parameters on bifacial PERC and PERT solar cell performance

Passivated Emitter and Rear Contact (PERC) and Passivated Emitter Rear Totally Diffused (PERT) solar cell designs are now a market reality. In the production of these cells, ion implantation is another method for creating emitters and back surface field (BSF) regions, since it can facilitate the process flow and precise doping control. Here, Technology Computer Aided Design (TCAD) is utilized to assess the effects of ion implantation fluences, annealing temperature, and duration, on the performance of bifacial PERC solar cells. To ensure realistic simulation results, the solar cell model is developed using experimentally demonstrated bifacial counterparts. The process simulation models are also calibrated to match experimentally obtained doping profiles. Simulation results show that by replacing emitter diffusion with phosphorus ion implantation, both the front/rear efficiencies can be improved by 0.07%. The rear boron implantation is also optimized to provide an effective BSF, improving the front/rear efficiencies by 0.21/0.15%, respectively. Moreover, co-annealing of emitter and BSF regions exhibits a 0.2% increase in efficiency than separately annealed PERT cells. Hence an overall improvement of 0.48/0.42% is achieved in the front/rear efficiencies when compared to the original diffused emitter PERC design. The fabrication process sequence is also suggested for these solar cells.

High‐performance P(VDF‐TrFE)/BaTiO3 nanocomposite based ferroelectric field effect transistor (FeFET) for memory and switching applications

AbstractThe ferroelectric field effect transistor (FeFET) using Poly (vinylidene fluoride‐trifluoroethylene)/Barium titanate [P(VDF‐TrFE)/BaTiO3] polymer nanocomposite as dielectric layer, has been fabricated and characterized. P(VDF‐TrFE)/BaTiO3 nanocomposite of 300 nm thin film over 10 nm SiO2 was used in the optimized fabrication process sequence of FeFET. The addition of BaTiO3 nanoparticle to the P(VDF‐TrFE) copolymer has enhanced the ferroelectric property with an observed 2 V difference in memory window. The effect of temperature and frequency on these memory window characteristics were observed to optimized the stack thickness for an ideal FeCAP (ferroelectric capacitor). Drain current–drain voltage (ID‐VD) characteristics of P(VDF‐TrFE)/BaTiO3 FeFET shows significant variation in ID with pinch of voltage around 1 V for wide range of gate voltage (VG). ION/IOFF ratio of FeFET using P(VDF‐TrFE)/BaTiO3 was found to be 35, which was higher than the ratio of FeFET fabricated using P(VDF‐TrFE) copolymer (4.4). ID‐VG characteristics of both the FETs clearly indicate a lower threshold voltage (0.83 V) for P(VDF‐TrFE)/BaTiO3 FET, which is almost three times lesser than threshold voltage of a P(VDF‐TrFE) FET (2.5 V).

Exploration of Inter-Die Bulk Fin-Typed Field Effect Transistor Process Variation for Reduction of Device Variability.

This work first reports a novel exploration technique to systematically prioritize key fabrication in-line process parameters of 16-nm high-k metal gate (HKMG) bulk FinFET to reduce device's die-to-die variation. To extract hidden correlations and reduce decision variables among the complex in-line process parameters, a data mining technique is employed to highlight and group associated parameters. To correlate the measured data with the distribution of physical dimension of devices for all in-line processes, a sensitivity analysis is then performed. Because the variability of current process deeply affects the next process, so the sequence of fabrication process is further added into the analyzing procedure to increase the searching efficiency. The source of variation of the initial process can be monitored and traced by the proposed methodology. The result of this study indicates that the gate spacer is a key process factor and will determine the uniformity of process including, such as the source-and-drain proximity, and the depth, lateral offset and overlap of sequential doping implants. The ranked key in-line process parameters can be used to optimize process and minimize the device variability of 16-nm HKMG bulk FinFET devices.

Fabrication of electron beam physical vapor deposited polysilicon piezoresistive MEMS pressure sensor

MEMS pressure sensor fabrication introduce a number of challenges to handle the processed wafers in batch fabrication after bulk-micromachining. In this paper, fabrication process sequence was optimized where photolithography steps were reduced after the diaphragm formation. Reactive ion etching (RIE) and low pressure chemical vapor deposition (LPCVD) has been replaced during the modified process. Polysilicon thin film based on electron beam physical vapor deposition (EBPVD) was optimized for required sheet resistivity. MEMS pressure sensor rooted on EBPVD polysilicon piezoresistive sensing element was successfully fabricated and characterized in terms of sensitivity, linearity and repeatability.

Planarized ambipolar a-SiGe:H thin-film transistors: Influence of the sequence of fabrication process

This work presents the fabrication, characterization and modeling of inverted staggered a-SiGe:H TFTs with planarized gate electrode. Using this structure two different sequences of fabrication are presented, where spin-on glass and silicon nitride are used as passivation layer, respectively. The results show ambipolar and unipolar behavior in the a-SiGe:H TFTs depending on the fabrication sequence. Also, trap density and characteristic energies for the deep localized states in the a-SiGe:H film are obtained. Using these parameters the device modeling is presented.

3D-feature-based structure design for silicon fabrication of micro devices

To make MEMS structure design in a more intuitive way, and to support the “function to 3D shape to mask” design flow, a 3D feature based structure design framework and its corresponding key enabling techniques are presented on the basis of inverse design processes and top-down design methodologies. Driven by space mapping among function and structure, the feature model and its parameters are restricted with the bond graph represented simulation model, which is constructed with functional components in simulation library at the system-level. Conforming design rules, the hierarchic feature information model is established and finally can be cascaded down to a group of 3D feature nodes, which are all silicon fabrication oriented and defined on the top of CSG/B-rep 3D solid models. Surrounding this feature information model, the 2D mask deducing and fabrication parameters extraction at the fabrication-level can be performed for manufacturability checking, design/fabrication conflict feedback and fabrication process sequence generation. Taking a micro gap-closing actuator as an example, the structure design process is demonstrated in terms of this 3D feature modeling methodology.

DC- and IF-noise performance optimization of GaAs Schottky diodes for THz applications

This paper presents results which originated from a long-term systematic optimization of surface processing prior to anode formation of THz Schottky-based components. Particularly, four most promising surface-processing approaches are carefully investigated separately and in combination in order to understand the chemical and physical processes occurring on a GaAs surface. A reliable technological approach for anode formation is identified, which exhibits optimal diode characteristics and production repeatability. A model is proposed for the influence of each process on the subsequent one in the fabrication process sequence. DC- and IF-noise measurements are performed using an automated measurement system providing statistically significant data. Very good dc-parameters such as a series resistance of Rs = 15 Ω, an ideality factor N = 1.168, a reverse current Is = 0.024 fA and an IF-noise temperature of 257 K at 1 mA current bias with a good uniformity are achieved for non-cooled Schottky diodes with an anode diameter of 1 µm. The best noise figure is measured to be as low as 220 K at 3.8 GHz and 1 mA current bias.

A complementary-metal-oxide-semiconductor-field-effect-transistor-compatible atomic force microscopy tip fabrication process and integrated atomic force microscopy cantilevers fabricated with this process

A complementary-metal-oxide-semiconductor-field-effect-transistor-compatible process for the fabrication of atomic force microscopy cantilevers with integrated tips has been developed. For the first time, the tips are fabricated after the completion of the regular complementary metal-oxide-semiconductor-field-effect-transistor fabrication process sequence. On-chip circuit components, such as piezoresistive deflection sensors, deflection actuators, and amplifiers, are fabricated on the mirror-polished surface of the wafer, ensuring optimal performance. The tip fabrication process is based on anisotropic silicon etching at low temperature using a tetramethylammonium hydroxide solution. The anisotropic etching process has been optimized to ensure process controllability. Using the described process, complementary-metal-oxide-semiconductor-field-effect-transistor-based cantilevers with piezoresistive deflection sensors and integrated tips have been successfully fabricated. Force–distance curves and scanning images in constant-force mode have been recorded.

Characterization of Low Temperature Polysilicon TFTs with Self-Aligned Graded LDD Structure

AbstractA simple process sequence for fabrication of low temperature polysilicon (LTPS) TFTs with self-aligned graded LDD structure was demonstrated. The graded LDD structure was self-aligned by side-etch of Al under the photo-resist followed by excimer laser irradiation for dopant activation and laterally diffusion. The graded LDD polysilicon TFTs were suitable for high-speed operation and active matrix switches applications because they possessed low-leakage-current characteristic without sacrificing driving capability significantly and increasing overlap capacitance. The leakage current of graded LDD polysilicon TFTs at Vd = 5V and Vg = −10V could attain to below 1pA/μm without any hygrogenation process, when proper LDD length and laser activation process were applied. The on/off current ratios of these devices were also above 108. Furthermore, due to graded dopant distribution in LDD regions, the drain electric field could be reduced further, and as a result, graded LDD polysilicon TFTs provided high reliability for high voltage operation.

Low-voltage organic transistors on plastic comprising high-dielectric constant gate insulators

The gate bias dependence of the field-effect mobility in pentacene-based insulated gate field-effect transistors (IGFETs) was interpreted on the basis of the interaction of charge carriers with localized trap levels in the band gap. This understanding was used to design and fabricate IGFETs with mobility of more than 0.3 square centimeter per volt per second and current modulation of 10(5), with the use of amorphous metal oxide gate insulators. These values were obtained at operating voltage ranges as low as 5 volts, which are much smaller than previously reported results. An all-room-temperature fabrication process sequence was used, which enabled the demonstration of high-performance organic IGFETs on transparent plastic substrates, at low operating voltages for organic devices.

A Composite Two-Dimensional Process/Device Simulation System (TOPMODE) and its Application for Total Process Designing in Submicron VLSI MOS Device Phase

A new composite two-dimensional process/two-dimensional device simulation system (TOPMODE) (FOOTNOTE: Standing for TOshiba Simulation Program for MOS DEvice.) has been developed to provide a straightforward means of predicting small-geometry device characteristics using the fabrication process sequence. Using TOP-MODE, an analysis of the anomalous subthreshold drain current peculiar to buried oxide isolation (BOX) structure device has been conducted and the physical mechanism is attributed to the impurity profile and other geometry effects. Input to TOPMODE is specially designed using key words language as a user-oriented CAD tool. Plotting functions for multidimensional perspective drawing of output results have also been installed to provide a better visual aid.