Fabrication Of Single-electron Transistors Research Articles

A Novel Fabrication of Single Electron Transistor from Patterned Gold Nanoparticle Array Template-Prepared by Polystyrene Nanospheres.

In this paper, polystyrene microspheres were firstly prepared by seeded emulsion polymerization, and the uniform monolayer of polystyrene microspheres was prepared on the substrate by the dipping method. Then, polystyrene monolayer film was used as a mask and a low dimensional array structure of gold was prepared by bottom-up self-assembly process. After that, the method of solution etching and annealing was used, and the gold nanoparticle array was post-processed. As a result, gold nanoparticles were recrystallized, with an average diameter of about 50 nm. Subsequently, the semiconductor process was adopted, with focused ion beams induced deposition and electron beam evaporation, and single electron transistors were fabricated, based on self-assembled gold nanoparticles. Finally, the devices were fixed in a liquid helium cryostat and Coulomb blockade was observed at 320 mK. It is a novel fabrication of a single electron transistor based on gold nanoparticle array template and prepared with polystyrene nanospheres.

Fabrication of single-electron transistors with electromigrated Ni nanogaps

We analyze single-electron transistors (SETs) fabricated with electromigrated Ni nanogaps using the Korotkov and Nazarov (KN) model. First, we investigate nanogap-based SETs consisting of multiple Ni islands placed between the source and drain electrodes by a field-emission-induced electromigration technique known as “activation.” After the activation procedure is performed using a preset current Is of 3 μA, the drain current-drain voltage characteristics of SETs with single-island structures are obtained and analyzed by using the KN model and considering the offset charges on the islands. We determine the fitting parameters obtained by the KN model from the electrical properties of the SETs. The parameters can be explained using the geometrical structures of the SETs that are observed in both scanning electron and atomic force microscopy images after the activation procedure. This approach allows the electrical and structural properties of the single-island structures of the SETs fabricated using the activation method to be determined.

Single-electron transistor with an island formed by several dopant phosphorus atoms

We present the results of an experimental study of electron transport through individual phosphorus dopants implanted into a silicon crystal. We developed an original technique for single-electron transistor fabrication from silicon-on-insulator material with an island formed by single phosphorus atoms. The proposed method is based on well-known CMOS compatible technological processes that are standard in semiconductor electronics and may be used in most research groups. The large Coulomb blockade energy value of the investigated single-electron transistor (∼20 meV) allows one to observe single-electron effects in a wide temperature range up to 77 K. We measured and analyzed stability diagrams of fabricated experimental structures. We demonstrated a single-electron transistor with controllable electron transport through two to three phosphorus dopants only.

Atomic layer deposition of Al2O3 for single electron transistors utilizing Pt oxidation and reduction

This work describes the fabrication of single electron transistors using electron beam lithography and atomic layer deposition to form nanoscale tunnel transparent junctions of alumina (Al2O3) on platinum nanowires using either water or ozone as the oxygen precursor and trimethylaluminum as the aluminum precursor. Using room temperature, low frequency conductance measurements between the source and drain, it was found that devices fabricated using water had higher conductance than devices fabricated with ozone. Subsequent annealing caused both water- and ozone-based devices to increase in conductance by more than 2 orders of magnitude. Furthermore, comparison of devices at low temperatures (∼4 K) showed that annealed devices displayed much closer to the ideal behavior (i.e., constant differential conductance) outside of the Coulomb blockade region and that untreated devices showed nonlinear behavior outside of the Coulomb blockade region (i.e., an increase in differential conductance with source-drain voltage bias). Transmission electron microscopy cross-sectional images showed that annealing did not significantly change device geometry, but energy dispersive x-ray spectroscopy showed an unusually large amount of oxygen in the bottom platinum layer. This suggests that the atomic layer deposition process results in the formation of a thin platinum surface oxide, which either decomposes or is reduced during the anneal step, resulting in a tunnel barrier without the in-series native oxide contribution. Furthermore, the difference between ozone- and water-based devices suggests that ozone promotes atomic layer deposition nucleation by oxidizing the surface but that water relies on physisorption of the precursors. To test this theory, devices were exposed to forming gas at room temperature, which also reduces platinum oxide, and a decrease in resistance was observed, as expected.

Fabrication and Characterization of a Single Electron Transistor Based on a Silicon-on-Insulator**Supported by the National Natural Science Foundation of China under Grant Nos 11074280 and 11403084, the Instrument Developing Project of Chinese Academy of Sciences under Grant No YZ201152, the Fundamental Research Funds for Central Universities under Grant Nos JUSRP51323B and JUDCF12032, the Joint Innovation Project of Jiangsu Province under

A single electron transistor based on a silicon-on-insulator is successfully fabricated with electron-beam nanolithography, inductively coupled plasma etching, thermal oxidation and other techniques. The unique design of the pattern inversion is used, and the pattern is transferred to be negative in the electron-beam lithography step. The oxidation process is used to form the silicon oxide tunneling barriers, and to further reduce the effective size of the quantum dot. Combinations of these methods offer advantages of good size controllability and accuracy, high reproducibility, low cost, large-area contacts, allowing batch fabrication of single electron transistors and good integration with a radio-frequency tank circuit. The fabricated single electron transistor with a quantum dot about 50nm in diameter is demonstrated to operate at temperatures up to 70 K. The charging energy of the Coulomb island is about 12.5 meV.

In situ electrical characterization of palladium-based single electron transistors made by electromigration technique

We report the fabrication of single electron transistors (SETs) by feedback-controlled electromigration of palladium and palladium-nickel alloy nanowires. We have optimized a gradual electromigration process for obtaining devices consisting of three terminals (source, drain and gate electrodes), which are capacitively coupled to a metallic cluster of nanometric dimensions. This metal nanocluster forms into the inter-electrode channel during the electromigration process and constitutes the active element of each device, acting as a quantum dot that rules the electron flow between source and drain electrodes. The charge transport of the as-fabricated devices shows Coulomb blockade characteristics and the source to drain conductance can be modulated by electrostatic gating. We have thus achieved the fabrication and in situ measurement of palladium-based SETs inside a liquid helium cryostat chamber.

Sub-10 nm nano-gap device for single-cluster transport measurements

We present a versatile procedure for the fabrication of single electron transistor (SET) devices with nanometer-sized clusters and embedded back gate electrode. The process uses sputtering gas-aggregation for the growth of clusters and e-beam lithography with double angle shadow-edge deposition to obtain electrodes separated by nano-gaps with width below 10 nm. The nano-gap width is easily controlled only by geometrical factors such as deposited thin film thickness and evaporation angles. The usefulness of this technique is demonstrated by measuring the SET behavior of a device with a 4 nm cobalt cluster embedded in alumina, where the Coulomb blockade and incremental cluster charging can be readily identified without resorting to the differential conductivity.

Fabrication of single electron transistors using transfer-printed aligned single walled carbon nanotubes arrays

A technique has been developed to transfer the aligned single-walled carbon nanotubes (SWCNTs) grown on a single-crystal quarz substrate to a SiO2/Si substrate. Aligned single electron transistors (SETs) have been fabricated with the transferred SWCNTs, and the low-temperature transport measurements have been carried out at 1.5 K. Several SETs fabricated in this approach exhibited regular Coulomb oscillations and closed Coulomb diamonds, which indicate the single quantum dot behavior. This suggests that the mechanical transfer technique does not produce serious damage to the SETs and would be useful for future integrated SET devices and circuits.

Fabrication of an array of single-electron transistors for a scanning probe microscopesensor

A technique for the fabrication of single-electron transistors (SETs) on tips for use inscanning probe microscopy is presented. The tips are micromachined out of anMBE-grown AlGaAs–GaAs heterostructure with a trench within each tip. The SETs areproduced by aluminum evaporation and oxidation, and natural shadowing by thetrench is used to separate the source and drain electrodes. By separating adjacenttips also by trenches, the concept allows the fabrication of tip arrays for parallelprobing.

Controlled fabrication of single electron transistors from single-walled carbon nanotubes

Single electron transistors (SETs) are fabricated by placing single-walled carbon nanotubes (SWNTs) on a 100nm wide local Al∕Al2O3 bottom gate and then contacting with Pd electrodes. Coulomb oscillations up to 125K were observed and charging energies of 12–15meV with level spacing of ∼5meV were measured from the Coulomb diamond, in agreement with a dot size of ∼100nm, implying that the local gate defines the dot size by bending SWNT at the edges and controls its operation. This “mechanical template” approach may facilitate large scale fabrication of SET devices using SWNT.

A mean field approach to Coulomb blockade for a disordered assembly of quantum dots

The Coulomb blockade (CB) in quantum dots (QDs) is by now well documented. It has been used to guide the fabrication of single electron transistors. Even the most sophisticated techniques for synthesizing QDs (e.g. MOCVD/MBE) result in an assembly in which a certain amount of disorder is inevitable. On the other hand, theoretical approaches to CB limit themselves to an analysis of a single QD. In the present work we consider two types of disorders: (i) size disorder; e.g. QDs have a distribution of sizes which could be unimodal or bimodal in nature. (ii) Potential disorder with the confining potential assuming a variety of shapes depending on growth condition and external fields. We assume a Gaussian distribution in disorder in both size and potential and employ a simplified mean field theory. To do this we rely on the scaling laws for the CB (also termed as Hubbard U) obtained for an isolated QD [1]. We analyze the distribution in the Hubbard U as a consequence of disorder and observe that Coulomb blockade is partially suppressed by the disorder. Further, the distribution in U is a skewed Gaussian with enhanced broadening.

Fabrication and characterization of Si quantum dots andSiO2 tunnel barriers grown by a controlled oxidation process

The control of the growth of silicon dioxide(SiO2) and the formation of quantum dots (QDs) play an important role in the fabrication ofsingle-electron transistors (SETs). In this work, SET structures were fabricated using asystematic oxidation technique known as the pattern-dependent oxidation (PADOX) process.For comparison, two oxidation processes using conventional furnace and rapid thermal processing(RTP) were used. The oxidation temperature for both oxidation processes was set at1000 °C and the oxygen flow rate in the furnace was set at1 l min−1. The nanostructures were characterized using AFM, SEM and TEM to determine the qualityand the stoichiometry of the Si QDs and the oxides. The oxidation rate using a furnace is0.36 nm s−1, significantly lower than the RTP value which is2.16 nm s−1. Meanwhile, theoxygen contents in SiO2 grown by furnace and RTP are approximately the same.

Nano patterning of cone dots and nano constrictions of negative e-beam resist for single electron transistor fabrication

We present an optimization of nano dot of negative tone e-beam resist which is a very important step in single electron transistor fabrication process. The optimum design of dot and nano constriction plays a significant role in determining optimum etching resolution and single electron transistor performance. In this research, we have optimized nano dot and nano constriction dimensions of resist by controlling some parameters, such as e-beam dose, spin speed, pre-bake time and image development time. However, a nano constriction design variety of 120–200 nm in width was carried out to reach the optimum design. In this paper, the fabrication process of cone nano dots using e-beam lithography with considering proximity effect is reported. As nano constriction design decreased, cone nano dot changed to pyramid nano dot and the compression effect on the dot also significantly increased as well.

Fabrication and characterization of single electron transistor on SOI

A novel technique, based on electron-beam lithography (EBL) and anisotropic reactive ion etch (RIE), was developed in this work for the fabrications of single electron transistors with ultra small junctions in silicon on insulator (SOI). Junction size as small as 10 nm has been achieved. Initial characterisation at low temperature has demonstrated clear Coulomb blockade gap in the measured I– V curves, indicating that such narrow junctions in silicon finally formed by RIE are still functional. This process eases the difficulty in EBL for 10 nm feature size by the controllable lateral dry-etch on the sidewall of the silicon thin layer, opening up a prospect for routine manufacture of single electronic devices and circuits on SOI, which possesses broad applications in meteorological measurement and IT technology.

A route to fabricate nanocontacts by X-ray lithography for the realization of single electron transistors and highly sensitive biosensors

The fabrication of single electron transistors and/or highly sensitive biosensors is still a challenging task on account of the tight control required to get proper shapes and size of the electrodes. The nanosized tips and the separation of a few nanometers between electrode pairs are critical features. Conventional lithography is not suited to obtain these features because of the resolution limits, so that previous alternative approaches have involved the use of electron beam lithography, focused ion beam lithography or scanning probe nanolithography. The novel approach presented in this letter is the exploitation of X-ray lithography in the Elettra synchrotron to fabricate arrays of nanocontacts spaced a few nanometers, devoted to the design of a new class of nanodevices based on nanoparticles and/or single molecules, including single electron transistors and highly sensitive biosensors. The method to fabricate such devices is illustrated and discussed. Experimental details of the fabrication process are given and preliminary results are presented through SEM and AFM images. It is worth noting that this paper presents a viable method to produce nanocontacts by using the X-ray lithography by synchrotron radiation source, that has not yet been reported together with experimental, though preliminary, data.

Proximity effect of electron beam lithography for single-electron transistor fabrication

In this letter, we shall describe a method, utilizing the proximity effect in electron beam lithography, suitable for fabricating silicon dots and devices, and demonstrate the electronic characteristics of the Si single-electron transistor. The drain current (Id) of the device oscillates against gate voltage. The electrical characteristics of the single-electron transistor were observed to be consistent with the expected behavior of electron transport through gated quantum dots, at up to 150K. The dependence of the electrical characteristics on the dot size reveals that the Id oscillation follows from the Coulomb blockade by poly-Si grains in the poly-Si dot. The method of fabrication of this device is completely compatible with complementary metal–oxide–semiconductor technology, raising the possibility of manufacturing large-scale integrated nanoelectronic systems.

Properties of evaporated titanium thin films and their possible application in single electron devices

The influence of the deposition rate of titanium thin films on their microscopic structure has been investigated by transmission electron microscopy, X-ray diffraction analyses and atomic force microscopy. Furthermore, the resistivity of the films has been characterized by van der Pauw measurements in a temperature range of 5–300 K. Titanium films with a thickness of 10 nm evaporated with a rate of 1 Å/s showed the typical and well known temperature dependency of the resistivity (i.e. decreasing resistivity with falling temperature). In contrast, the resistivity of thin films deposited with a rate of 0.2 Å/s rises with decreasing temperature. Additionally, the resistivity of the films evaporated with the lower rate rises significantly when reducing their film thickness down to 3 nm. Due to this increase of the resistivity we are able to present an alternative and relatively simple approach for the fabrication of single electron transistors (SETs). The presented SET design is based on the evaporated thin titanium films with a deposition rate of 0.2 Å/s onto well defined trenches previously etched into a dielectric layer of thermally grown silicon dioxide. The tunnel junctions originate from a local increase of the resistance of the metallic wire at the edges of the trenches. The devices fabricated in this manner with lateral dimensions in the 50–100 nm range show clear SET features at an operating temperature of up to 77 K. Additionally, the influence of background charges on the Coulomb oscillations in this devices are demonstrated and discussed in comparison with simulated data.

Fabrication of single electron transistors in multi-wall carbon nanotubes using Ar beam irradiation

The Ar beam with an acceleration voltage of 300 V has been irradiated to multi-wall carbon nanotubes (MWNTs) through a narrow opening of the resist, in order to form a tunnel barrier. The tunnel resistance could be set by appropriate dose, in the range greater than h/ e 2, and single electron transistors (SETs) have been fabricated with two tunnel barriers in series. Electrical transport measurements have been carried out at 2.6 K. Most of the samples have shown periodic Coulomb diamonds, suggesting the formation of a single quantum dot with a maximum Coulomb gap ranging from 5 to 26 meV. In a few samples, there was still a finite Coulomb gap at the gate voltages where two adjacent diamonds meet, suggesting an unexpected multi-barrier formation. The present technique may be useful for the fabrication of more complicated quantum dot-based nanodevices in carbon nanotubes.

Fabrication of single-electron transistors and circuits using SOIs

The paper describes the fabrication of single-electron transistors and circuits using silicon-on-insulators (SOIs). We first point out that control of the oxidation of Si is quite important and could be the key to the fabrication of quantum devices including single-electron devices. We then introduce our technique for making single-electron transistors, which uses special phenomena that occur during the oxidation of SOIs, and show that the technique enables us to realize primary single-electron circuits as a result of its high controllability, reproducibility and thermal stability.