Silicon Wafer Fabrication Research Articles

Sidewall Modification Process for Trench Silicon Power Devices

In this study, trench sidewall modification processes were designed to improve profile uniformity and thereby enhance the electrical performance of silicon power devices in large-scale production. The effects of trench sidewall modification on the morphology, structure and electrical properties were studied. Plasma-induced damage in etching processes was also observed and briefly explained. Straight and smooth sidewall profiles were achieved through adjusting the SF6/CHF3 proportion in a combined etchant gas flow in the main etching procedure. By comparing HRSEM images from different etching protocols, it was evident that an enhanced CHF3 flow formed a proper passivation of the sidewall, eliminating the ion damages that are common in current main etch steps. To address the impurities introduced from the etchant gas and improve the gate oxide uniformity, further steps of depolymerization were applied in a plasma asher chamber, followed by wet clean steps. In the meantime, the plasma-induced charge accumulation effect was reduced by UV curing. Improved trench sidewall profiles and the gate oxide uniformity contributed to a lower leakage current between the gate and source terminals, leading to an overall yield enhancement of device properties in large-scale silicon wafer fabrication.

Introduction of IC Manufacturing to Amateurs

In the fabrication of silicon wafers to create integrated circuits, chemistry and physics play a significant role. It is important to change the silicon wafer surface conditions and properties using both innocuous and harmful compounds, particular and uncommon circumstances, plasma-state elements, and RF (Radio Frequency) energies. Starting with the production of silicon wafers, sands are molten under high temperature in order to change its molecular structure. In this process, silicon ingot with particular diameter is formed and sliced into pieces of wafer. Following by chemical manufacture, wafer would be prepared to be fabricated into integrated circuits. Then, the circuits would be drawn onto the wafer through oxidation, photolithography, etching, diffusion, and ion implanation. After those fabrication, all these components (transistors, resistors, capacitors, and so on) were only accessible as discrete units, would have taken up most of a medium-sized room 20 years ago, the devices currently fill a one-inch square IC’s surface. When it comes to wafer sorting, a systematic mode will be used to take each bad die from the whole die pie. The researchers will use the relative finder and tester to gain the situation for each die and this work will bring foundation to the following stages including packaging and final test. The packaging process comes to the next consideration. This work divides the packaging process into five steps. All those steps are listed clearly in the essay below, from sawing up the wafer into an individual die to marking the packages. The final process after packaging is the final test. The final test is not such complicated. So this work only introduces the devices that it will use and its purpose.

High surface integrity fabrication of silicon wafers using a newly developed nonwoven structured grind-polishing wheel

Silicon wafer is a predominant substrate material in integrated circuits (IC) manufacturing. Currently, grinding is employed as a major machining method for back-thinning and flattening of the wafers. To obtain high surface/subsurface quality of ground silicon wafer, a novel nonwoven structured grind-polishing wheel with ultrafine abrasives is developed in this work. The developed wheel uses zirconia (ZrO2) with a grit diameter of 200 nm as abrasives, where the nonwoven fibers are employed as structures to support the abrasives. By measuring the surface and subsurface quality of ground silicon, grinding performance of the developed grind-polishing wheel is investigated and compared to that of #8000 diamond wheel, which is a commercial grinding wheel with the smallest grit size. The grinding experimental results show that the surface produced by the developed wheel has a surface roughness Ra of 0.45 nm, and a thickness of subsurface damage layer about 67 nm. In addition, the material removal rate for silicon wafers machined by the developed wheel is 0.86 μm/min. Compared with the #8000 diamond wheel, the developed wheel is more suitable for the semi-fine finishing process to produce a smooth surface at reduced time and cost.

Fully Bottom‐Up Waste‐Free Growth of Ultrathin Silicon Wafer via Self‐Releasing Seed Layer (Adv. Mater. 41/2021)

Bottom-Up Fabrication In article number 2103708, Joon-Ho Oh, Ka-Hyun Kim, and co-workers present the unprecedented fabrication of crystalline silicon wafers and solar cells by a fully bottom-up growth method without wasting substrate, in contrast to conventional technologies that sacrifice large amounts of raw material. A plasma-assisted epitaxially grown silicon seed layer with a self-organized nanogap is key for the realization of the fully bottom-up process. The results represent a technological breakthrough in advanced silicon microelectronics and photovoltaics.

Fully Bottom-Up Waste-Free Growth of Ultrathin Silicon Wafer via Self-Releasing Seed Layer.

The fabrication of ultrathin silicon wafers at low cost is crucial for advancing silicon electronics toward stretchability and flexibility. However, conventional fabrication techniques are inefficient because they sacrifice a large amount of substrate material. Thus, advanced silicon electronics that have been realized in laboratories cannot move forward to commercialization. Here, a fully bottom-up technique for producing a self-releasing ultrathin silicon wafer without sacrificing any of the substrate is presented. The key to this approach is a self-organized nanogap on the substrate fabricated by plasma-assisted epitaxial growth (plasma-epi) and subsequent hydrogen annealing. The wafer thickness can be independently controlled during the bulk growth after the formation of plasma-epi seed layer. In addition, semiconductor devices are realized using the ultrathin silicon wafer. Given the high scalability of plasma-epi and its compatibility with conventional semiconductor process, the proposed bottom-up wafer fabrication process will open a new route to developing advanced silicon electronics.

Oxygen concentration dependence of as-grown defect formation in nitrogen-doped Czochralski silicon single crystals

The interstitial oxygen concentration ([OI]) dependence of the as-grown defect (voids and dislocation clusters) behavior in nitrogen-doped silicon crystals fabricated by Czochralski technique (Cz-Si) have been investigated. Nitrogen-doped Cz-Si crystals with [OI] values of 7–8 and 1–3 × 1017 atoms cm−3 are evaluated, and it was found that the range of v/G in which as-grown defect-free (AGDF) region can be obtained become wide with decreasing [O I], where v is the crystal growth rate and G is the axial temperature gradient at the solid–liquid interface. This result indicates that as-grown defect suppression effect by nitrogen doping is enhanced at low [OI].By the analysis based on a thermodynamic model, it is shown that nitrogen–vacancy (NV) and nitrogen–oxygen (NO) complexes compete in the nitrogen-doped Cz-Si crystals and their concentration fraction changes with [OI] value. At low [OI], the concentration of the NO complex becomes low; thus, the concentration of nitrogen that can form NV complexes increases, thereby enhancing the as-grown defect suppression effect. Silicon wafers for insulated gate bipolar transistors (IGBTs) are required AGDF and oxide precipitate-free, therefore nitrogen-doped Cz-Si crystals with low [OI] values are suitable for the fabrication of silicon wafers for IGBTs.

Evaluating critical metals contained in spintronic memory with a particular focus on Pt substitution for improved sustainability

Thanks to their unique combination of properties: non-volatility, speed, density and write endurance, spintronic memory called spin transfer-torque Magnetic Random Access Memory (STT-MRAM) is expected to play a major role in the future development of the Internet of Things (IoT) and more generally in information and communication technologies. This type of spintronic device is usually made of materials, some of which can be classified as critical. Recent studies have evaluated critical materials contained in magnetic random access memory (Ku, 2018; European Commission, 2020 [1,2]). However, in those cases the type of memory analyzed belongs to the first generation of MRAMs developed in the early 2000s. Nowadays, the memory devices are magnetized perpendicularly to the plane of the layers and contain a synthetic antiferromagnet (SAF) that provides a high coercivity to the STT-MRAM reference layer with reduced stray field. This SAF is typically made of cobalt (Co) and platinum (Pt) multilayers antiferromagnetically coupled across a thin ruthenium (Ru) layer. Due to the high-embodied energy of platinum group metals (PGMs), a common concern when evaluating these materials is the environmental risk associated with their production. An evaluation of the environmental and economic risks of using such multilayers is first reported here, followed by a discussion of its supply risk. Substitution of Co/Pt multilayers by Co/Ni multilayers can lead to a reduction by 3–4 orders of magnitude in terms of energy requirements or global warming potential (GWP) associated with the use of these multilayers. An alternative concept based on perpendicular shape anisotropy (PSA) can also yield a reduction by 1–2 orders of magnitude in these quantities. However, for the case of STT-MRAM, tiny quantities of PGM layers are used in comparison with the mass of the silicon wafers on which these type of devices are grown. Therefore, the environmental and economic impact of the silicon wafer fabrication is found to be much higher than that of the PGM materials incorporated in the STT-MRAM stacks. Nonetheless, the high supply risk associated with PGMs remains a reason for awareness. One explored possibility is a SAF structure based on Co/Ni multilayers which can have similar performance. A second more challenging alternative is also proposed based on the aforementioned PSA concept. Finally, we address the case of several other metals identified by the European Commission as critical and used in MRAM such as W or Ta, both recently included in the EU's Conflict Minerals Regulation released in January 2021 (https://ec.europa.eu/trade/policy/in-focus/conflict-minerals-regulation/regulation-explained/, 2020 [3]).

19.2%-Efficient Multicrystalline Silicon Solar Cells via Additive-Free Mechanical Grinding Surface Pretreatment for Diamond-Wire-Sawn Wafers

The introduction of diamond wire sawing (DWS) technology has resulted in significant cost reduction in the fabrication of crystalline silicon wafers. However, the DWS process results in parallel wheel marks, saw damage, and formation of an amorphous silicon layer on the surface, which causes difficultly in effectively forming the desired surface texture using conventional acidic etching (also known isotropic etching) techniques for multicrystalline silicon (mc-Si) wafers. In this study, we propose a novel pretreatment grinding (NPTG) technique as a method to address such issues. This is a relatively simple and inexpensive method that does not utilize processes that require the use of expensive equipment, such as vacuum equipment. Additionally, it makes use of environment-friendly procedures that do not require materials such as metal catalysts and additives that cause environmental pollution. The proposed NPTG method provides a good surface topology for effective texturing using a conventional acidic etching solution, and as a result, a uniform texture can be applied to DWS mc-Si wafers. Under the optimized experimental conditions in this study, a weighted average reflectance of 22.63% was achieved after the NPTG was applied. This reflected 6.67% less light than the 29.3% after conventional acidic texturing without the NPTG using DWS mc-Si wafers. Further, a solar cell fabricated using the DWS mc-Si wafers treated with the NPTG method achieved a cell efficiency of approximately 19.2%.

Multi-Objective Optimization of Wire-Electric Discharge Machined Ultrathin Silicon Wafers Using Response Surface Methodology for Solar Cell Applications

Abstract Recent investigations on the fabrication of ultrathin silicon (Si) wafers using wire-electric discharge machining (wire-EDM) were observed to possess some inherent limitations. These include thermal damage (TD), kerf-loss (KL), and low slicing rate (SR), which constraints its industrial use. The extent of TD, KL, and SR largely depends on the process parameters such as open voltage (OV), servovoltage (SV), and pulse on-time (Ton). Therefore, optimizing the parameters that pertain to minimum TD and KL while maintaining a higher SR is the key to improvement in the fabrication of Si wafers using wire-EDM. Thus, this study is an effort to analyze and identify the optimal parameters that relate to the most effective Si slicing in wire-EDM. A central composite design (CCD)-based response surface methodology (RSM) was used for optimizing the process parameters. The capability to slice Si wafers in wire-EDM was observed to be influenced by the discharge energy, which significantly impacted the overall responses. The severities of TDs were observed to be mainly dominated by the variation in OV and Ton due to the diffusion of thermal energy into the workpiece, leading to melting and subsequent resolidification. For high productivity, the optimized parameters resulted in a SR of 0.72 mm/min, TD of 17.44 μm, and a kerf-loss of about 280 μm.

Two-step crystallization and solid–solid transitions in binary colloidal mixtures

Crystallization is fundamental to materials science and is central to a variety of applications, ranging from the fabrication of silicon wafers for microelectronics to the determination of protein structures. The basic picture is that a crystal nucleates from a homogeneous fluid by a spontaneous fluctuation that kicks the system over a single free-energy barrier. However, it is becoming apparent that nucleation is often more complicated than this simple picture and, instead, can proceed via multiple transformations of metastable structures along the pathway to the thermodynamic minimum. In this article, we observe, characterize, and model crystallization pathways using DNA-coated colloids. We use optical microscopy to investigate the crystallization of a binary colloidal mixture with single-particle resolution. We observe classical one-step pathways and nonclassical two-step pathways that proceed via a solid-solid transformation of a crystal intermediate. We also use enhanced sampling to compute the free-energy landscapes corresponding to our experiments and show that both one- and two-step pathways are driven by thermodynamics alone. Specifically, the two-step solid-solid transition is governed by a competition between two different crystal phases with free energies that depend on the crystal size. These results extend our understanding of available pathways to crystallization, by showing that size-dependent thermodynamic forces can produce pathways with multiple crystal phases that interconvert without free-energy barriers and could provide approaches to controlling the self-assembly of materials made from colloids.

Controllable fabrication and mechanism study of textured ultra-thin silicon wafers via one-step Cu-assisted chemical etching

In this paper, the one-step Cu-assisted chemical etching method is reported for controllable thinning and texturization on mono-crystalline silicon in Cu2+/HF/H2O2 mixture solution. HF and Cu2+ exhibited a synergetic effect on accelerating etching process while H2O2 slowed down the preferential Si (100) etching by oxidizing the Cu atoms. Within optimal 0.15 M Cu2+/4 M HF/0.88 M H2O2 solution, quasi-inverted pyramid-like structures of 2–4 μm in size and a reflectance of 8.46% were obtained at 20 °C. By adjusting the temperature and etching time, ultra-thin silicon wafers with thickness of 19–120 μm were fabricated. Comparing the microstructures obtained at 20 °C and 60 °C, widths and inclination angles were distinct. By illustrating the transportation and distribution of holes during the etching process, the intrinsic connection between thinning and texturization was studied. The etching results, including etching rates and morphologies, were determined by the distribution of holes between the B’ and B” orbitals. In summary, controllable fabrication of textured ultra-thin silicon wafers with desired thickness and microstructures could be achieved by one-step, short-time and low-temperature Cu-assisted chemical etching method, exhibiting a great potential use in ultra-thin silicon solar cells.

Fabrication and characterization of double curvature bendable silicon wafers

We report the design and implementation of a unique, wafer sized stretchable and bendable monolithic silicon matrix structure. The achieved stretchability not only allows for one directional folding, but is capable of bending in two directions simultaneously, which is required to conform the structure to complex shapes such as spheres, tori, hyperboloids or a combination of them. Moreover, it also enables dynamic mechanical deformation of the structure to cope with a moving environment, e.g. the wall of the heart muscle. The minimal measured bending radius is 8 mm, which is 20% smaller than the current state of art. Furthermore, a new fabrication process is proposed that enables the use of common wafers. This enables a broader and more accessible applicability compared to earlier work, which is based on non-standard wafers, or the more expensive SOI wafers. The technique can lead to a revolutionary potential of applications, especially in the medical field, by enabling complex silicon monitoring systems to be linked to organs without hindering them.

(Invited) SiGe BiCMOS Heterogeneous Integration Using Wafer Bonding Technologies

Heterogeneous integration has been a very attractive research topic for the last decades. Due to the limitations for further device scaling the More-than-Moore approach based on heterogeneous integration has been pointed out as the key integration path for future smart system integration [1]. Temporary and permanent wafer bonding technologies are one of the key enabling technologies for heterogeneous integration. Temporary wafer bonding is a well-established bonding technique to provide a stable handling and fabrication of ultra-thin silicon wafers. Permanent wafer bonding with various electrical isolating or conductive bonding interfaces is applied for wafer-level heterogeneous device integration [2]. Making available both temporary and permanent wafer bonding technologies together with a high performance SiGe BiCMOS technology will pave the way for new applications like millimeter-wave packaging, 3D-integration and smart sensors to realize multi-functional and miniaturized systems. The potential of temporary and permanent wafer bonding techniques for heterogeneous integration of a high performance SiGe BiCMOS technology with additional devices and technology modules will be presented by three different application examples namely BiCMOS embedded Through-Silicon Vias (TSV), silicon interposer including substrate-integrated waveguides and BiCMOS embedded microfluidics. With respect to the different applications the potential and the main technology obstacles for SiGe BiCMOS temporary and permanent wafer bonding will be highlighted. While the temporary wafer bonding process with subsequent wafer thinning and thin wafer backside fabrication is mainly limited by the robustness of adhesives against high temperature and high vacuum process conditions, the permanent wafer bonding based on SiO2-SiO2 fusion bonding is mainly limited by the demanding surface requirements in terms of roughness and wafer bow which has been optimized to fulfill the requirements. By optimizing the SiGe BiCMOS technology both temporary and permanent wafer bonding together with subsequent semiconductor fabrication becomes feasible. In summary, the development of wafer bonding application together with an industrial-level BiCMOS process will be presented. By the use of temporary and permanent wafer bonding new applications in the area of heterogeneous integration becomes feasible making SiGe BiCMOS technologies more attractive for future smart system applications.

Binary Phase Diagrams and Thermodynamic Properties of Silicon and Essential Doping Elements (Al, As, B, Bi, Ga, In, N, P, Sb and Tl).

Fabrication of solar and electronic silicon wafers involves direct contact between solid, liquid and gas phases at near equilibrium conditions. Understanding of the phase diagrams and thermochemical properties of the Si-dopant binary systems is essential for providing processing conditions and for understanding the phase formation and transformation. In this work, ten Si-based binary phase diagrams, including Si with group IIIA elements (Al, B, Ga, In and Tl) and with group VA elements (As, Bi, N, P and Sb), have been reviewed. Each of these systems has been critically discussed on both aspects of phase diagram and thermodynamic properties. The available experimental data and thermodynamic parameters in the literature have been summarized and assessed thoroughly to provide consistent understanding of each system. Some systems were re-calculated to obtain a combination of the best evaluated phase diagram and a set of optimized thermodynamic parameters. As doping levels of solar and electronic silicon are of high technological importance, diffusion data has been presented to serve as a useful reference on the properties, behavior and quantities of metal impurities in silicon. This paper is meant to bridge the theoretical understanding of phase diagrams with the research and development of solar-grade silicon production, relying on the available information in the literature and our own analysis.

Wetting behaviors of the molten silicon on graphite surface

A theory which was proposed by Scheid et al. in 2010 (Scheid B, van Nierop E A, Stone H A 2010 Appl. Phys. Lett. 97 171906) suggests that very thin ribbons of molten material can be drawn out of a melt by adequately tuning the temperature gradient along the dynamic meniscus that connects the static meniscus at the melting bath to the region of the drawn flat film. Based on this theory, one-step manufacturing ultra-thin silicon wafer by pulling out from a molten silicon bath has attracted considerable attention in recent year due to its many attractive performances such as low cost, simple process, etc. By using this method, solar cell can have intensive applications due to its low cost and stable output efficiency. The results show that the thermal capillarity effect plays a great role in preparing the ultra-thin silicon. The thickness of the silicon wafer is sensitive to the capillary length and the strength of the surface tension variation as well. In order to reveal the mechanism for the effect of thermal capillary on the fabrication of ultra-thin silicon wafer, a thermal capillary finite element model is developed for the horizontal ribbon growth system to study the wetting behaviors of molten silicon on graphite. The mathematical model is established and simulated by using the commercial software; several parameters such as mass, viscous stress and capillary force are calculated. The wetting processes are tested by changing surface roughness (Ra=0.721 m and Ra=0.134 m), system temperatures (17371744 K), and durations (1030 s) at constant temperature on a high-temperature, high-vacuum contact angle measurement instrument. It is found that the wetting angle of silicon droplet on graphite decreases with surface roughness and temperature increasing; the wetting angle comes down with time going by (lasting 30 s) at constant temperature, which is consistent with the theoretical result of Wenzel. The influence of surface tension on wetting process is studied by analyzing the distributions of pressure and velocity field. It is shown that the differential pressure at the solid-liquid interfaces, induced by thermal capillary effect, decreases in the wetting process and reaches a balance which prevents the droplet from being wetted. At T=1700 K, the wetting angle and the shape of droplet change quickly within 0.4 ms and eventually become stable after 5 ms as shown in the simulation. The spreading length L and droplet height h at the steady-state are calculated with considering the influence of droplet radius on the wetting process. The results show that both L and h are directly related to the steady-state of wetting angle. The surface tension dominates the wetting process for droplet radius R0 5mm; while for R0 5 mm, the wetting process is dominated by gravity.

다결정 실리콘 웨이퍼 직접제조에 대한 공정변수 영향

A ribbon-type polycrystalline silicon wafer was directly fabricated from liquid silicon via a novel technique for both a fast growth rate and large grain size by exploiting gas pressure. Effects of processing parameters such as moving speed of a dummy bar and the length of the solidification zone on continuous casting of the silicon wafer were investigated. Silicon melt extruded from the growth region in the case of a solidification zone with a length of 1cm due to incomplete solidification. In case of a solidification zone wieh a length of 2 cm, on the other hand, continuous casting of the wafer was impossible due to the volume expansion of silicon derived from the liquid-solid transformation in solidification zone. Consequently, the optimal length of the solidification zone was 1.5 cm for maintaining the position of the solid-liquid interface in the solidification zone. The silicon wafer could be continuously casted when the moving speed of the dummy bar was 6 cm/min, but liquid silicon extruded from the growth region without solidification when the moving speed of the dummy bar was 9 cm/min. This was due to a shift of the position of the solid-liquid interface from the solidification zone to the moving area. The present study reports experimental findings on a new direct growth system for obtaining silicon wafers with both high quality and productivity, as a candidate for an alternate route for the fabrication of ribbon-type silicon wafers.

Whole Air Canister Sampling Coupled with Preconcentration GC/MS Analysis of Part-per-Trillion Levels of Trimethylsilanol in Semiconductor Cleanroom Air

The costly damage airborne trimethylsilanol (TMS) exacts on optics in the semiconductor industry has resulted in the demand for accurate and reliable methods for measuring TMS at trace levels (i.e., parts per trillion, volume per volume of air [ppt(v)] [~ng/m(3)]). In this study I developed a whole air canister-based approach for field sampling trimethylsilanol in air, as well as a preconcentration gas chromatography/mass spectrometry laboratory method for analysis. The results demonstrate clean canister blanks (0.06 ppt(v) [0.24 ng/m(3)], which is below the detection limit), excellent linearity (a calibration relative response factor relative standard deviation [RSD] of 9.8%) over a wide dynamic mass range (1-100 ppt(v)), recovery/accuracy of 93%, a low selected ion monitoring method detection limit of 0.12 ppt(v) (0.48 ng/m(3)), replicate precision of 6.8% RSD, and stability (84% recovery) out to four days of storage at room temperature. Samples collected at two silicon wafer fabrication facilities ranged from 10.0 to 9120 ppt(v) TMS and appear to be associated with the use of hexamethyldisilazane priming agent. This method will enable semiconductor cleanroom managers to monitor and control for trace levels of trimethylsilanol.

CO<sub>2</sub>-Dissolved Water Cleans for 2xnm-Node Silicon Devices in a Single Wafer Megasonic System

Megasonic cleans have been applied to remove defects such as particles and polymer/resist residues in silicon wafer fabrication of IC devices. However, with the shrink of device technology node, megasonic cleans are being challenged to maintain high cleaning efficiency promoted by streaming force of stable cavitation for the smaller particles without producing pattern collapse caused by violent implosions of transient cavities [. S. Kumari et al. reported that CO2-dissolved water (CO2 DIW) was potentially able to suppress wafer damage during megasonic exposure by minimizing unrestrained explosion of transient cavities. This is accomplished through the study on Sonoluninescence (SL), the phenomenon of release of light when liquid is irradiated by sound wafers of sufficient intensity, as a sensitive indicator of cavitation events [2, . This paper compares the effects of CO2 dissolution on particle removal efficiency (PRE) and pattern collapse in a range of megasonic power with >100nm-size Si3N4 particles and 2xnm node line/space-pattern, respectively to N2-gasified water (N2 DIW).

Ribbon Silicon Material for Solar Cells

Solar cell is one of most important renewable energy. But now it is not be widely used because of its high cost compared with traditional resource. Ribbon silicon is one new low cost solar cell material avoiding ingot casting and slicing. It is a promising silicon wafer fabrication technology alternative to traditional ingot casting and slicing. Using ribbon silicon can make solar cell production cost greatly reduced. In this paper EFG, String Ribbon and a novel silicon wafer are discussed.

Characterization of Recrystallized Sintered Silicon Substrates for Photovoltaic's Solar Cells

In this work, we describe a new process of fabrication of low-cost silicon wafers which are produced by sintering silicon powder followed by a Zone Melting Recrystallization (ZMR) step. The influence of the ZMR step on the physical and chemical characteristics of the substrate is reported. The evolution of the impurities content along the different steps of the substrate process was studied. In addition to the increase of the grain size and improved crystalline quality, the ZMR step allowed reducing the total impurities and especially the oxygen content already present in sintered wafer. Furthermore the ZMR improved drastically the value of the minority charge carrier lifetime resulting from impurities reduction and the crystal growth in the sintered substrate. The recrystallized sintered wafers showed a good majority carrier mobility of 245 cm2 V-1 s-1 and a doping level of 5x1016 atm cm-3. The efficiency of 8.9% obtained with the recrystallized sintered wafer, using the simplified cell process, is very encouraging.