Fabrication Of MOSFETs Research Articles

Enabling of CMOS Circuit using Dual Material Gate Germanium Pocket Induced FDSOI MOSFET

This research presents a comparison of the electrical performance of a double-side induced germanium-pocket (IGP) FD-SOI MOSFET and a dual material gate IGPFDSOI (DIGPFDSOI). The electrical performance is reviewed by comparing the device parameters like drain current, band diagram, lateral electric field, surface potential, and work function of the gate material. The proposed structure exhibits excellent characteristics compared to the IGPFDSOI MOSFET. The proposed structure has a greater Ion/Ioff ratio, a lower subthreshold slope, reduced capacitance, and an elevated cut-off frequency. The implementation of a dual metal gate is considered a superior method in comparison to FD-SOI technology because it effectively reduces the negative effects of scaling. A study is being done to analyze the differences in the work functions of metal gates to evaluate the effectiveness of the proposed construction. The comparison evaluation shows that the suggested design can be used for both digital and analog tasks because it has a higher switching frequency and a better cut-off frequency. Apart from this, the proposed structure can also be implemented without making substantial changes to the conventional FD-SOI MOSFET fabrication process flow. Here, we are using n-type and p-type DIGPFDSOI MOSFETs to make a CMOS converter circuit. Sentaurus TCAD is used to simulate and analyze the performance of the proposed structure.

Application of Pulsed Green Laser Activation to Top-Tier MOSFET Fabrication for Monolithic 3-D Integration

Application of Pulsed Green Laser Activation to Top-Tier MOSFET Fabrication for Monolithic 3-D Integration

Surface-Localized 15R Formation on 4H-SiC (0001) Si-Face by Laser Annealing for Power N-Type MOSFETs

A SiC MOSFET fabricated on a thin 15R-SiC layer on top of a 4H-SiC would benefit from both the higher inversion channel mobility of 15R-SiC and higher bulk mobility of 4H-SiC. In this work, a method based on Al implantation followed by UV laser annealing (UV-LA) to form 15R-SiC on 4H is shown. Evaluation of crystal quality and SiC polytype identification are performed by Raman spectroscopy. We show that UV-LA is able to grow 15R-SiC and cure the crystal damaged by ion implantation until a level close to the pristine substrate. This opens new perspectives for fabrication of SiC n-type MOSFETs.

Fabrication of GeSn Nanowire MOSFETs by Utilizing Highly Selective Etching Techniques

Germanium–tin (GeSn) epitaxy layer was prepared on an 8-in SOI wafer with a Ge buffer layer. The etching rates of different solutions for the GeSn layer were investigated. The ammonia peroxide mixture can remove the Ge buffer layer with high efficiency and selectivity to the GeSn layer. Heated ammonia solution is able to etch the Si layer without damaging the GeSn layer significantly. The two-step etching process developed in this study is conducive to achieving GeSn nanowires (NWs) by selectively etching the Ge buffer and Si bottom layers. GeSn NWFETs were fabricated and measured. The strain of the GeSn NW channels is preserved with the optimized fabrication process proposed in this study.

Demonstration of self-aligned β-Ga2O3 δ-doped MOSFETs with current density >550 mA/mm

We report on the design and fabrication of β-Ga2O3 self-aligned lateral MOSFETs by utilizing a heavily doped β-Ga2O3 cap layer. The fabrication of the self-aligned device used a combination of in situ Ga etching for damage free gate recess, in situ growth of Al2O3 for gate dielectric, and atomic layer deposited Al2O3 based sidewall spacers to form highly scaled (<100 nm) source–gate and gate–drain access regions. The fabricated device showed a record high DC drain current density of 560 mA/mm at a drain bias of 5 V. The DC current density was found to be limited by excessive self-heating resulting in premature current saturation in the device. Pulsed I–V measurements of the device showed a record high current density of 895 mA/mm and a high transconductance of 43 mS/mm, thanks to reduced self-heating in the device. The high current densities obtained in this work are promising for the development of high power density devices based on β-Ga2O3.

Effects of Channel Length Scaling on the Electrical Characteristics of Multilayer MoS2 Field Effect Transistor

With the rapid miniaturization of integrated chips in recent decades, aggressive geometric scaling of transistor dimensions to nanometric scales has become imperative. Recent works have reported the usefulness of 2D transition metal dichalcogenides (TMDs) like MoS2 in MOSFET fabrication due to their enhanced active surface area, thin body, and non-zero bandgap. However, a systematic study on the effects of geometric scaling down to sub-10-nm nodes on the performance of MoS2 MOSFETs is lacking. Here, the authors present an extensive study on the performance of MoS2 FETs when geometrically scaled down to the sub-10 nm range. Transport properties are modelled using drift-diffusion equations in the classical regime and self-consistent Schrödinger-Poisson solution using NEGF formulation in the quantum regime. By employing the device modeling tool COMSOL for the classical regime, drain current vs. gate voltage (ID vs. VGS) plots were simulated. On the other hand, NEGF formulation for quantum regions is performed using MATLAB, and transfer characteristics are obtained. The effects of scaling device dimensions, such as channel length and contact length, are evaluated based on transfer characteristics by computing performance metrics like drain-induced barrier lowering (DIBL), on-off currents, subthreshold swing, and threshold voltage.

DDDMOSFET Performance Improvement by Gate Oxide Removal Followed by Silicided Source/Drain Formation in Gate Slots

In this work, the intentional insertion of slots in metal gate (MG) is introduced to solve the dishing issue for the double-diffused drain MOSFET (DDDMOSFET) fabrication. For traditional DDDMOSFET, the gate oxide layer in slots will be reserved to improve the device reliability, which requires an additional photomask to screen the gate/slot regions during the following sidewall formation and source/drain (S/D) implantation. This makes the process more complicated with increased cost. Without that additional photomask, it is proposed that the removal of gate oxide layer in slots can directly allow the floating S/D formation and the followed Ni silicidation there. It is demonstrated that such a novel process can not only relieve the MG dishing issue but can also effectively result in ~16% higher ON current and comparable OFF current for both N- and P-DDDMOSFETs without threshold voltage shift after applying electrical stress on gates. It is also revealed that the floating silicided S/Ds in slots have negligible influence on device breakdown characteristics. By saving one photomask, this work proposes a novel solution for the effective integration of core devices with very small feature sizes and high-voltage (HV) devices with large feature sizes in the same die, which is a common challenge for display driver chip fabrication using high- <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">${k}$ </tex-math></inline-formula> /MG (HK/MG) technology.

Demonstration of 4H-SiC CMOS digital IC gates based on the mainstream 6-inch wafer processing technique

In this article, the design, fabrication and characterization of silicon carbide (SiC) complementary-metal-oxide-semiconductor (CMOS)-based integrated circuits (ICs) are presented. A metal interconnect strategy is proposed to fabricate the fundamental N-channel MOS (NMOS) and P-channel MOS (PMOS) devices that are required for the CMOS circuit configuration. Based on the mainstream 6-inch SiC wafer processing technology, the simultaneous fabrication of SiC CMOS ICs and power MOSFET is realized. Fundamental gates, such as inverter and NAND gates, are fabricated and tested. The measurement results show that the inverter and NAND gates function well. The calculated low-to-high delay (low-to-high output transition) and high-to-low delay (high-to-low output transition) are 49.9 and 90 ns, respectively.

Study of Vertical Capacitance in an n-Type 4H-SiC Stepped Thick-Oxide Trench MOS Structure

In this work, characteristics of trench sidewall capacitance were investigated in a 4H-SiC stepped thick-oxide (STO) trench metal–oxide–semiconductor (MOS) structure. Multigroup SiC trench MOS capacitor test patterns with different structures and geometric parameters were designed and fabricated. From the capacitance–voltage measurements, the characteristics of the described SiC STO trench MOS were calculated and analyzed, including the thicknesses of the oxide at different locations in trench, the position of the oxide step at trench sidewall, and the flat-band voltages as well as the oxide charge densities of MOS from the upper part and lower part of oxide step at trench sidewall. Results showed that the flat-band voltages of MOS from the upper part (10.2 V) and lower part (12.5 V) of trench sidewall step had pronounced positive shifts over the ideal flat-band voltage (0.36 V), indicating a massive negative charges in the sidewall oxide film. Meanwhile, the net oxide charge density of MOS from the lower part of sidewall step ( <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">$- 0.92\times10$ </tex-math></inline-formula> <sup xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">12</sup> cm <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">$^{-2}$ </tex-math></inline-formula> ) was smaller than that from the upper part ( <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">$- 2.41\times10$ </tex-math></inline-formula> <sup xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">12</sup> cm <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">$^{-2}$ </tex-math></inline-formula> ), which was likely attributed to the massive shallow states in the oxide and to the poor quality of the thick-oxide film grown via chemical vapor deposition technology. The present works are providing a convenient technology to monitor the trench MOS structure by measuring the capacitance during SiC trench MOSFETs fabrication.

(Digital Presentation) Study on the Electrical Characteristics and Band Diagrams of Ga2O3 MOS Gate Stacks

β-Ga2O3 is expected as one of the candidate materials for high-efficient and cost-effective power devices for high-voltage applications [1]. For the fabrication of MOSFETs the understanding of band diagrams of MOS structure is inevitably important. However, the previous reports on band alignments of β-Ga2O3 and various dielectrics including Al2O3 and SiO2 are controversial with significant inconsistencies in their values [2]. Since the ideal band diagram referring to the vacuum level is not clarified we cannot tell the Fermi level of β-Ga2O3 and the flat-band voltage (Vfb) shift of MOS capacitors. In this study we fabricated MOS structures and its band diagram was investigated from photoelectron spectroscopy.We employed SiO2 as the gate dielectric. Single crystalline β-Ga2O3 (001) wafers with ~2×1016 cm-3 n-type doped epitaxial layers were cleaned in diluted HF solution. Then SiO2 films were deposited by electron-beam evaporation of Si in O2 ambient of ~1×10-2 Pa, followed by post-deposition annealing (PDA) in 1 atm-O2 at various temperatures. Au was evaporated as gate electrode to form MOS capacitors. Ultraviolet photoelectron spectroscopy (UPS) was conducted to determine the energy level of the valence band edge on the surface of β-Ga2O3 epitaxial layer referring to the vacuum level. The valence band spectrum of ~4nm-thick SiO2/β-Ga2O3 was also investigated by x-ray photoelectron spectroscopy to determine the valence band offset at the interface.From C-V characteristics of MOS capacitors with different PDA conditions, the higher PDA temperature was found to be beneficial to achieve nearly-ideal C-V characteristics. A negligibly-small hysteresis was obtained for the one fabricated with O2-PDA at 1000℃ [3]. The energy profiles of interface state density (Dit) were determined by conductance method for the samples of different PDA conditions. The values of Dit decreased for higher PDA temperature down to ~1010 cm-3 at the energy level of EC−0.2 eV [3]. These values are significantly lower than typically reported ones for ALD-Al2O3 MOS structures on β-Ga2O3 [4]. The additional annealing at low temperature at 400℃ works for the further reduction of hysteresis to less than 1 mV/nm.Next the band diagrams of the MOS structures were investigated. From the UPS spectra we could deduce the energy level of valence band edge referring to the vacuum level, from the difference between minimum (cut-off) and maximum edges of the obtained kinetic energy spectra of photoelectrons. We also evaluated the valence band offset from the deconvolution of the valence band XPS of thin SiO2/β-Ga2O3 stack. From the energy edge difference between the deconvoluted spectra corresponding to SiO2 and Ga2O3, respectively, the valence band offset ~1.1 eV was deduced, which is not conflicting with the estimated valence band edge energy of Ga2O3 and the well-reported valence band edge energy of SiO2. The conduction band edge energy was also estimated assuming the bandgap of β-Ga2O3 (4.7eV) [1]. Considering the Fermi-level of β-Ga2O3 with n-type doping of ~2×1016 cm-3 was approximated to be ~0.1 eV from the conduction band edge, the Fermi-level on the surface of β-Ga2O3 epitaxial layer after 1000℃ O2 annealing was estimated to be 3.6-3.7eV below the vacuum level [5]. Note that this value would be significantly smaller than the one simply estimated from the previously reported electron affinity of Ga2O3 [6].Finally the Vfb shifts were investigated for the MOS capacitors fabricated with O2 annealing at 1000℃ with various thicknesses, referring to the ideal flat-band voltage determined with the Fermi-level of β-Ga2O3 as discussed above and the work function of Au electrode which was also determined with UPS measurement. As a result, we found the most of the Vfb values were around the ideal flat-band voltage irrespective of the film thickness from 20 to 60 nm, which indicates a small density of fixed charges <2×1011 cm-2 [5].In conclusion, we found that SiO2/β-Ga2O3 (001) MOS capacitors showed nearly-ideal electrical characteristics with small fixed charge density by applying O2-PDA at 1000℃. The band diagram for the MOS stacks referring to the vacuum level was clarified by photoelectron spectroscopy, which enables us to understand the β-Ga2O3 MOS interface properties correctly.

Inherent selective pulsed chemical vapor deposition of amorphous hafnium oxide / titanium oxide nanolaminates

Water-free Inherent selective pulsed chemical vapor deposition (CVD) of HfO2/TiO2 nanolaminates on Si and SiO2 in preference to SiCOH has been studied. SiCOH is highly porous alkylated SiO2, which is used as a nonreactive low-k dielectric. Ti(OiPr)4 [titanium(IV) isopropoxide] and Hf(OtBu)4 [Hafnium tert butoxide] were used in the CVD study. Previous studies showed that metal alkoxide precursors could form oxide films through thermal decomposition. However, single oxide films greater than 2 nm can be rough due to crystallization. To solve this issue, HfO2/TiO2 nanolaminate structures were studied. With sequential dosing of each precursor in a supercycle at 300 °C sample temperature, HfO2/TiO2 nanolaminate films with thin (less than 3 nm) sublayers were selectively deposited. The films were smooth with root mean square (RMS) roughness lower than 0.5 nm and almost amorphous from XRD analysis; this is unexpected since both oxides readily crystalize. Amorphous nanolaminate oxide film deposition with high selectivity was achieved by controlling each sublayer thickness and the Hf:Ti ratio. TEM studies proved that ∼ 20 nm of the nanolaminate film could also be selectively deposited on nanoscale patterned surfaces. This selective amorphous nanolaminate oxide CVD process has a potential to be applicable in the nanoscale patterning in MOSFET fabrication.

Realization with Fabrication of Dual-Gate MOSFET Based Source Follower

Realization with Fabrication of Dual-Gate MOSFET Based Source Follower

Realization with fabrication of double-gate MOSFET based boost regulator

In the regulator system, there is a voltage drop, which increases overall power dissipation. On the transient peaks, the amplifier cannot transport higher power. To avoid this situation, in this paper, a boost regulator has been designed. The novelty of this work is its basic cell which is a Double-Gate (DG) MOSFET in place of traditional MOSFETs. This DG MOSFET technology provides a higher current in the boost switching converter. After designing this device, it has been fabricated and analyzed with its various parameters, including power characteristics. The proposed DG boost converter circuit can operate from 6 V to 14 V and produced the output variable voltage of 35 V. The voltage across the output resistor is 24 V with a maximum output ripple of 1%. It was observed that the power efficiency exceeds 98%. Using this designed device, the unregulated power supplies voltage and current ripple can be lowered.

Improved Short-Circuit Ruggedness for 1.2kV 4H-SiC MOSFET Using a Deep P-Well Implemented by Channeling Implantation

The trade-off relationship between specific on-resistance and short-circuit withstand time in 1.2 kV 4H-SiC MOSFETs was drastically increased using a novel device structure. MOSFETs with deep P-well-formed using channeling implantation were firstly demonstrated to improve short-circuit ruggedness (&#x007E;4 times longer than conventional MOSFET) with no negative impact on specific on-resistance. Proposed MOSFETs achieved short-circuit withstand time of <inline-formula> <tex-math notation="LaTeX">$8~\mu \text{s}$ </tex-math></inline-formula>. Channeling implant with low energy was conducted to form deep P-well junctions. Fabrication of a deep P-well using channeling implantation is demonstrated using no additional nor complicated processes when compared to the conventional MOSFET fabrication process. A comparison between the conventional and novel designs was performed in terms of the output characteristics, blocking behaviors, and short-circuit ruggedness.

Systematic Characterization of Plasma-Etched Trenches on 4H-SiC Wafers.

Silicon carbide power semiconductors overcome some limitations of silicon chips, and therefore, SiC is an attractive candidate for next-generation power electronics. In addition, the number of possible vertical devices that can be obtained on a given surface using the trench technique is significantly larger than that attainable using a planar setup. Moreover, a SiC trench power metal oxide semiconductor field-effect transistor (power MOSFET) structure removes the junction field-effect transistor (JFET) region (that would decrease the current flow width) and improves the channel density, thus reducing the specific electrical resistance. Consequently, in the present study, we report on the chemical bonding state of elements and structural characterization of trenches, obtained using SF6-based plasma etching, on the 4H-SiC polytype substrate. An interferometric algorithm that finds the endpoint to stop etching governed the trench depth. Scanning electron microscopy, transmission electron microscopy, atomic force microscopy, and X-ray photoelectron spectroscopy analyses stated the high quality and uniformity of the trenches. These materials are particularly promising for the fabrication of the SiC MOSFET to be implemented in the manufacturing of power devices.

L Style n-MOSFET Layout For Mitigating TID Effects

This paper proposes a new rad hard layout L style of nmos metal oxide semiconductor field effect transistor (n-MOSFET), which is evaluated to show that its efficacy at reducing radiation-induced leakage currents, thus improving the total ionization dose(TID) tolerance with very less area and parasitic capacitance as compared to enclosed layout transistor(ELT). This proposed layout structure is fully compatible to present commercial fabrication technology without any additional mask requirement as compared to conventional n MOSFET fabrication and can be used as radiation tolerant by design technique. The simulated ID - VG characteristics of the rad hard L n-MOSFET layout demonstrated the effectiveness of eliminating radiation-induced leakage current paths. The leakage current in proposed rad hard L n-MOSFET has been reduced by factor of 108 at 300Krad dose as compared to conventional layout n-MOSFET.

A comprehensive Analysis of Nanoscale Transistor Based Biosensor: A Review

Imperative introduction of biosensor in the field of medicine, defence, food safety, security and environmental contamination detection acquired paramount attraction. Thus the foundation of the fame of biosensors in detecting wide scope of biomolecules in innumerable fields has driven researchers in advancement of biosensor and enhancing more updates in devices. Among all semiconductor-FET based biosensors grab attraction due to their miniaturization,mass production, ultra-sensitive in nature, improved lifetime, rapid response and reduce thermal budgets. In this review, field effect based biosensors sensitive to ions their principle model along with pros and cons of different structures. Various performance characteristics for semiconductor based biosensor are explored along with detection of label free analytes such as tuberculosis, glucose, antigen 85-B with ISFET. Following with comprehensive detail on MOSFET junction less Silicon based Dual Gate Biosensor with their design parameters for biosensing of neutral and charged analytes with results summarized in table. Drawbacks of dual gate structure introduce cylindrical structures summarized in table with device parameters and respective sensitivity. Role of analytes size in choosing the cavity width and position of analytes influence the sensitivity is recorded. Recent advancement on selectivity, sensitivity and switching results the gate and channel engineering thus compound semiconductor came in picture. In last section challenges with solution and importance of III-V compound channel as scope in biosensor with taking the benefits of fabrication of III-V compound MOSFETs. Semiconductor compound properties are summarized in table for various applications in recent use.

Realization with Fabrication of Double-Gate MOSFET Based Buck Regulator

The traditional buck regulator provides the steady output voltage with high efficiency and low power dissipation. Various parameters of this regulator can be improved by the placement of Double-Gate (DG) MOSFET. The double-gate MOSFET provides twice the drain current flow, which improves the various parameters of buck regulator structure and inevitably increases the device performance and efficiency. In this research work, these parameters have been analyzed with implemented DG MOSFET buck regulator and realized the total losses 42.676 mW and efficiency 74.208%. This research work has designed a DG MOSFET based buck regulator with the specification of input voltage 12 V, output voltage 3.3 V, maximum output current 40 mA, switching frequency 100 kHz, ripple current of 10%, and ripple voltage of 1%.

Design and Fabrication of 4H-Sic Mosfets with Optimized JFET and p-Body Design

In this paper, 4H-SiC planar MOSFETs were designed and fabricated. By using TCAD tool, the trade-off between on-resistance and maximum gate oxide electric field was optimized. With optimized gate oxide growth process, the gate oxide’s critical electric field of 9.8 MV/cm and the effective barrier height of 2.57 eV between SiO2 and 4H-SiC were obtained. The field effective mobility with different p-body doping was compared and studied. The MOS interface state density of 1.12E12 cm-2eV-1 at EC - EIT = 0.21 eV and channel mobility of 19.3 cm2/Vs at VGS = 20 V were obtained. The fabricated MOSFET’s on-resistance of 6.4 mΩcm2 was obtained with hexagonal cell structure which is very consistent with the simulation results.

Realization with Fabrication of Parallel-Gate MOSFET Based Differential Amplifier

Realization with Fabrication of Parallel-Gate MOSFET Based Differential Amplifier