Extraction Of Effective Mobility Research Articles

P‐5: Improved Split C–V Technique for Effective Mobility Extraction in Self‐Aligned Top‐Gate Amorphous InGaZnO TFTs with Short Channel

In this paper, we evaluate the feasibility of the split capacitance‐voltage (C–V) technique for mobility extraction in self‐aligned top‐gate (SATG) amorphous InGaZnO (a‐IGZO) thin‐film transistors (TFTs) with short channel down to 5 μm. The accuracy of the effective mobility (μeff) extraction approach is greatly enhanced by properly de‐embedding the disturbances, including channel length reduction (ΔL), inner fringing capacitance (Cif), and source/drain access resistance (RSD). The results show that the parasitic bias‐dependent RSD and Cif in the inner fringe regions of the channel account for the underestimation of μeff on short‐channel devices.

Extraction of effective mobility of In0.8Ga0.2As/In0.52Al0.48As quantum well high-electron-mobility transistors on InP substrate

In this work, we explored the effective mobility of In-rich InxGa1-xAs/In0.52Al0.48As (x > 0.53) quantum well (QW) high-electron-mobility transistors (HEMTs) on an InP substrate. Historically, the carrier transport properties of these types of devices have been assessed mostly using their Hall mobility, not using the effective mobility, mainly because the excessive gate leakage current degrades and contaminates their measured capacitance voltage (CV) characteristics. However, our recent studies on these devices achieved a significant reduction in the gate leakage current, which motivated us to explore their effective mobility. In this work, therefore, we used a conventional split CV technique to determine and analyze the effective mobility of In0.8Ga0.2As/In0.52Al0.48As QW HEMTs. We also attempted to model the extracted effective mobility by considering three different scattering mechanisms—Coulombic scattering, phonon scattering and surface-roughness scattering— under the guidance of Matthiessen’s rule.

Improved Technique for Extraction of Effective Mobility by Considering Gate Bias-Dependent Inversion Charges in a Floating-Body Si/SiGe pMOSFET

Improved Technique for Extraction of Effective Mobility by Considering Gate Bias-Dependent Inversion Charges in a Floating-Body Si/SiGe pMOSFET

A New Method for Accurate Extraction of Source Resistance and Effective Mobility in Nanoscale Multifinger nMOSFETs

A new method is is developed for accurate extraction of the effective mobility ( $\mu _{\textrm {eff}}$ ) in the multifinger nMOSFETs with various poly-to-poly (PO-PO) spaces. The wide PO-PO space intends to increase the tensile stress from a contact etching stop layer (CESL) and yields higher $\mu _{\textrm {eff}}$ in the nMOSFETs. However, the source resistance ( $R_{S}$ ) emerges as a critical parasitic element in the multifinger devices with a large finger number. The wide PO-PO space generally leads to the further increase of $R_{S}$ , which may offset $\mu _{\textrm {eff}}$ improvement and degrade transconductance ( $g_{m}$ ). A two-end source line is proposed to reduce $R_{S}$ and the impact on $g_{m}$ . The complicated layout-dependent effects containing the CESL strain, $R_{S}$ , and 3-D fringing capacitances bring a crucial challenge to the $\mu _{\textrm {eff}}$ extraction. In this paper, a distributed transmission line model is derived for a reliable determination of $R_{S}$ , which is a key to the realization of accurate extraction of $\mu _{\textrm {eff}}$ and layout-dependent effects in multifinger devices.

On the effective mobility extraction by point-contact techniques on silicon-on-insulator substrates

In this work, we introduce the mobility vs. effective electric field representation for bare silicon-on-insulator substrates. The key factors determining the effective field in the silicon film are identified and modeled. This representation sheds light on the origins of the carrier mobility differences observed in passivated and non-passivated wafers. At low effective electric field, the roles of the Coulomb scattering, determined by the top-interface, and the impact of the silicon film thickness are clearly disclosed. Two and four point-contact characterization techniques are compared; caution is called when the two point Pseudo-MOSFET configuration is used without calibration of the current form factor, since it may lead to an underestimation of the mobility values. Nevertheless, when the effective field and current form factors are evaluated accurately, we report that the carrier mobility of the silicon film at high effective electric field, with passivated surface or not, obeys the Universal Mobility Curves.

Intrinsic effective mobility extraction with extremely scaled gate dielectrics

We propose a mobility extraction methodology for metal-oxide-semiconductor field effect transistors with extremely scaled equivalent oxide thickness (EOT) below 1 nm. In conventional split C-V method, extracted mobility shows strong dependence on drain bias. As EOT scales to the requirements of 22 nm node and beyond, the phenomenon becomes more pronounced and causes bigger errors in mobility determination. We studied the physical origin of the extracted mobility dependence on drain bias by technology computer aided design electrostatics modeling and electrical characterization. A methodology is proposed and verified for intrinsic effective mobility determination for devices with EOT down to 0.6 nm.

Improved effective mobility extraction in MOSFETs

The standard method of extracting carrier effective mobility from electrical measurements on MOSFETs is reviewed and the assumptions implicit in this method are discussed. A novel technique is suggested that corrects for the difference in drain bias during IV and CV measurements. It is further shown that the lateral field and diffusion corrections, which are both commonly neglected, in fact cancel. The effectiveness of the proposed technique is demonstrated by application to data measured on a quasi-planar SOI finFET at 300 K and 4 K.

Phonon- and surface-roughness-limited mobility of gate-all-around 3C-SiC and Si nanowireFETs

We present numerical simulations of gate-all-around (GAA) 3C-SiC and Si nanowire (NW)field effect transistors (FETs) using a full quantum self-consistent Poisson–Schrödingeralgorithm within the non-equilibrium Green’s function (NEGF) formalism. A directcomparison between Si and 3C-SiC device performances sheds some light on the differenttransport properties of the two materials. Effective mobility extraction has been performedin a linear transport regime and both phonon- (PH) and surface-roughness-(SR) limitedmobility values were computed. 3C-SiC FETs present stronger acoustic phonon scattering,due to a larger deformation potential, resulting in lower phonon-limited mobility values.Although Si NW devices reveal a slightly better electrostatic control compared to 3C-SiCones, SR-limited mobility shows a slower degradation with increasing charge density for3C-SiC devices. This implies that the difference between Si and 3C-SiC device mobility isreduced at large gate voltages. 3C-SiC nanowires, besides their advantages compared tosilicon ones, present electrical transport properties that are comparable to the Sicase.

Application of Area-Saving RF Test Structure on Mobility Extraction

An RF test structure is proposed and its applicability is confirmed by measuring DC characteristics and high frequency characteristics. Effective mobility extraction is also performed to confirm the validity of proposed test structure. The area of suggested test structure consumed on wafer was decreased by more than 50% and its characteristics do not be degraded compared with conventional structure.

Carriers Mobility Extraction Methods for Triple-gate FinFET

This work presents a review of some mobility extraction methods for Triple-gate FinFET transistors. The methods are divided in two types: extraction of effective mobility, and separation of top and lateral mobility. Three-dimensional numerical simulations are performed to compare the methods. The results for effective mobility extraction show that all methods studied can be applied for Triple-gate FinFET devices with long channel length, higher than 910 nm which has an error lower than 10%. Among the method studied, the Faynot method presents lower error for shorter devices in the range from 910 nm down to 110 nm. The methods studied to extract the top and lateral mobilities show a good agreement with the expected mobility values, showing a maximum error of 11.3%, for the range of fin width of 50 nm to 9.87 µm. The Vikram method is a good option taking in consideration lower error than Daugé method and easier application than split C-V method.

Accurate effective mobility extraction by split C-V technique in SOI MOSFETs: suppression of the influence of floating-body effects

In this letter, we modify the split capacitance-voltage technique to exclude the influence of floating-body effects on the extracted mobility values and extend its applicability by using the integral of transconductance measured at high frequencies instead of dc drain current values. For the first time it is shown that such procedure allows not only to suppress parasitic gate-induced floating-body effect, which is an inevitable feature of advanced silicon-on-insulator MOSFETs, but also to improve the general accuracy of mobility extraction in moderate-to-strong inversion regime. We demonstrate the advantages of our modified technique over the conventional one by applying it to partially depleted silicon-on-insulator devices from a FinFET process.

A New Quantum Effect in Metal-Oxide-Semiconductor Field-Effect Transistor: Threshold Voltage Creep with Gate Voltage

We report a new quantum effect in metal-oxide-semiconductor field-effect transistor (MOSFET), namely that the two-dimensional (2-D) inversion charge falls substantially short of the classically predicted linear increase with gate voltage (VG) in strong inversion. This effect is to be effectively quantified via the threshold voltage (VTH) increasing with VG in the classical current–voltage (I–V) model and is called herein the threshold voltage creep (VTH-creep). In 0.18 µm MOSFET, for example, VTH-creep amounts to 58% of the VTH at the device turn-on point, when VG is swept from 0.5 to 2 V. Additionally, the VTH-creep significantly affects the extraction of effective mobility (µeff) from the I–V data. VTH-creep is shown a key to the accurate I–V modeling and constitutes one of the most clearly observed quantum phenomena in MOSFET.

Ionization radiation induced degradation of MOSFET channel frequency response

A model is presented for the frequency response degradation of metal-oxide-semiconductor field-effect transistors (MOSFETs) exposed to ionizing radiation. It is shown that response degradation can be predicted by monitoring a single parameter, the gate-to-channel time-constant tau /sub GC/, which is highly sensitive to the density of interface traps at the silicon-insulator interface. The value of tau /sub GC/ and its degradation with radiation dose are directly obtained by measuring the small signal impedance of a MOSFET. The measurement technique used enables the extraction of effective mobility of the inversion layer. Frequency response characteristics of two types of MOSFETs, fabricated using two different gate-insulator technologies and exposed to a total dose of 1 Mrad (Si), are compared.< <ETX xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">&gt;</ETX>