Extra Area Research Articles

A new radiation-hardened architecture for holographic memory address calculation

Architectures for the memory address calculation unit of a holographic memory device have been deeply analyzed in the literature. Finite-precision analysis and the selection of parameters to ensure a discrepancy between the hologram plane and the observation plane of less than 1% has been performed by other designers. However, a fault-tolerant architecture implemented on field-programmable gate array (FPGA) for an Optically Reconfigurable Gate Array has not been proposed yet. Due to the importance of this unit in environments with high levels of radiation, such as robots in nuclear disasters or satellites in space, which are the most common applications, there is a real interest in protecting this hardware. This work introduces two main contributions: i) replaces the calculation of distances through a Coordinate Rotation Digital Computer (CORDIC) unit in order to save area and ii) improves the ratio of fault-detection and extends the input range of the trigonometric computations to exploit more efficient error detection techniques. The derived architecture allows us to recover the FPGA from a faulty behavior in 95% of the cases, which avoids waiting for slower processes such as scrubbing. This real-time detection only requires an extra area of 13% with respect to the unprotected circuit and does not include any loss of precision compared to previous designs.

A novel membrane-promoted crystallization process integrating water recovery and salt production for brine management

Brine management is one of the global challenges nowadays. Herein, by taking advantage of capillary forces and low-grade heat (50 °C), we propose a novel ceramic membrane-promoted crystallization (MPC) process for brine management. The MPC process simplifies the traditional multiple energy-intensive steps and dispenses the use of expensive anticorrosive equipment via adopting three hierarchical layers (α-Al2O3 substrate, γ-Al2O3 interlayer, and SiO2 top layer). The hydrophilic mesoporous SiO2 top layer provides continuous driving force for brine solution transport from the inner shell of the membrane toward the outer surface, where heterogenous nucleation and secondary nucleation occur to form numerous long needle-like salt whiskers. The growth kinetics of salt whiskers accelerates with time as the formed salt whiskers provide extra evaporation area to intensify water evaporation. Template-directing molecules P123 significantly enhance the specific surface area, pore volume, pore size, and pore regularity of the SiO2 top layer, thereby promoting both water recovery and salt production. The optimized membrane displays high water recovery (790.3 g m−2) and salt production (194.6 g m−2) for high-salinity brine (20 wt%). Moreover, the MPC process demonstrates high performance, mechanical stability and thermal durability during the long-term test. It is expected that the MPC process would provide an innovative zero-liquid discharge approach for the efficient and low-cost brine management.

4-bit Carry Look Ahead Adder Using MGDI Technique

Abstract: Today's high-performance processor is built with arithmetic logic units that add and subtract key components. Design considerations related to low power and high performance digital VLSI circuits have become more prevalent in today's world. In order to develop low-power and high-performance processors, the designers need to design their adder circuits with the required speed and power dissipation for their applications. This topic introduces the concept of a adder using MGDI Technique. The Exact Speculative Carry Look Ahead Adder the use of the Modified-GDI (Modified-Gate Diffusion Input) is cautioned in this work. The delay, location and energy trade off performs a integral role in VLSI. We already comprehend that designs which are of CMOS fashion occupy extra area might also eat extra strength consumption. The switching conduct of the circuit reason the heating up of integrated circuits affects the working stipulations of the purposeful unit. The adders are the most important parts of countless applications such as microprocessors, microcontrollers and digital signal processors and additionally in actual time applications. Hence it is necessary to minimize the adder blocks to format a perfect processor. This work is proposed on a 16 bit carry seem to be in advance adder is designed through using MGDI gate and 4T XOR gates and a speculator blocks. The proposed MGDI raise Look Ahead adder occupies 68% much less region and the strength consumption and the propagation extend additionally considerably reduces when in contrast to the traditional carry Look Ahead adder why because the variety transistors extensively reduces from 1448 (Conventional) to 456 (Proposed CLA). The simulation consequences of the proposed format carried out in Xilinx. Keywords: Delay, power dissipation, voltage, transistor sizing.

Interwoven traditions in Bell Beaker metallurgy: Approaching the social value of copper at Bauma del Serrat del Pont (Northeast Iberia).

Debates on early metallurgy in Western Europe have frequently focused on the social value of copper (between utilitarian and symbolic) and its purported role in the emergence and consolidation of hierarchies. Recent research shows that generalisations are increasingly untenable and highlights the need for comparative regional studies. Given its location in an intermediate area, the early metallurgy of Northeast Iberia provides an interesting case in point to explore the interaction between the well-characterised traditions of southern Iberia and southern France during the 3rd and 2nd millennia BCE. Here the analytical study of seven Bell Beaker (decorated and undecorated) vessels reused as crucibles at Bauma del Serrrat del Pont (Tortellà, Girona) are presented. We employed pXRF, metallography, SEM-EDS and lead isotope analyses. The results show evidence for copper smelting employing a remarkable variety of ore sources, including Solana del Bepo, Turquesa and Les Ferreres mines, and an extra unknown area. The smelting vessels were manufactured using the same clay, which contained both mineral and organic inclusions. Our results are discussed with reference to all the evidence available for metals and metallurgy in the Northeast, and more broadly in comparison to southern Iberia and southern France, with special emphasis on issues of production organisation and social complexity. Taken together, our results support the notion that copper metallurgy played a predominantly utilitarian role in Bell Beaker societies and highlight idiosyncratic aspects of the metallurgical trajectory in the Northeast. Differences between territories challenge unilinear explanations of technological and social development after the introduction of metallurgy. Separate trajectories can only be explained in relation to area-specific socio-cultural and environmental factors.

Low mismatch high-speed charge pump for high bandwidth phase locked loops

This paper presents a low mismatch high-speed charge pump for high bandwidth phase locked loop (PLL). A novel mismatch compensation technique is used for reducing the current mismatch without having any extra area and power overhead. Proposed circuit is designed for 100 μA charge pump current (ICP) and it achieves less than 1% mismatch current across all process corners for an output voltage compliance range of 0.2–1 V. A prototype circuit of 1 GHz PLL is designed in 65 nm CMOS technology for testing the proposed charge pump. It achieves −81.2 dBc spur-level at reference frequency of 250 MHz. In locked condition of the PLL, proposed charge pump consumes 176 μW power from 1.2 V supply including the reference current. Area occupied by proposed design is 72 × 35 μm2.

A Reconfigurable Multiplier for Signed Multiplications with Asymmetric Bit-Widths

Multiplications have been commonly conducted in quantized CNNs, filters, and reconfigurable cores, and so on, which are widely deployed in mobile and embedded applications. Most multipliers are designed to perform multiplications with symmetric bit-widths, i.e., n - by n -bit multiplication. Such features would cause extra area overhead and performance loss when m - by n -bit multiplications ( m > n ) are deployed in the same hardware design, resulting in inefficient multiplication operations. It is highly desired and challenging to propose a reconfigurable multiplier design to accommodate operands with both symmetric and asymmetric bit-widths. In this work, we propose a reconfigurable approximate multiplier to support multiplications at various precisions, i.e., bit-widths. Unlike prior works of approximate adders assuming a uniform weight distribution with bit-wise independence, scenarios like a quantized CNN may have a centralized weight distribution and hence follow a Gaussian-like distribution with correlated adjacent bits. Thus, a new block-based approximate adder is also proposed as part of the multiplier to ensure energy-efficient operation with an awareness of the bit-wise correlation. Our experimental results show that the proposed approximate adder significantly reduces the error rate by 76% to 98% over a state-of-the-art approximate adder for Gaussian-like distribution scenarios. Evaluation results show that the proposed multiplier is 19% faster and 22% more power saving than a Xilinx multiplier IP at the same bit precision and achieves a 23.94-dB peak signal-to-noise ratio, which is comparable to the accurate one of 24.10 dB when deployed in a Gaussian filter for image processing tasks.

Attack Mitigation of Hardware Trojans for Thermal Sensing via Micro-ring Resonator in Optical NoCs

As an emerging role in new-generation on-chip communication, optical networks-on-chip (ONoCs) provide ultra-high bandwidth, low latency, and low power dissipation for data transfers. However, the thermo-optic effects of the photonic devices have a great impact on the operating performance and reliability of ONoCs, where the thermal-aware control with accurate measurements, e.g., thermal sensing, is typically applied to alleviate it. Besides, the temperature-sensitive ONoCs are prone to be attacked by the hardware Trojans (HTs) covertly embedded in the counterfeit integrated circuits (ICs) from the malicious third-party vendors, leading to performance degradation, denial-of-service (DoS), or even permanent damages. In this article, we focus on the tampering and snooping attacks during the thermal sensing via micro-ring resonator (MR) in ONoCs. Based on the provided workflow and attack model, a new structure of the anti-HT module is proposed to verify and protect the obtained data from the thermal sensor for attacks in its optical sampling and electronic transmission processes. In addition, we present the detection scheme based on the spiking neural networks (SNNs) to implement an accurate classification of the network security statuses for further high-level control. Evaluation results indicate that, with less than 1% extra area of a tile, our approach can significantly enhance the hardware security of thermal sensing for ONoC with trivial costs of up to 8.73%, 5.32%, and 6.14% in average latency, execution time, and energy consumption, respectively.

Via-Minimization-Oriented Region Routing Under Length-Matching Constraints in Rapid Single-Flux-Quantum Circuits

It is known that the pipelined architecture in a rapid single-flux-quantum (RSFQ) circuit can be constructed by inserting a set of path-balancing D-type flip-flops (DFFs) into some gate columns. Based on the assignment of the combined gates involving the splitters (SPLs) inside each gate column in the placement stage, the passive transmission line (PTL) region between two adjacent gate columns can be formed for a set of 2-pin connections in the routing stage. In this article, given a set of 2-pin connections with their length-matching constraints inside one PTL region, based on the concept of introducing a minimal set of vias in two available layers for single-flux-quantum (SFQ) pulse integrity, an efficient via-minimization-oriented routing algorithm can be proposed to minimize the routed width of one PTL region under length-matching constraint. By separating the wiring segments into sub-segments on some connections, the corresponding segments can be first assigned onto two available layers using a minimal set of vias. Furthermore, the introduced vias on the separated segments can be assigned onto feasible positions under the non-detouring and capacity constraints, and the monotonic river-routing process can be used to minimize the region width. Besides that, a set of flexible available areas can be constructed for the extension lengths on the given connections. Finally, one extra area can be accurately estimated and inserted for the extension lengths on the given connections and the zigzag detouring paths can be inserted into the available areas to satisfy the requirement of the extension lengths on the given connections. Compared with Kito's algorithm and Yan's algorithm in region routing under length-matching constraints, the experimental results show that our proposed routing algorithm can use reasonable CPU time to decrease 79.9% and 43.6% of the via number and 34.5% and 12.3% of the region width for 12 tested examples on average, respectively.

Multilayer toroidal tuned liquid column dampers for seismic vibration control of structures

The toroidal tuned liquid column damper (TTLCD) is a recently developed device, which extends the application scenarios of liquid column dampers to multidirectional vibration control. Based on the single-TTLCD, this article creatively designs a multilayer-TTLCD, composed of several cylinder shells and baffles, to improve the damping performance in multidirection. The real-time hybrid simulation (RTHS) technique is employed to experimentally investigate the control efficiency of the multilayer-TTLCD. It is confirmed that the multilayer configuration makes it possible to incorporate more oscillating liquid into the columns of the container without extra occupied floor area, and thus the liquid mass can be raised. Due to the increase of the liquid mass, the multilayer-TTLCD shows certain improvements on peak and root-mean-square (RMS) displacement mitigation over the single-TTLCD when suppressing one specific structural vibration mode. More importantly, it is found that the multilayer-TTLCD is beneficial in multimodal vibration damping and has potential to control multi-order modal responses of structures simultaneously with a wide frequency range.

Experimental and DFT studies on the effect of carbon nanoparticles on asphaltene precipitation and aggregation phenomena

• CNPs were synthesized for controlling asphaltene precipitation and aggregation. • FESEM and FTIR demonstrate uniform adsorption of asphaltene on surface of CNPs. • DFT modeling proves the strong hydrogen interaction between CNPs and asphaltenes. • CNPs represent biocompatible and affordable asphaltene inhibitor-dispersant. In this study, a new class of carbon nanoparticles (CNPs) is synthesized for inhibition/dispersion of asphaltene precipitation and aggregation in unstable crude oil. The microscopy and asphaltene dispersant experiments are carried out to assess the effects of CNPs on asphaltene precipitation and aggregation. Also, density functional theory is applied to describe the mechanisms of asphaltene adsorption onto the CNPs surfaces. Experimental results demonstrate postponement of asphaltene onset of precipitation from 26 to 37 vol% n-C 7 in the presence of 400 ppm of the CNPs which is ascribed to the extra high specific surface area of the CNPs. DLS analysis shows the average size of asphaltene aggregates adsorbed onto the CNPs reduces from 1730 nm in the blank oil to 255 nm in treated oil with CNPs. The results of DFT modeling demonstrate the strong hydrogen interaction between functional groups of the CNPs and active sites of asphaltene. Also, π–π interactions occur between electron cloud of aromatic rings of asphaltene and CNPs with minimum equilibrium distance of 2.94 Å. The adsorption energy for the most stable complex of asphaltene and CNPs in the gas and solvent phases are −91.22 and −107.64 kJ/mol, respectively, confirming the strong chemisorption of asphaltene over the CNPs. This research reveals that synthesized CNPs with specific features such as high surface area, potential of covering the external shell with a wide variety of functional groups, low toxicity and cost, and environment-friendly can be successfully implemented as an efficient inhibitor and/or dispersant for asphaltene handling strategies.

Corporate Social Responsibility and Firm Age: In Technology Sector

in this paper I explore the corporate social responsibility (CSR) performance within the information technology sector. And research the actual relationship between CRS and one of the firm’s critical characteristics—firm’s life circle. I test my hypothesis using a multiple variables regression analysis on a sample of 24,496 observations for 2610 firms over the period 1992-2016. I find that mature firms can have better CSR performance than young firms. Old firms are capable of generating higher income and paying back debt. Therefore, they tend to have more abilities to invest money in extra area, such as CSR. And I also check the research findings by adding lagged dependent variables. Although the association between the firm age and CSR score is weaker when involving more control variables in model, my results show there is a significant positive relationship between the level of maturity and CSR contribution.

Use of Cuckoo Search Algorithm for Performance Evaluation of Split Elliptic Shaped Fins for Enhanced Rate of Heat Transfer

Abstract Proper dissipation of thermal energy has always been a need for desirable efficiency of a system. Extended surface aids in releasing the heat to the immediate surrounding by inducing an extra area. This particular work assesses thermal and fluid flow behavior of extended surfaces with circular and elliptic shaped cross section. Extended surfaces of unvaried cross section are mounted over a square plate arrayed in a staggered manner. With the aid of different thermofluidic parameters, the elliptic shaped pin fin is established to provide a higher thermal performance enhancement of nearly 15% over cylindrical pin fin at inlet flow velocity of 2.35 m/s. Further, for elevating the interaction between the surface of the fin and the fluid, elliptic fins are reoriented to form a split. In contrast to cylindrical shaped fin, modification using split shows better result with the highest heat transfer increment of nearly 25%. Further, in order to maximize Nusselt number (Nu), a single objective cuckoo search optimization analysis is done by adopting the response surface method. After analyzing the optimization, it is found that the maximum value of Nu is obtained at dimensionless transverse offset (TO*) = 0.125 and dimensionless longitudinal offset (LO*) = 0, which has been further validated with the numerical result within 0.97% accuracy. Further, for the cylindrical fin, the present simulations agree with the available empirical correlation within 6.22% accuracy.

Design and concept proof of an inductive impulse self-destructor in sense-and-react countermeasure against physical attacks

This paper presents an inductive impulse self-destruction circuit utilized in a sense-and-react IC-level countermeasure against physical attacks on a cryptographic processor. Triggered upon an alarm signal assertion by an integrated attack sensor, the proposed circuit instantaneously generates >10 V high-voltage impulse to permanently destruct the cryptographic processor for enhancing tamper resiliency. A compact design with only a single on-chip inductor and a transistor significantly saves the hardware overhead. The inductor accumulates large electric energy in its magnetic field and the switch transistor suddenly opens the accumulated energy to boost the impulse voltage in an inertial manner. Since the inductor is drawn over the cryptographic core by existing on-chip IC interconnections, no extra area for the inductor and no any optional IC process steps are needed. This fully standard CMOS compatible, complete circuit solution, results in no fabrication cost penalty. A prototype implemented in both discrete components and a 0.18 μm standard CMOS process successfully demonstrated the-proof-of-concept.

Hardware–Software Co-Design for Decimal Multiplication

Decimal arithmetic using software is slow for very large-scale applications. On the other hand, when hardware is employed, extra area overhead is required. A balanced strategy can overcome both issues. Our proposed methods are compliant with the IEEE 754-2008 standard for decimal floating-point arithmetic and combinations of software and hardware. In our methods, software with some area-efficient decimal component (hardware) is used to design the multiplication process. Analysis in a RISC-V-based integrated co-design evaluation framework reveals that the proposed methods provide several Pareto points for decimal multiplication solutions. The total execution process is sped up by 1.43× to 2.37× compared with a full software solution. In addition, 7–97% less hardware is required compared with an area-efficient full hardware solution.

Pediatric autoimmune encephalitis associated with anti-glutamic acid decarboxylase 65 antibody: two cases report and literature review

Objective: To investigate the clinical features and prognosis of pediatric autoimmune encephalitis associated with anti-glutamic acid decarboxylase 65 (GAD65) antibody. Methods: Clinical data of 2 patients diagnosed as autoimmune encephalitis associated with anti-GAD65 antibody at Department of Neurology, Beijing Children's Hospital in 2019 were analyzed retrospectively. A literature search with "anti-GAD65 antibody""encephalitis""epilepsy" or "cerebellar ataxia" as key words was conducted at China National Knowledge Infrastructure, Wanfang Data Knowledge Service Platform and PubMed (up to January 2020). The clinical features and prognosis of pediatric cases with complete clinical data were retrieved and summarized. Results: Two patients with positive anti-GAD65 antibody of serum and cerebrospinal fluid were both females. The onset age of case 1 was 57 months and her main clinical manifestations were fever and unconsciousness. The cranial magnetic resonance imaging (MRI) showed diffuse T2 weighted imaging (T2WI) abnormal signals, and the electroencephalogram (EEG) showed slow waves. The onset age of case 2 was 80 months and her main clinical manifestations of were recurrent focal seizures, memory loss, and headache. The MRI showed high T2WI signal in bilateral hippocampus, and the EEG showed abnormal discharge involving the temporal area. Both cases were treated with methylprednisolone and intravenous immunoglobulin, the short-term symptoms of them were both improved. They were followed up for 6 months and 1 year respectively, the case 1 recovered completely, and the case 2 still had focal seizures. Six English reports which included 6 cases were retrieved. Together with these 2 cases, a total of 8 cases were analyzed. The clinical symptoms included seizures (6 cases), memory loss (4 cases), loss of consciousness (3 cases), behavioral abnormalities (3 cases), cognitive impairment (2 cases), headache (2 cases), autonomic symptoms (1 case), ataxia (1 case), dysphagia (1 case), and aphasia (1 case). There were 5 cases with cranial MRI abnormalities in the acute phase or sub-acute phase, of whom 3 cases had the limbic system involvement, and 2 cases were mainly had extra limbic area involvement. Three cases had hippocampal atrophy or sclerosis during follow-up. All 8 patients were treated with immunotherapy. After immunotherapy, all patients had short-term improvement. Follow-up for 6 months to 6 years showed that 3 cases with extra limbic encephalitis improved to baseline levels, and 5 limbic encephalitis cases had poor outcomes, including 1 death and 4 cases still had focal epilepsy. Conclusions: Pediatric anti-GAD65 antibody associated autoimmune encephalitis is a rare but treatable disease, including limbic encephalitis and extra limbic encephalitis. The most common clinical manifestations are seizures and memory impairment. Early diagnosis and immunotherapy can improve the symptoms in a short time. But patients with limbic encephalitis often had refractory epilepsy in the chronic phase, and have a poor long-term outcome.

ASIC Implementation of Low PAPR Multidevice Variable-Rate Architecture for IEEE 802.11ah

The advancement of next-generation systems has led to a rapid increase in day-to-day applications by connecting billions of devices. Mobile networks require a considerable cost to support these billions of devices, and conventional IEEE 802.11 is meant for the usage of small-scale applications. To support long-range applications, IEEE task group-ah has proposed a new standard named IEEE 802.11ah. However, it has challenges like efficient device grouping based on variable sampling rates and power consumption. This standard employs orthogonal frequency-division multiplexing as a multicarrier scheme that suffers from high peak-to-average power ratio (PAPR). Hence, to support multiple devices of variable rates in the physical layer along with low PAPR and acceptable bit error rate, a new framework and an optimized architecture of carrier interferometry-group orthogonal–orthogonal frequency-division multiple access architecture is proposed. The proposed architecture reduces the 16-point inverse fast Fourier transform area by 57.1%, device padding area by 50% along with three extra adders functional area compared with the existing architecture. Furthermore, the proposed architecture is prototyped on Virtex5 field-programmable gate array for on-chip validation, and the hardware parameters are measured in real time. The area-timing complexity of the proposed architecture is estimated and further achieves the lowest area- and power-delay product than the existing architecture. Application-specific integrated circuit implementation is carried out using commercially available 32 - nm technology library, where the postlayout results reported less area utilization and low power consumption.

Buffer Sizing for Multimedia Flows in Packet-Switching NoCs

Wormhole packet switching, used in many NoC designs, introduces jitter. This may produce violations of application deadlines. Several works in the literature propose stream workload models, and techniques for buffer sizing. These works do not consider the concurrency between different flows, or the NoC model is too abstract, masking the jitter introduced by data packaging and router processing. One technique to deal with jitter is to introduce a decoupling buffer (D-buffer) on the target IP. This buffer receives data from the NoC with jitter, while the target IP consumes data from this buffer at the application rate, without jitter. Two problems must be solved to implement D-buffers: (i) which size must the buffer have? (ii) how much time should be expected before data consumption starts (threshold)? This work proposes a general method to define D-buffer size and threshold, considering the influence of packaging, arbitration, routing and concurrency between flows. A traffic model for stream applications is detailed and used to characterize jitter sources in wormhole packet switching. Experimental results demonstrate the impact on multimedia flows with fixed and variable packet sizes (from real traffic traces). Simple traffic models employing constant frame sizes result in small D-buffers. On the other hand, employing multimedia frames from application traces (i.e. real application data) increases buffer size and threshold while still suppressing jitter. Another parameter analyzed in the paper is the percentage of deadline violations as a function of D-buffer size. The method guarantees throughput with no deadline violation and does not modify the NoC structure. The cost of adding such D-buffers is an increased latency and extra silicon area.

Compact Millimeter-Wave Endfire Dual-Polarized Antenna Array for Low-Cost Multibeam Applications

A compact multibeam endfire dual-polarized antenna array for low-cost millimeter-wave (mmWave) applications is proposed in this letter. Multimode substrate-integrated waveguide (SIW) section with interactions is applied as the basic beamformer. The dual-mode SIW is used in the beamforming network to support dual-polarization application without occupying an extra area. The printed dipole antenna with integrated balun and the open-ended SIW antenna with metallic strips are integrated to realize an endfire dual-polarized antenna element. Based on this endfire antenna element, a multibeam dual-polarized antenna array is developed. The proposed antenna array includes a four-element antenna array, an SIW beamforming network, and transitions. Additional air gaps between antenna elements are designed for mutual coupling reduction. The fabricated multibeam endfire dual-polarized antenna array achieves an impedance bandwidth of 11.3%, and the overlapped 3 dB beamwidth of the four generated beams in two polarizations are able to cover a wide range between ± 41°. The proposed low-cost multibeam antenna array can be a good candidate for 5G mmWave wireless applications.

Decoding Algorithm for Quadruple-Error-Correcting Reed-Solomon Codes and Its Derived Architectures

This brief introduces a new method to compute in parallel the roots of a polynomial locator of degree four in a Reed-Solomon decoder. The novelty of this brief is the introduction of an algorithm that transforms the polynomial locator obtained with the Peterson-Gorenstein-Zierler's algorithm into an equivalent one that allows a direct search for the four roots that indicate the location of the symbols in error. This new solution improves a previous approach proposed in the literature for a quadruple-error-correction decoder (QEC) that requires a cubic aid equation. This previous solution does not work in the cases in which the cubic aid does not have a solution. In contrast, the proposal of this brief works in 100% of cases (with t ≤ 4) as it solves an equivalent polynomial. This new algorithm allows two different implementations: a fully parallel architecture which provides an extremely low latency at an extra area cost, and a fully serial architecture with less area, but a higher latency.

Adsorption of brilliant green dye from aqueous solution onto chemically modified areca nut husk

Areca nut husk, an inexpensive, easily available agricultural by-product modified with sodium hydroxide has been applied to remove Brilliant green (BG) dye from aqueous solution. Surface characteristics and the elemental composition of areca nut husks were examined using Scanning electron microscope (SEM) and Energy dispersive X-ray (EDX). The chemical treatment changes the surface morphology of the areca nut husk. The alkali treatment removes natural wax, resins and lignin from husks and thus it added extra active surface area and pores for better adsorption. The Fourier-transform infrared (FTIR) spectroscopy indicated that the presence of functional groups (-OH), (-C=O), (-C=C), (-COOH). Experiments were performed in batch adsorption procedure. The optimum removal of 97% BG dye was obtained at pH 7.0, adsorbent dosage 10 g/L, initial concentration 100 mg/L, agitation speed 200 rpm and temperature 298 K. Adsorption data fit better to Langmuir model in comparison with Freundlich, Temkin and Dubinin-Radushkevich isotherm model. The maximum adsorption capacity of 18.21 mg/g was obtained. Kinetic date followed pseudo-second-order rate kinetic better than pseudo-first-order model. The thermodynamic parameters ΔH0 = 12.522 kJ/mol and ΔS0 = 0.044 J/mol indicate endothermic and spontaneous adsorption process. Taking considerations of all experimental results and model analysis, it is concluded that sodium hydroxide treated areca nut husk is a good, low cost and effective biosorbent for the removal of BG dye from aqueous solution.