External Memory Interface Research Articles

A High Performance Dual Stage Face Detection Algorithm Implementation using FPGA Chip and DSP Processor

A dual stage system architecture for face detection based on skin tone detection and Viola and Jones face detection structure is presented in this paper. The proposed architecture able to track down human faces in the image with high accuracy within time constrain. A non-linear transformation technique is introduced in the first stage to reduce the false alarms in second stage. Moreover, in the second stage pipe line technique is used to improve overall throughput of the system. The proposed system design is based on Xil¬inx’s Virtex FPGA chip and Texas Instruments DSP processor. The dual port BRAM memory in FPGA chip and EMIF (External Memory Interface) of DSP processor are used as interface between FPGA and DSP processor. The proposed system exploits advantages of both the computational elements (FPGA and DSP) and the system level pipelining to achieve real time perform¬ance. The present system implementation focuses on high accurate and high speed face detec¬tion and this system evaluated using standard BAO image database, which include images with different poses, orientations, occlusions and illumination. The proposed system attained 16.53 FPS frame rate for the input image spatial resolution of 640X480, which is 23.4 times faster detection of faces compared to MATLAB implementation and 12.14 times faster than DSP implementation and 2.1 times faster than FPGA implementation.

Total Ionizing Dose Effect and Failure Mechanism of Digital Signal Processor

Ionizing radiation effect and failure mechanism of Digital signal processor (DSP) is studied through test-board and automatic test equipment to find the relationship between system function failure and parameter degradation. Static bias is more sensitive than dynamic bias when DSP is tested on-line during radiation. Core current, high-Z leakage current and timing parameter are sensitive to ionizing radiation. No enhanced low-dose-rate sensitivity is found by comparing experiment results under high and low dose rate radiation. External memory interface and Timer are deduced to be the sensitive module by step radiation and analysis basing full parameter test in Verigy 93000. The timing parameter degradation have a strong correlation to these module functions. And the degeneration mechanism is analysed on inverter through Hspice simulation which indicate the leakage circuit caused by radiation can lead a delay to the digital signal propagating. The parasitical capacitance among long connections make it worse to the data transmission around DSP, field programmable gate array and memory. Then an early function failure occurs in test board than Verigy 93000. This work provide support to systematic radiation hardness design and hardness assurance/lot acceptance testing in space applications.

SHyLoC 2.0: A Versatile Hardware Solution for On-Board Data and Hyperspectral Image Compression on Future Space Missions

In this paper, we present the design, implementation and results of a set of IP cores that perform on-board hyperspectral image compression according to the CCSDS 123.0-B-1 lossless standard, specifically designed to be suited for on-board systems and for any kind of hyperspectral sensor. As entropy coder, the sample-adaptive entropy coder defined in the 123.0-B-1 standard or the low-complexity block-adaptive encoder defined by the CCSDS 121.0-B-2 lossless standard could be used. Both IPs, 123.0-B-1 and 121.0-B-2, are part of SHyLoC 2.0, and can be used together for compression of hyperspectral images, being also possible the compression of any kind of data using only the 121-IP. SHyLoC 2.0 improves and extends the capabilities of SHyLoC 1.0, currently available at the ESA IP Cores library, increasing its compression efficiency and throughput, without compromising the resources footprint. Moreover, it incorporates new features, such as the unit-delay predictor option defined by the CCSDS 121.0-B-2 standard, and burst capabilities in the external memory interface of the CCSDS 123-IP, among others. Dedicated architectures have been designed for all the possible input image sample arrangements, in order to maximise throughput and reduce the hardware resources utilization. The design is technology-agnostic, enabling the mapping of the VHDL code in different FPGAs or ASICs. Results are presented for a representative group of well-known space-qualified FPGAs, including the new NanoXplore BRAVE family. A maximum throughput of 150 MSamples/s is obtained for Xilinx Virtex XQR5VFX130 when the SHyLoC 2.0 CCSDS-123 IP is configured in Band-Interleaved by Pixel (BIP) order, using only the 4% of LUTs and less than the 1% of internal memory.

Real-time Frame Buffer Implementation based on External Memory using FPGA

In this paper, design of a real-time video frame buffer with an external memory interface is proposed. In addition, simulation and implementation processes of the design is described. The mentioned system is able to buffer video signals up to 1920×1080 full-HD resolution at 60 Hz frame rate. The memory interface is designed based on an external SDRAM memory and supports burst read/write operations. Input video resolution, video buffer size on memory and burst size of the memory interface are user defined and can be configured.

Real-Time FPGA-Based Object Tracker with Automatic Pan-Tilt Features for Smart Video Surveillance Systems

The design of smart video surveillance systems is an active research field among the computer vision community because of their ability to perform automatic scene analysis by selecting and tracking the objects of interest. In this paper, we present the design and implementation of an FPGA-based standalone working prototype system for real-time tracking of an object of interest in live video streams for such systems. In addition to real-time tracking of the object of interest, the implemented system is also capable of providing purposive automatic camera movement (pan-tilt) in the direction determined by movement of the tracked object. The complete system, including camera interface, DDR2 external memory interface controller, designed object tracking VLSI architecture, camera movement controller and display interface, has been implemented on the Xilinx ML510 (Virtex-5 FX130T) FPGA Board. Our proposed, designed and implemented system robustly tracks the target object present in the scene in real time for standard PAL (720 × 576) resolution color video and automatically controls camera movement in the direction determined by the movement of the tracked object.

Using NI PXI Modules for Digital Signal Processing Microprocessor Testing

The article considers the implementation of the external memory interface based on National Instruments modular PXI equipment for environmental testing of digital signal processing (DSP) microprocessors. The block diagram of the developed device pointing out the advantages and disadvantages of this solution is provided. The block diagram of an improved external memory interface is also shown.

External Memory Interface Verification Based on VMM

With the growth of the scale of SoC, function verification becomes more and more complicated. Traditional functional verification method is confronted with some challenges. This paper achieves coverage-driven, constrained-randomization and assertion verification methodology based on SystemVerilog and VMM, to build verification platform by taking example of EMI (external memory interface). As result of verification, we can monitor coverage, control the platform, optimize testbench and testcase, finish function coverage 100%. These applications can simplify complex function verification, improve the platform reuse, and meet the needs of chip verification.

Low-Cost, 3-Dimension, Office-Based Inertial Sensors for Automated Tremor Assessment: Technical Development and Experimental Verification

Tremors are common clinical complaints among the elderly and non-specialist physicians frequently are challenged by the need to provide an accurate diagnosis of various tremor syndromes, particularly Parkinson's disease and essential tremor in their busy practices. We sought to develop an easy-to-use, mobile robust, accurate, and cost-effective instrument that can objectively quantify tremors. The low-cost, 3-dimension, inertial sensors were developed for automated tremor assessment. The main sensor unit consists of a 3-axis accelerometer and a 3-axis gyroscope for the purpose of measuring the tilting angle relative to the gravity, linear acceleration, and angular velocity of the body segments affected by tremors. The transmitter consists of five main modules, including a microcontroller, power management module, sensor module, external memory interface module, and Bluetooth™ communication interface module, which connects to the sensors by a thin wire. The signal processing utilized fast Fourier transform analysis to include RMS angular rate, RMS angle, RMS rate, RMS velocity, peak frequency, peak frequency magnitude, and dispersion of frequency as variables. The prototype was tested with a tremor simulator at programmable angular rates of 2-, 4-, and 8-Hz confirming its accuracy. Twenty subjects (10 PD and 10 age-matched ET patients) participated as part of the experimental verification to perform three tremor tasks, including rest, postural, and kinetic tremor according to the teaching videotape of the motor section of the UPDRS. The mean peak frequency was significantly lower in PD than ET patients at rest on the x- (p < 0.01) and z-axis (p < 0.01). In PD patients, the RMS angular rate, RMS angle, RMS rate, RMS velocity, and peak magnitude were all significantly higher than those values in ET patient at rest while the data was not significantly difference during postural and kinetic actions. ET patients had significantly higher peak frequency during postural action in the y-axis than PD patients (p < 0.05). The study provides the technical development of an accurate, inexpensive, and simple method to measure the kinematics of tremor in humans. Further studies are warranted to confirm the validity of each parameter and the diagnostic accuracy in each tremor syndrome.

Design and implementation of high-speed sampling buffer system based on FPGA

An embedded general-purpose hardware structure based on FPGA + DSP was proposed in order to improve the real-time performance of the high-speed data acquisition system.In the structure,a new high speed sampling buffer as the data channel between the high-speed A/D and DSP was designed in FPGA and was used to realize the diversion and deceleration of high-speed data stream.The high-speed sampling buffer was based on the ping-pong operation structure of soft-core dual-clock First In First Out(FIFO) provided by Quartus Ⅱ 9.0.Under the control of the External Memory Interface A(EMIFA) interface of the DSP,it completed write-and-read operations of high-speed A/D data streams.The test results indicate that: in the case of large difference between the value of the read-and-write clock,high speed sampling buffer can save the time of the A/D sampling data to provide sufficient signal processing time for DSP,so the real-time performance of the entire system is improved.

FPGA-based reconfigurable processor for ultrafast interlaced ultrasound and photoacoustic imaging

In this paper, we report, to the best of our knowledge, a unique field-programmable gate array (FPGA)-based reconfigurable processor for real-time interlaced co-registered ultrasound and photoacoustic imaging and its application in imaging tumor dynamic response. The FPGA is used to control, acquire, store, delay-and-sum, and transfer the data for real-time co-registered imaging. The FPGA controls the ultrasound transmission and ultrasound and photoacoustic data acquisition process of a customized 16-channel module that contains all of the necessary analog and digital circuits. The 16-channel module is one of multiple modules plugged into a motherboard; their beamformed outputs are made available for a digital signal processor (DSP) to access using an external memory interface (EMIF). The FPGA performs a key role through ultrafast reconfiguration and adaptation of its structure to allow real-time switching between the two imaging modes, including transmission control, laser synchronization, internal memory structure, beamforming, and EMIF structure and memory size. It performs another role by parallel accessing of internal memories and multi-thread processing to reduce the transfer of data and the processing load on the DSP. Furthermore, because the laser will be pulsing even during ultrasound pulse-echo acquisition, the FPGA ensures that the laser pulses are far enough from the pulse-echo acquisitions by appropriate time-division multiplexing (TDM). A co-registered ultrasound and photoacoustic imaging system consisting of four FPGA modules (64-channels) is constructed, and its performance is demonstrated using phantom targets and in vivo mouse tumor models.

Analytical synthesis of bandwidth-efficient SDRAM address generators

SDRAM memories are a commodity technology which deliver fast, cheap and high capacity external memory in many cost-sensitive embedded applications. When designing with SDRAM memory, the memory bandwidth available is strongly dependent on the sequence of addresses requested. For applications with hard real-time performance requirements, it is prudent to perform at compile time, some form of analysis to guarantee those hard real-time deadlines are met. In general with SDRAM memories, this analysis is difficult, and this leads to conservative implementations. On-chip memory buffers can make possible data reuse and request reordering which together ensure bandwidth on an SDRAM interface is used efficiently. This paper outlines an automated procedure for synthesizing application-specific address generators which exploit data-reuse in on-chip memory and transaction reordering on an external memory interface. We quantify the impact this has on memory bandwidth over a range of representative benchmarks. Across a range of parameterized designs, we observe up to 50× reduction in the quantity of data fetched from external memory. This, combined with reordering of the transactions, allows up to 128× reduction in the memory access time of certain memory-intensive benchmarks implemented in an FPGA. Since the synthesis procedure results in monotonic memory addressing functions, we can extract tight worst-case execution (WCET) bounds that are useful in system analysis. We show that we can extract performance guarantees which are significantly tighter than the absolute worst-case SDRAM performance.

A Reconfigurable Heterogeneous Multimedia Processor for IC-Stacking on Si-Interposer

This paper presents a heterogeneous multimedia processor for embedded media applications such as image processing, vision, 3-D graphics and augmented reality (AR), assuming integrated circuit (IC)-stacking on Si-interposer. This processor embeds reconfigurable output drivers for external memory interface to increase memory bandwidth even in a mobile environment. The implemented output driver reconfigures its driving strength according to channel loss between the implemented processor and the memory, so it enables highspeed data communication while achieving 8× higher memory bandwidth compared to previous embedded media processors. The implemented processor includes three main programmable intellectual properties, mode-configurable vector processing units (MCVPUs), a unified filtering unit (UFU), and a unified shader. MCVPUs have 32 integer (16 bit) cores in order to support dual-mode operations between image-level processing and graphics processing. This mode-configuration enables a frame-level pipelining in AR application, so the proposed processor achieves 1.7× higher frame rate compared to the sequential AR processing. UFU supports 16 types of filtering operations only with a single instruction. Most image-level processing consists of various types of filtering operations, so UFU can improve media processing performance and energy-efficiency. UFU also supports texture filtering which is performance bottleneck of common graphics pipeline. A memory-access-efficient (off-chip memory) texturing algorithm named as an adaptive block selection is proposed to enhance texturing performance in 3-D graphics pipeline. UFU has two-level on-chip memory hierarchies, a 512B level-0 (L0) data buffer, and an 8kB level-1 (L1) static random-access memory (SRAM) cache. The small-sized L0 data buffer limits direct references to the large-sized L1 SRAM cache to reduce energy consumed in on-chip memories. Unified shader consists of four homogeneous scalar processing elements (SPEs) for geometry operations in 3-D graphics. Each SPE has single-precision floating-point data-paths, since precision of geometry operations in 3-D graphics is important in today's handheld devices (high resolution). The proposed media processor is fabricated in 0.13 μm CMOS technology with 4 mm × 4 mm chip size, and dissipates 275 mW for full AR operation.

移动便携图像存储系统的设计

In order to meet the requirement of miniaturization and portability of the image storage system for camera based on Camera Link interface,the hardware circuit was designed with a Virtex4 family Field Programming Gate Array(FPGA) from Xilinx company and a 6000 series Digital Signal Processor(DSP) from TI Company.First,under the control of FPGA,image data from Camera Link were cached in a SDRAM;at the same time,the image data which read from the other SDRAM were stored in other solid-state hard disks by ping-pang operation.Then the host computer connected with DSP through Fast Ethernet,under the control of the host computer,DSP acquired image data through External Memory Interface(EMIF) and sent it to host computer to realize real-time display or image playback function.The system that based on the scheme stored image successfully,past by the experiment in 640×480,100 f/s,10 bit monochrome.When the real-time display function is not needed,the designed system could accomplish image storage independently to meet the Base Camera Link type Camera portable storage requirements.

A digital audio signal processor for sound field controls

A new digital audio signal processor (DASP) that is suitable for sound field control applications has been developed. An adaptable external memory configuration method is introduced. The device includes a 32-bit arithmetic and logic unit (ALU) and a 32* 24 bit multiplier/accumulator. The processor is designed to optimize sound field controls such as sound field reproduction of concert halls in a listening room or sound position selection to create natural stereo sounds in an automobile. The programmable external memory interface allows various configurations of DRAM to be selected. The DASP with the external memory interface allows implementation of sound field control, equalization, and filtering applications on a single chip. This reduces overall system costs and periods of system development.< <ETX xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">&gt;</ETX>

A digital signal processor for digital audio use

The authors describe the D/sup 2/SP digital signal processor which is designed with a dual processor architecture, and is especially effective for stereo audio signal processing. The D/sup 2/SP has two independent processor units, the left processor and right processor. The D/sup 2/SP contains an audio data interface, external dynamic random-access memory (DRAM) interface, microcomputer interface, and a sequence controller. The single chip D/sup 2/SP is capable of performing audio signal processing needed for graphic equalizers, surround, and sound power spectrum calculation. The dual processor mainly consists of a 24-bit multiplier with a 108-ns cycle time and is assembled on a single chip fabricated from 1.2- mu m CMOS technology. The total number of integrated transistors is approximately 300 K. Applications, such as use as a seven-band graphic equalizer, seven-band power spectrum calculator, and surround sound processing, are briefly discussed. >