Abstract

In this paper, we present the design, implementation and results of a set of IP cores that perform on-board hyperspectral image compression according to the CCSDS 123.0-B-1 lossless standard, specifically designed to be suited for on-board systems and for any kind of hyperspectral sensor. As entropy coder, the sample-adaptive entropy coder defined in the 123.0-B-1 standard or the low-complexity block-adaptive encoder defined by the CCSDS 121.0-B-2 lossless standard could be used. Both IPs, 123.0-B-1 and 121.0-B-2, are part of SHyLoC 2.0, and can be used together for compression of hyperspectral images, being also possible the compression of any kind of data using only the 121-IP. SHyLoC 2.0 improves and extends the capabilities of SHyLoC 1.0, currently available at the ESA IP Cores library, increasing its compression efficiency and throughput, without compromising the resources footprint. Moreover, it incorporates new features, such as the unit-delay predictor option defined by the CCSDS 121.0-B-2 standard, and burst capabilities in the external memory interface of the CCSDS 123-IP, among others. Dedicated architectures have been designed for all the possible input image sample arrangements, in order to maximise throughput and reduce the hardware resources utilization. The design is technology-agnostic, enabling the mapping of the VHDL code in different FPGAs or ASICs. Results are presented for a representative group of well-known space-qualified FPGAs, including the new NanoXplore BRAVE family. A maximum throughput of 150 MSamples/s is obtained for Xilinx Virtex XQR5VFX130 when the SHyLoC 2.0 CCSDS-123 IP is configured in Band-Interleaved by Pixel (BIP) order, using only the 4% of LUTs and less than the 1% of internal memory.

Highlights

  • Nowadays, high-resolution hyperspectral imaging sensors are becoming more common in Earth Observation (EO) satellite missions due to their multiple applications for identification, surveillance and navigation purposes, among others

  • The Multispectral Instrument (MSI) on-board Sentinel-2 supported by ESA, the Hyperion imaging spectrometer integrated in the EO-1 NASA satellite or PRISMA, The associate editor coordinating the review of this manuscript and approving it for publication was Remigiusz Wisniewskis

  • For the Big Reprogrammable Array for Versatile Environments (BRAVE) Field-Programmable Gate Arrays (FPGAs) family, the NG-LARGE device is selected as implementation target for the CCSDS123-IP, since it provides enough resources to map the IP in most configurations, including the most complex ones, that can be too demanding for smaller devices such as the NG-MEDIUM

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Summary

Introduction

High-resolution hyperspectral imaging sensors are becoming more common in Earth Observation (EO) satellite missions due to their multiple applications for identification, surveillance and navigation purposes, among others. The input samples are received through an ad-hoc parallel interface, designed with the purpose of connecting the module with an external pre-processing stage when its unit-delay predictor is not included (this is controlled with the parameter PREPROCESSOR_GEN different from 2), performing only the encoding step.

Results
Conclusion
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