Design and implementation of high-speed sampling buffer system based on FPGA

Abstract

An embedded general-purpose hardware structure based on FPGA + DSP was proposed in order to improve the real-time performance of the high-speed data acquisition system.In the structure,a new high speed sampling buffer as the data channel between the high-speed A/D and DSP was designed in FPGA and was used to realize the diversion and deceleration of high-speed data stream.The high-speed sampling buffer was based on the ping-pong operation structure of soft-core dual-clock First In First Out(FIFO) provided by Quartus Ⅱ 9.0.Under the control of the External Memory Interface A(EMIFA) interface of the DSP,it completed write-and-read operations of high-speed A/D data streams.The test results indicate that: in the case of large difference between the value of the read-and-write clock,high speed sampling buffer can save the time of the A/D sampling data to provide sufficient signal processing time for DSP,so the real-time performance of the entire system is improved.