Abstract
The paper presents an efficient first in first out (FIFO) buffer for use in network on chip routers for efficient management of data flow. Further we have designed a heterogeneous router using the efficient FIFO buffer, in which each channel can have a different buffer size. Even the FIFO of a particular channel is full it can borrow more buffer length from neighbouring channels. In this new architecture read and write operations are managed by the FIFO and channel itself, thus reducing the circuitry and making it a high speed router.
Talk to us
Join us for a 30 min session where you can share your feedback and ask us any queries you have
Schedule a callDisclaimer: All third-party content on this website/platform is and will remain the property of their respective owners and is provided on "as is" basis without any warranties, express or implied. Use of third-party content does not indicate any affiliation, sponsorship with or endorsement by them. Any references to third-party content is to identify the corresponding services and shall be considered fair use under The CopyrightLaw.
