Abstract
To meet the complex requirements of the miniature embedded integrated (INS/GPS) navigation system based on DSP, all peripheral circuits were integrated in single chip of FPGA, such as logic control module, serial/parallel data conversion and FIFO(First In First Out), etc. The multi-channel UART(Universal Asynchronous Receiver Transmitter) consists of the data conversion circuit and FIFO. In addition, the ping-pong buffer storages were assigned in the internal RAM of DSP so that EDMA controller of DSP could transmit data between the FIFOs of UART and the ping-pong buffer storages without CPU intervention. All methods above could relieve the redundant overhead of CPU on data transmission. The test results indicate that the scheme makes multi-channel UART operate at 460.8 kbps steadily by control of EDMA when CPU processes data at the same time. In this way, the real-time performance and reliability of the system can be enhanced effectively and CPU can be devoted to navigation algorithms and Kalman filtering.
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