External Clock Research Articles

A new PPP one-way timing approach via BDS-3 PPP-B2b and short-message communication service

In the realm of time-frequency, precise point positioning (PPP) technology has been widely used, the current PPP time transfer or timing necessitates network communication for data transmission, which consequently leads to a reduction in the reliability of PPP timing. Based on the BDS-3 PPP service (PPP-B2b) and the global short message communication (GSMC) service, this study proposes a novel PPP one-way timing method that is not subject to distance limitations or the requirements of network communication. Users can directly obtain the difference with UTC(k). Then, the proposed PPP timing method was validated using four stations equipped with external high-performance atomic clocks, based on a dataset of eight days. According to the findings, the suggested PPP one-way timing technique might reach a timing accuracy of roughly 0.5 ns in environments without a network. In terms of frequency stability, the proposed PPP timing method exhibits a stability of approximately 1.4 × 10−13 at 960 s and a stability of about 3 × 10−14 at 15360 s. Further, even under GSMC communication delays of 1 min, 5 min, and 10 min, the proposed PPP one-way timing accuracy can still achieve better than 0.5 ns.

A Standard-Cell-Based Neuro-Inspired Integrate-and-Fire Analog-to-Time Converter for Biological and Low-Frequency Signals - Comparison With Analog Version.

Continuous-time asynchronous data converters namely, analog-to-digital converters and analog-to-time converters, can be beneficial for certain types of applications, such as, processing of biological signals with sparse information. A particular case of these converters is the integrate-and-fire converter (IFC) that is inspired by the neural system. If it is possible to develop a standard-cell-based (SCB) IFC circuit to perform well in advanced technology nodes, it will benefit from the simplicity of SCB circuit designs and can be implemented in widely available field-programmable gate arrays (FPGAs). This way, this paper proposes two IFC circuits designed and prototyped in a 130 nm CMOS standard process. The first is a novel SCB open-loop dynamic IFC. The latter, is a closed-loop analog IFC with conventional blocks. This paper presents a through comparison between the two IFC circuits. They have a power dissipation of 59 μW and 53 μW, and an energy per pulse of 18 pJ and 1060 pJ, SCB and analog IFC, respectively. The SCB IFC has one of the lowest energy per pulse consumption reported for IFC circuits. The analog IFC, being fully differential, is to our knowledge the first of its kind. Moreover, they do not require an external clock. They can convert signals with a peak-to-peak amplitude from 1.6 mV to 28 mV and 0.6 mV to 2.4 mV, and a frequency range of 2 Hz to 42 kHz and 10 Hz to 4 kHz, SCB and analog IFC, respectively. Presenting low normalized RMS conversion plus reconstruction errors, below 5.2%. The maximum pulse density (average firing-rate) is 3300 kHz, for the SCB and 50 kHz, for the analog IFC.

Research on the synchronization technology of external clock based on gps timing

Research on the synchronization technology of external clock based on gps timing

New insights into the relationship between clock genes and ascorbic acid metabolism in spinach during pre- and postharvest periods

In this study, the effects of light and dark conditions on the expression of candidate clock genes (SoLHY, SoPRR5, and SoTOC1), photoreceptor genes (SoPHYA, SoPHYB, and SoZTL), ascorbic acid (AsA) synthesis genes (SoVTC2 and SoGLDH), an AsA degradation gene (SoAPX), an AsA regeneration gene (SoMDHAR), and AsA content of spinach during the pre- and postharvest periods were investigated. The AsA content decreased under constant dark storage, whereas the AsA content was efficiently maintained under a light/dark cycle. Gene expression with rhythmic signals confirmed by the JTK_CYCLE method (P ≤ 0.05) was used for the analysis of partial correlation coefficients. Strong correlations between SoLHY and SoVTC2 were observed under all investigated conditions. AsA synthesis regulation via the clock gene LHY was stable and likely not altered by harvesting stress and/or external light stimuli. After harvesting, SoPRR5 was negatively correlated with SoVTC2. This finding suggested that a reduction in the SoPRR5 expression level might be an alternative way to induce/maintain AsA content during storage. Additionally, the expression of the photoreceptor genes SoPHYA and SoZTL was moderately correlated with that of SoVTC2 during cultivation. Surprisingly, these correlations were not observed during storage even in the presence of light. Instead, SoPHYA expression was correlated with that of another AsA synthesis gene, SoGLDH, under light/dark storage. Moreover, under constant dark storage, SoZTL expression showed a strong correlation with SoVTC2. The considerable variation in the relationship between the expression levels of AsA-related genes and photoreceptor genes during cultivation and storage indicates the contribution of light regulators to maintaining AsA rhythm in spinach. In summary, this study is the first to suggest possible crosslinking of external signals (light/dark), photoreceptor genes, clock genes, and AsA metabolism genes, which are related to changes in the quality of spinach during the pre- and postharvest periods.

Design of A 12-phase Clock Generator Based on DLL

Abstract This article proposes a 12-phase clock generator for DC-DC power supply chips, which can be used for external clock synchronization of DC-DC and serves as the foundation for multiple parallel connections of DC-DC. This article is based on the NTC 0.35 um BCD process and verified through simulation by using Cadence software. In typical environments of 3.3 V and 27°, the clock input range is 832 K-49.6 MHz, the time to reach stability is less than 5 us, the clock jitter is less than 1%, the duty cycle error is less than 3.5%, and the phase error generated is less than 1%.

Synchronized source of indistinguishable photons for quantum networks

We present a source of indistinguishable photons at telecom wavelength, synchronized to an external clock, for the use in distributed quantum networks. We characterize the indistinguishability of photons generated in independent parametric down-conversion events using a Hong-Ou-Mandel interferometer, and show non-classical interference with coalescence, C = 0.83(5). We also demonstrate the synchronization to an external clock within sub-picosecond timing jitter, which is significantly shorter than the single-photon wavepacket duration of ≈ 35 ps. Our source enables scalable quantum protocols over multi-node, long-distance optical networks using network-based clock recovery systems.

Modeling and assessment of Galileo PPP one-way timing with RT-product

Precise point positioning (PPP) technology is widely used in positioning, navigation, and timing. In order to meet the needs of users for real-time high-precision time information, a real-time Galileo PPP one-way timing model based on existing real-time (RT) products (CAS, CNES, GMV, and WHU) was established and applied for the timing field. Experiments were designed with 8 GNSS stations with an external H-MASER clock to research Galileo PPP timing with 25 day observations. For the modified Allan deviation (MDEV) of Galileo PPP timing solutions, similar to the timing solutions of GPS, the MDEV of Galileo PPP with CAS and CNES shows worse short-term frequency stability, with 1 to 2 × 10−13 at 960 s stability, and indicates similar long-term frequency stability, with about 5–6 × 10−15 at 61 440 s stability. For Galileo PPP time transfer, the standard deviation values are about 0.01–0.49 ns for all time-links with different products. For the stability of Galileo time transfer, the similar characteristic of Galileo time transfer is comparable to that of GPS. For short-term stability, the MDEV of all time-links from Galileo PPP ranges from 2 × 10−14 to 3 × 10−14 at 960 s. For long-term stability, 1 to 2 × 10−15 levels can be reached at 61 440 s for all time-links, except for that of CNES.

Frequency Instability Impact of Low-Cost SDRs on Doppler-Based Localization Accuracy.

In this paper, we explore several widely available software-defined radio (SDR) platforms that could be used for locating with the signal Doppler frequency (SDF) method. In the SDF, location error is closely related to the accuracy of determining the Doppler frequency shift. Therefore, ensuring high frequency stability of the SDR, which is utilized in the location sensor, plays a crucial role. So, we define three device classes based on the measured frequency stability of selected SDRs without and with an external rubidium clock. We estimate the localization accuracy for these classes for two scenarios, i.e., short- and long-range. Using an external frequency standard reduces the location error from 20 km to 30 m or 15 km to 2 m for long- and short-range scenarios, respectively. The obtained simulation results allowed us to choose an SDR with appropriate stability. The studies showed that using an external frequency standard is necessary for minimizing SDR frequency instability in the Doppler effect-based location sensor. Additionally, we review small-size frequency oscillators. For further research, we propose two location sensor systems with small size and weight, low power consumption, and appropriate frequency stability. In our opinion, the SDF location sensor should be based on the bladeRF 2.0 micro xA4 or USRP B200mini-i SDR platform, both with the chip-scale atomic clock CSAC SA.45s, which will allow for minor positioning errors in the radio emitters.

A Binary Coding Pattern for Virtual Absolute Encoder

In this article, a binary coding pattern has been presented for the optical type virtual encoder. Unlike the traditional encoder, it can sense the direction, speed, and absolute position of the moving object. In this pattern, each combination of the binary number is represented by pulse transition, thus it is named as pulse transition code (PTC). In addition to the n-track binary code, it has dual clock track. So, in the absence of the external clock (i.e. reference) signal, one track can generate a clock signal during the rotation of the measured object. This signal is not only used for decoding the PTC pattern but also maintain the decoding rate of the receiver unit. Since the second clock track is placed 90 out-of-phase, thus it can sense the speed and direction of the moving object with respect to the prior clock track. Compared to the conventional binary coding pattern, its resolution varies four times per track number ((^)^). Eventually, to demonstrate the decoding methodology of the proposed coding pattern, a 2-bit PTC pattern is designed and developed an algorithm for a Microcontroller based decoder unit. The developed virtual encoder exhibits a satisfactory performance in laboratory conditions.

An Interstation Undifferenced Real-Time Time Transfer Method with Refined Modeling of Receiver Clock

Due to their advantages of high measurement accuracy and wide coverage, global navigation satellite systems (GNSSs) can carry out long-distance time transfers, among which the precise point positioning (PPP) method is widely used. However, the accuracy and stability of PPP real-time time transfer are restricted by the real-time satellite clock offset products. In addition, the receiver clock offset is usually estimated using the white noise model, which ignores the correlation of the clock offsets between adjacent epochs and the stability of the atomic clock itself. In order to obtain higher performance time transfer results, we propose an interstation undifferenced time transfer method with refined modeling of the receiver clock. This method takes the satellite clock offset as the parameter to be estimated, which can avoid the influence of external satellite clock offset products. In addition, the refined modeling of the receiver clock can improve the strength of the model and the accuracy of time transfer. Based on the ultrarapid satellite orbit products provided by the International GNSS Service (IGS), time transfer experiments are carried out using data from IGS observatories and self-collected data. The results show that sub-nanosecond accuracy can be achieved in real-time time transfer using this method. Compared with the traditional PPP model, the accuracies of the four time links are increased by 88.4%, 92.9%, 88.6%, and 74.5%, respectively, and the stability is increased by approximately 66.4% on average. Moreover, after applying the clock offset constraint model, frequency stability is further improved, in which the short-term stability is improved significantly, with a maximum of 86.9% and an average improvement of approximately 66.8%.

Design and development of MTCA.4-based generic control and data acquisition module for CSNS-II and SAPS-TP

A new generation of domestically generic control and data acquisition AMC module has been developed to meet the requirements of the upgrade and renovation of the RCS LLRF system in the CSNS-II project, as well as the horizontal testing needs of the SAPS-TP. This module complies with the MicroTCA.4 standard and utilizes the Xilinx ZYNQ 7045 SOC as the core data processing chip. It can simultaneously run FPGA algorithms and the EPICS IOC remote control application program, serving as an autonomous control node. The module is equipped with 8 channels of 125 MSPS 16-bit ADC and 2 channels of 16-bit DAC with a maximum sampling rate of up to 500 MSPS. It also features standard expansion interface, front optical panel fiber interface, external clock interface, front panel digital IO interface, and more, catering to the needs of multiple systems in accelerator facilities such as radio-frequency, beam diagnostics, and control system. Additionally, the module can function independently for smaller-scale experimental and testing systems, such as the LLRF system for horizontal testing of SAPS-TP. To guarantee the seamless integration and proper operation of the AMC module within the MicroTCA.4 ecosystem, the MMC mezzanine card has been developed and thoroughly tested. In order to further reduce costs for small-scale systems, we optimized the software of the MMC so that the AMC board can run without the MCH module and realize self-health monitoring. For common applications, we have developed a complete software architecture and demo programs, including FPGA firmware, embedded Linux operating system, kernel driver modules, and EPICS IOC demo application programs. Detailed measurements have been conducted on hardware performance such as SNR, SFDR, channel isolation, as well as software performance including AXI DMA data bandwidth and system resources utilization, etc. The measurement results indicate that the module's performance indicators meet the design requirements.

Self-Clocked Shift Registers Utilizing 90 nm CMOS: Design, Analysis and Insights

This paper presents an efficient approach to designing and analyzing four bit shift register utilizing self-clocked D flip-flops as integral storage components. The use of internal clock generation within these flip-flops obviates the need for external clock synchronization. These specially designed flip-flops incorporate a reduced number of transistors in comparison to conventional designs, leading to notable enhancements in power efficiency, packaging density, and operational speed. The implementation of self-triggered D flip-flops facilitates the creation of various shift register configurations, including Serial in Serial out (SISO), Serial in Parallel out (SIPO), Parallel in Serial out (PISO), and Parallel in Parallel out (PIPO). These registers not only occupy a smaller die area but also exhibit diminished power consumption and heightened operational speed when contrasted with standard counterparts. The design and simulation procedures are executed using the Microwind tool and a 90 nm CMOS technology.

An ultra-low power 10-bit, 50 MSps SAR ADC for multi-channel readout ASICs

The design and measurement results of a fast, ultra-low power, small area 10-bit SAR ADC, developed for multi-channel readout systems, in particular for applications in particle physics experiments, are discussed. A prototype ASIC was designed and fabricated in 130 nm CMOS technology and a wide spectrum of static (INL<0.4 LSB, DNL<0.3 LSB) and dynamic (ENOB=9.45) measurements was performed to study and quantify the performance of ADC.The ADC converts analogue signals with a sampling frequency up to 55 MHz and power consumption below 1 mW.The ADC works asynchronously, so no external clock is required. The ADC Figure of Merit (FOM) at 50 MHz sampling frequency is 24 fJ/conv.-step, and is the lowest among the State of the Art designs with similar technology and specifications.

Adaptation of metrology-grade ac current source in velocity mode of Planck-Balance 2: direct referencing induced voltages with ac quantum voltage standard

The adaptation of developed metrology-grade ac current source (MCS) to the velocity mode of measurements of the Planck-Balance 2 as a means for generating ac mechanical oscillations is presented. The universality in operating with the MCS unit especially practical for the Planck-Balance setup for frequencies of 0.1 Hz–20 Hz (including but not limited to the negligence of a broader range of 0.01 Hz up to several hundred Hz) and for amplitudes of up to 10 mA with 16 (offset with 14)-bit effective resolution is demonstrated. MCS allows generating complex ac waveform signals as waveform synthesizers by adding to the original signal an extra five independent harmonic components, each of which with an adjustable resolution of 10 ns for phase and 16-bit for amplitude. Additionally, the MCS is supported by an external clock at 10 MHz frequency which serves also as a common reference time base for the comparison between the direct output signal of MCS, or of the induced voltage in the coil of the Planck-Balance resulting due to the applied current by MCS, with the ac quantum voltage standard at the required accuracy levels.

Novel Approach to Autonomous Lunar Localization and Timing

The ability of a deep space spacecraft to estimate its position, velocity, and clock errors without external clock error estimation is investigated. A novel approach to onboard estimation of clock errors is proposed. The effects of clock bias and drift on spacecraft position and velocity errors are derived. These derived equations are leveraged to design a Kalman filter that processes optical measurements along with one-way ranging or two-way position updates from the ground. Simulations are performed to numerically validate the proposed approach and show good localization and timing estimation performance even with lengthy tracking data gaps.

Design of a high performance Digital data AcquIsition SYstem (DAISY) for innovative nuclear experiments

A dedicated digital data acquisition (DAQ) system has been developed for innovative nuclear data measurements, from time-of-flight to irradiation experiments as well as other basic nuclear physics experiments. The DAQ system is based on fast digitizers with 14 bits resolution and 1 GS/s sampling rate for reliable pulse shape discrimination, energy and timing resolution measurements. Thanks to the high throughput provided by the PCIe bus, data can be processed at CPU or co-processor level, thus allowing great flexibility and reliability. The use of an external clock system and a dedicated triggering system guarantee a very precise synchronization with other possible subsystems in any experimental setup. Finally, its modularity allows to build a flexible and scalable system.

Reconstruction of Range-Doppler Map Corrupted by FMCW Radar Asynchronization.

Frequency-modulated continuous wave (FMCW) radar system synchronization using external clock signals can cause repeated Range-Doppler (R-D) map corruption when clock signal asynchronization problems occur between the transmitter and receiver. In this paper, we propose a signal processing method for the reconstruction of the corrupted R-D map owing to the FMCW radar's asynchronization. After calculating the image entropy for each R-D map, the corrupted ones are extracted and reconstructed using the normal R-D maps acquired before and after the individual maps. To verify the effectiveness of the proposed method, three target detection experiments were conducted: a human target detection in an indoor environment and a wide place and a moving bike-rider target detection in an outdoor environment. The corrupted R-D map sequence of observed targets in each case was reconstructed properly and showed the validity by comparing the map-by-map range and speed changes in the detected target with the ground-truth information of the target.

The feeling of the passage of time against the time of the external clock

When people say that time is passing faster or slower, they are referring to the clock time. What exactly is the role of this reference to clock time in the awareness of the passage of time? Three experiments were conducted to examine this question. In Experiment 1, participants performed an easy and a difficult task in a condition with or without an external clock. In Experiment 2, the external clock was introduced after several trials of the easy task performed by the same participants. In Experiment 3, the speed of the clock hands was manipulated. Eye movements towards the clock were recorded by an eye tracker. The results showed that time was judged to pass faster with the external clock, thus reducing the distortion of the sense of time. Indeed, participants noticed that time passed faster than they initially thought. However, our results also showed that this was an occasional and short-lived adjustment of subjective time to objective time, with a greater acceleration in the presence of the fast clock. Indeed, the clock quickly lost its effect after a few trials, the feeling of the passage remaining based on the emotion felt, i.e., the boredom felt in the easy task. Our experiments thus showed that the feeling of the passage of time is primarily grounded in the emotional affect experienced (Embodiment), and that knowledge of clock time had only a small and transient corrective effect.

Relations between timescales of stochastic thermodynamic observables

Abstract Any real physical process that produces entropy, dissipates energy as heat, or generates mechanical work must do so on a finite timescale. Recently derived thermodynamic speed limits place bounds on these observables using intrinsic timescales of the process. Here, we derive relationships for the thermodynamic speeds for any composite stochastic observable in terms of the timescales of its individual components. From these speed limits, we find bounds on thermal efficiency of stochastic processes exchanging energy as heat and work and bound the rate of entropy change in a system with entropy production and flow. Using the time set by an external clock, we find bounds on the first time to reach any value for the entropy production. As an illustration, we compute these bounds for Brownian particles diffusing in space subject to a constant-temperature heat bath and a time-dependent external force.

A low jitter 50 Gb/s PAM4 optical receiver in 130 nm SiGe BiCMOS

This paper analyzed the causes of phase jitter in four-level pulse amplitude modulation (PAM4) optical receiver (ORX), and a modified architecture was proposed. An optimized shunt-feedback transimpedance amplifier was employed to suppress the random jitter caused by the noise of analog front-end, a three-lane limiting amplifier with inter-stage feedback was introduced to extend the bandwidth, and retimers aligning the edges of thermometer codes with an external clock were also incorporated. The ORX fabricated in 130 nm SiGe BiCMOS technology occupies an area of 1.125 mm2 while dissipating 630 mW. The preliminary measured results demonstrated that the phase jitter of the most significant bit (MSB) was less than 0.08 UI for 25 Gb/s NRZ data. Post-layout simulation results indicate that our ORX can correctly decode 50 Gb/s PAM4 signal under a supply voltage of 3.3 V, and the peak-to-peak jitters for the MSB and the least significant bit (LSB) are only 1.5 ps and 2.9 ps, respectively.