External Access Research Articles

A 36.2 dB High SNR and PVT/Leakage-Robust eDRAM Computing-In-Memory Macro With Segmented BL and Reference Cell Array

Computing-in-memory (CIM) shows high energy-efficiency through the analog DNN computation inside the memory macros. However, as the DNN size increases, the energy-efficiency of CIM is reduced by external memory access (EMA). One of the promising solutions is eDRAM based CIM to increase memory capacity with a high density cell. Although the eDRAM-CIM has a higher density than the SRAM-CIM, it suffers from both poor robustness and a low signal-to-noise ratio (SNR). In this brief, the energy-efficient eDRAM-CIM macro is proposed while improving computational robustness and SNR with three key features: 1) High SNR voltage-based accumulation with segmented BL architecture (SBLA), resulting in 17.1 dB higher SNR, 2) canceling PVT/leakage-induced error with common-mode error canceling (CMEC) circuit, resulting in 51.4&#x0025; PVT variation reduction and 51.4&#x0025; refresh power reduction, 3) a ReLU-based zero-gating ADC (ZG-ADC), resulting in ADC power reduction up to 58.1&#x0025;. According to these new features, the proposed eDRAM-CIM macro achieves 81.5-to-115.0 TOPS/W energy-efficiency with 209-to-295 <inline-formula> <tex-math notation="LaTeX">$\mu \text{W}$ </tex-math></inline-formula> power consumption when 4b <inline-formula> <tex-math notation="LaTeX">$\times $ </tex-math></inline-formula> 4b MAC operation is performed with 250 MHz core frequency. The proposed macro also achieves 91.52&#x0025; accuracy at the CIFAR-10 object classification dataset (ResNet-20) without accuracy drop even with PVT variation.

External Jugular Vein Peripheral Intravenous Catheters: An Emergency Nurse’s Guide

Insertion of a peripheral intravenous catheter into the external jugular vein is regularly performed in emergency departments to treat patients with difficult intravenous access. Although emergency nurses are experienced in inserting peripheral intravenous catheters, there is an inconsistent practice and a lack of education and training regarding the insertion of catheters in the external jugular vein. This manuscript provides a practical guide for emergency nurses to care for patients who require an external jugular peripheral intravenous catheter. Key information found in this manuscript includes indications for external jugular intravenous access, the nurse’s role in performing external jugular peripheral intravenous catheters, and clinical considerations when caring for patients with an external jugular peripheral intravenous catheter.

OmniDRL: An Energy-Efficient Deep Reinforcement Learning Processor With Dual-Mode Weight Compression and Sparse Weight Transposer

In this article, we present an energy-efficient deep reinforcement learning (DRL) processor, OmniDRL, for DRL training on edge devices. Recently, the need for DRL training is growing due to the DRL’s distinct characteristics that can be adapted to each user. However, a massive amount of external and internal memory access limits the implementation of DRL training on resource-constrained platforms. OmniDRL proposes four key features that can reduce external memory access by compressing as much data as possible and can reduce internal memory access by directly processing compressed data. A group-sparse training (GST) enables a high weight compression ratio (CR) for every DRL iteration by selective utilization of weight grouping and weight pruning. A group-sparse training core is proposed to fully take advantage of compressed weight from GST by skipping redundant operations and reusing duplicated data. An exponent-mean-delta encoding additionally compresses the exponent of both weight and feature map for higher CR and low memory power consumption. A world-first on-chip sparse weight transposer enables the DRL training process of compressed weight without off-chip transposer. As a result, OmniDRL is fabricated in a 28-nm CMOS technology and occupies a <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">$3.6\times 3.6$ </tex-math></inline-formula> mm <sup xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">2</sup> die area. It shows a state-of-the-art peak performance of 4.18 TFLOPS and a peak energy efficiency of 29.3 TFLOPS/W. It achieved 7.42-TFLOPS/W energy efficiency for training robot agent (Mujoco Halfcheetah, TD3), which is 2.4 <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">$\times $ </tex-math></inline-formula> higher than the previous state of the art.

ENDOSCOPIC SURGERY OF THE ANTERIOR ETHMOIDAL ARTERY IN EPISTAXIS: DESCRIPTION OF THE TECHNIQUE AND RESULTS

Epistaxis is one of the most common otorhinolaryngological emergencies. Most cases are self-limiting and do not require medical support. While some bleeds require simple local compression to stop the bleeding, others require a more invasive approach, such as ligation or cauterization of the anterior ethmoidal artery or sphenopalatine artery. Anterior ethmoidal artery surgery by external access has been extensively described and studied in the literature. The advent of the endoscope for this procedure has offered the possibility of providing patients and surgeons with an alternative way to perform the surgery. In the present study, patients with epistaxis who underwent endoscopic cauterization of the anterior ethmoidal artery or sphenopalatine artery were selected, and the postoperative results, complications, and recurrence of bleeding were evaluated. In addition, the surgical technique used was described. From these data, it was concluded that endoscopic cauterization surgery of the anterior ethmoidal artery or sphenopalatine artery is effective in the treatment of epistaxis.

A New Hypothesis for Alzheimer's Disease: The Lipid Invasion Model.

This paper proposes a new hypothesis for Alzheimer’s disease (AD)—the lipid invasion model. It argues that AD results from external influx of free fatty acids (FFAs) and lipid-rich lipoproteins into the brain, following disruption of the blood-brain barrier (BBB). The lipid invasion model explains how the influx of albumin-bound FFAs via a disrupted BBB induces bioenergetic changes and oxidative stress, stimulates microglia-driven neuroinflammation, and causes anterograde amnesia. It also explains how the influx of external lipoproteins, which are much larger and more lipid-rich, especially more cholesterol-rich, than those normally present in the brain, causes endosomal-lysosomal abnormalities and overproduction of the peptide amyloid-β (Aβ). This leads to the formation of amyloid plaques and neurofibrillary tangles, the most well-known hallmarks of AD. The lipid invasion model argues that a key role of the BBB is protecting the brain from external lipid access. It shows how the BBB can be damaged by excess Aβ, as well as by most other known risk factors for AD, including aging, apolipoprotein E4 (APOE4), and lifestyle factors such as hypertension, smoking, obesity, diabetes, chronic sleep deprivation, stress, and head injury. The lipid invasion model gives a new rationale for what we already know about AD, explaining its many associated risk factors and neuropathologies, including some that are less well-accounted for in other explanations of AD. It offers new insights and suggests new ways to prevent, detect, and treat this destructive disease and potentially other neurodegenerative diseases.

Intravenous cannula fracture in external jugular vein access: A case report

Cardiovascular Surgery and Interventions publishes original articles on topics in cardiovascular surgery, cardiovascular anesthesia and cardiology. These encompass all relevant clinical, surgical and laboratory studies, editorials, current and collective reviews, technical know-how papers, case reports, interesting images, “How to Do It” papers, correspondence and commentary.

Reduction in the Duration of Postoperative Fever during the COVID-19 Pandemic in Orthopedic and Traumatic Surgery Due to PPE and Cautions.

The Italian government on the 8th of march in response to the increased global prevalenceof severe acute respiratory syndrome coronavirus 2 (SARS-CoV-2) stated a national quarantine. In this period the absence of rapid and sure screening tests for COVID-19 made necessary more attention for presence of fever in hospitalized patients, like continuous use of surgical, FFP2, and FFP3 masks (PPE) by nurses, physicians, and patients; moreover, patients visits were restricted. In this period, during the daily activities in our orthopedic department we observed an empirical decreased incidence of post-operative fever in patients admitted for trauma surgery. The aim of this study is to compare the prevalence of post-operative fever in this period with the same period in 2019. We analyzed the presence of post-operative fever in 110 patients admitted in 2020 and 129 admitted in 2019. The results show a significant decrease of the prevalence and duration of post-operative fever in patients admitted in 2020. This study evidenced that the use of PPE and limitation in external access to the hospital decrease postoperative fever in hospitalized patients undergone surgery for fracture.

HintStor: A Framework to Study I/O Hints in Heterogeneous Storage

To bridge the giant semantic gap between applications and modern storage systems, passing a piece of tiny and useful information, called I/O access hints, from upper layers to the storage layer may greatly improve application performance and ease data management in storage systems. This is especially true for heterogeneous storage systems that consist of multiple types of storage devices. Since ingesting external access hints will likely involve laborious modifications of legacy I/O stacks, it is very hard to evaluate the effect and take advantages of access hints. In this article, we design a generic and flexible framework, called HintStor, to quickly play with a set of I/O access hints and evaluate their impacts on heterogeneous storage systems. HintStor provides a new application/user-level interface, a file system plugin, and performs data management with a generic block storage data manager. We demonstrate the flexibility of HintStor by evaluating four types of access hints: file system data classification, stream ID, cloud prefetch, and I/O task scheduling on a Linux platform. The results show that HintStor can execute and evaluate various I/O access hints under different scenarios with minor modifications to the kernel and applications.

Efficient depthwise separable convolution accelerator for classification and UAV object detection

Depthwise separable convolutions (DSC) have been widely deployed in lightweight convolutional neural networks due to high efficiency. But the acceleration performance of the Graphics Processing Unit for DSC was not as well as in theory. In this paper, some approaches were proposed for accelerating DSC based on Field-Programmable Gate Array (FPGA). For the preceding layers, S2C (spatial to channel) was proposed to accelerate computing and improve the utilization rate of computational resources and bandwidth. An efficient SharePE was proposed to accelerate the DSC, which can improve the efficiency of the computing resource. The regulable parallelism approach was proposed to compute efficiently the different pointwise convolutional layers. P2D&D2P approach is proposed to reduce the external memory access. For the entire accelerating system, the pre-load workflow was proposed to reduce the waiting time of the accelerator between two images. We demonstrated our approaches on the SkyNet using the Ultra96V2 development board. Results indicated that our proposed accelerator obtained 80.030 frames per second and 0.072 Joule per image for UAV object detection, which achieved the state-of-the-art results for SkyNet. Besides, the MobileNetV2 model was implemented on a larger XC7Z100 FPGA, and the results showed our accelerator classified each picture from ImageNet in 2.69 ms. Code is available at https://github.com/AILearnerLi/DAC-SDC-2020-SEUer.

Intracranial complication of acute paranasal sinusitis during active COVID-19 infection – a case report

According to various sources, complications of sinusitis occur with a frequency of between 3 and 17%. Intracranial complications include: meningitis, epidural abscess, subdural abscess, brain abscess, and thrombophlebitis of the dura mater and the brain. The most common intracranial complications are inflammations of the frontal, ethmoid and sphenoid sinuses. A brain abscess is the second most common intracranial complication in the course of sinusitis after meningitis. The presented case concerns a 16-year-old patient treated for brain abscesses and CNS sinus thrombosis in the course of acute purulent inflammation of the frontal and maxillary sinus on the right side. The management of intracranial complications of acute paranasal sinusitis according to EPOS 2022 is high doses of intravenous antibiotics used for a long period, neurosurgical surgical treatment consisting in drainage of abscesses through craniotomy, drainage of the frontal sinus from external or endoscopic access. The prognosis of intracranial complications most often depends on the severity of neurological symptoms and appropriate prompt treatment implementation.

External iliac artery access for transcatheter aortic valve replacement.

External iliac artery access for transcatheter aortic valve replacement.

An FPGA-Accelerated Parallel Digital Beamforming Core for Medical Ultrasound Sector Imaging.

Plane-wave transmission followed by parallel receive beamforming is popular among high frame rate (HFR) ultrasound (US) imaging methods. However, due to technological limitations, HFR imaging is not widely successful in clinical US. The proposed work aims to design a field-programmable gate array (FPGA)-accelerated parallel beamforming core for medical US sector imaging systems. This architecture supports up to 128 channels and forms 28 beams per plane wave transmission in parallel. A block random access memories (BRAMs)-based, 28-read one-write (28R1W) multi-ported delay line architecture is actualized to realize the delay line. In addition, to optimize the FPGA memory, the required beam focusing delays are stored in an external static random access memory (SRAM) and are loaded into the internal delay line registers by a cycle stealing direct memory access (DMA). The FPGA prototype validation and verification are performed on the custom-designed Xilinx-Kintex-7 XC7C410T FPGA-based US imaging platform. The results showed that for a field of view (FOV) of 90° with 0.5° resolution, 640×480 imaging size, a ft/s of 714 is achieved. The performance of the proposed parallel beamformer architecture is compared with existing development works and concluded that the architecture is superior due to its occupancy of FPGA hardware resources and the processing speed.

АНАЛІЗ ЗАГРОЗ БЕЗПЕКИ МІКРОКОНТРОЛЕРІВ

In the article the materials of individual studies of the main security problems in microcontrollers operating as part of control systems of both general and specialized devices were considered and analyzed. In particular, the main trends of security threats were analyzed and the main attacks vectors were presented. Foreign and domestic experience of manifestation of unauthorized influences and cyber threats in the main most critical places of microcontroller architecture is analyzed. The analysis showed that the basic places of security threats and interventions to the microcontroller are: registers, stack, LPA, memory (EEPROM and Flash), input-output ports, circuits and interfaces for data transfer to the MC, circuits for additional functionality for connecting to external peripheral devices and channels for connecting the clock oscillator. In addition, explorations were carried out on the main threats of the microcontroller system memory, namely: interference with direct memory access, access to control registers and access to the microcontroller buffer, buffer stack overflow, remote code execution, external access and attacks on secondary channels (including via external data lines in the MC), changing the order of addressing in the MC, changing / replacing the values of addresses and stack numbering, interfering with the work of data registers and indicating the state of the input / output ports of the microcontroller. A number of protection mechanisms for microcontrollers have also been studied, which together can reduce the risks of unauthorized actions on the microcontroller system. These include: cyclic code redundancy control, power monitoring and resource monitoring, the using of isolation and control of the functionality of the clock system, control of the integrity and reliability of the memory contents, control of external physical and electrical parameters of the microcontroller, virtualization of the main computing process and its multi-level redundancy and restoration of previous states, the using of cryptographic systems and data processing algorithms, the using of multi-level software and hardware isolation.

Modular data model for energy-flexible cyber-physical production systems

Due to the massive expansion of renewable energies and the growing importance of carbon pricing, energy prices are rising, and industrial companies must put higher effort in purchasing electrical energy cost-efficiently. Additionally, the increasing share of renewable energies leads to more volatility in the power market, giving companies the opportunity to reduce their energy costs by using energy-flexibility measures. As thermal supply systems offer a great potential for energy flexibility, building automation systems which control the supply systems must be adapted for communication and external access. Intelligent algorithms interacting with the automation can enable factories to fexibilize their energy purchases and to participate in energy markets by using external information, such as energy prices or forecasts of the machine’s energy demand. This requires seamless communication that connects all hierarchy levels of the Reference Architectural Model Industry 4.0 (RAMI 4.0) from connected world to field level. Also functional safety must be ensured. Moreover, energy-flexibility measures must be validated within simulation environments which should show the same data structure. Therefore, a standardized data model that can be applied across different companies is necessary. We propose a concept for a modular and consistent data model for automation, simulation, and communication to enable simple data exchange using external algorithms. Therefore, base classes containing variables for generic actors and sensors are developed and extended by further variables to model systems based on their control mode. Moreover, a safety module to manage external access by algorithms is included. With this data model, industrial energy supply systems can be easily expanded to include additional components. Furthermore, energy supply systems consisting of several components, such as energy converters, pumps and valves can be modeled in an simple and time-efficient way. The data model is applied to a compression chiller at ETA Research Factory.

The efficacy of the extended endoscopic frontal sinus drill-out in cases of repeatedly operated polypous-purulent pansinusitis accompanied by a whistle in the front wall of the frontal sinus

Treatment of patients with severe chronic and recurrent forms of frontal sinusitis, often caused by scarring as a result of repeated interventions in the frontal sinuses, is a difficult task. In such cases, for adequate drainage of the frontal sinus and ensuring stable patency of the nasolabial anastomosis, an endoscopic extended frontotomy can be the choice operation, the possibility of which certainly depends on the experience of the surgeon, anatomical features of the structure of the frontal sinus and the nature of the pathological process. The article shows the effectiveness of surgical treatment of chronic purulent frontal sinusitis that developed after 5 interventions on the paranasal sinuses with external and combined access, accompanied by the development of a fistulous passage of the anterior wall of the frontal sinus. For wide drainage of the frontal sinus and stable preservation of patency of the nasolabial fistula, the patient underwent extended endoscopic frontotomy (Draf III operation according to the international classification).

Modern Automated Information Systems for Customs Operations Without the Participation of Customs Officials

The article provides a comprehensive analysis of the evolution of the introduction of automated information systems for customs operations from changes in information technology platforms for electronic declaration and the use of electronic forms of documents to changes in international and national legislation regarding the possibility of performing customs operations through an information system without the direct participation of customs officials ( in automatic mode). The main attention is paid to the use of modern information and software tools from the Unified Automated Information System of Customs Authorities and information resources of the customs authorities of the Russian Federation, logically combined into geographically distributed information systems and operating in a secure mode, including the System of Departmental Certification Centers of Customs Authorities, Automated Information system of external access of customs authorities, Unified automated information system of customs authorities, information systems for supporting the activities of organizational, staffing, personnel and financial divisions of the Federal Customs Service, external information systems, including open information resources of customs authorities in the international association of networks “Internet”. The developed information and software tools and the created information-computing and telecommunication infrastructures are used in all electronic customs, electronic declaration centers, at all customs posts of actual control and checkpoints.

A Framework for Ultra Low-Power Hardware Accelerators Using NNs for Embedded Time Series Classification

In embedded applications that use neural networks (NNs) for classification tasks, it is important to not only minimize the power consumption of the NN calculation, but of the whole system. Optimization approaches for individual parts exist, such as quantization of the NN or analog calculation of arithmetic operations. However, there is no holistic approach for a complete embedded system design that is generic enough in the design process to be used for different applications, but specific in the hardware implementation to waste no energy for a given application. Therefore, we present a novel framework that allows an end-to-end ASIC implementation of a low-power hardware for time series classification using NNs. This includes a neural architecture search (NAS), which optimizes the NN configuration for accuracy and energy efficiency at the same time. This optimization targets a custom designed hardware architecture that is derived from the key properties of time series classification tasks. Additionally, a hardware generation tool is used that creates a complete system from the definition of the NN. This system uses local multi-level RRAM memory as weight and bias storage to avoid external memory access. Exploiting the non-volatility of these devices, such a system can use a power-down mode to save significant energy during the data acquisition process. Detection of atrial fibrillation (AFib) in electrocardiogram (ECG) data is used as an example for evaluation of the framework. It is shown that a reduction of more than 95% of the energy consumption compared to state-of-the-art solutions is achieved.

Hardware-Efficient Residual Neural Network Execution in Line-Buffer Depth-First Processing

Deep convolutional neural networks (CNNs) provide State-of-the-Art (SotA) results in a variety of machine learning (ML) applications, such as image classification and object detection. The trends towards higher-resolution input images and large-scale model structures have brought drastic performance improvements for these tasks. Yet, these trends also pose increased stress on hardware resources. Recent work proposed an advanced layer fusion method relying on the line-buffer depth-first (LBDF) processing, to reduce memory usage and off-chip memory accesses in high resolution CNN processing. However, when deploying such LBDF approach for residual networks, the required external memory access or on-chip memory capacity drastically increases again, hence canceling many benefits of the depth-first approach. This paper, therefore, outlines and analyzes the possible methods for handling residual connections (RC) in combination with LBDF. With the proposed ReLU-based compression and tiling techniques, we minimize the overhead of RC on on-chip memory requirements and external memory accesses. Moreover, a proposed hybrid strategy, optimally combining the different methods across different residual blocks of a residual network, yields for ResNet20 and SqueezeNet a reduction of 24.7% and 45.1% respectively in inference energy cost. Also the execution latency is reduced by 19.4% and 46.7% respectively in comparison to the best single method under certain on-chip memory budgets. In addition, compared to the SotAs, in the best case, our hybrid strategy only consumes 43% energy and 29.9% latency while use the same on-chip memories; only requires 27.4% on-chip memory to achieve the same performance.

Reducing Delays in a Pediatric Procedural Unit With Ultrasound-Guided Intravenous Line Insertion.

Delay in vascular access is a leading cause of procedure delay in our pediatric procedure and infusion center. Use of ultrasound decreases time to peripheral intravenous catheter (PIV) insertion; however, ultrasound availability in our center was limited to an external venous access team (VAT). The objective of this project was to reduce PIV-related delays by 25%. Stakeholders convened and theorized that creating a unit-based nurse team specializing in ultrasound-guided peripheral intravenous catheter (USgPIV) insertion would facilitate faster access and a reduction in delayed procedures. An initial plan-do-study-act cycle was performed, training 2 nurses in USgPIV placement. Subsequent cycles were focused on increasing availability of USgPIV-trained nurses. The outcome measure was the rate of procedures delayed by PIV placement, analyzed on a statistical process control U-chart. The process measure was the percentage of USgPIV placements requiring consultations to the VAT, analyzed on a statistical process control P-chart. The balancing measure was the success rate per method of insertion. Comparisons of success rates were conducted by using a χ2 test and Fisher's exact test. The mean rate of procedures delayed because of vascular access fell by special cause variation from 10.8% to 6.4%. The mean VAT consultation rate fell from 86.4% to 32.0%. The VAT had higher rates of overall success (100% vs 87%; P = .01) and first-attempt success (93% vs 77%; P = .03) compared with unit nurse USgPIV placement. Unit-based USgPIV placement in a pediatric procedural center was successfully implemented, with a significant decline in procedures delayed by PIV access.

ANALYSIS OF SUSTAINABILITY REPORT DISCLOSURE, EXTERNAL ASSURANCE, ENVIRONMENTAL PERFORMANCE AND FINANCIAL ACCESS ON NON-FINANCIAL SECTOR COMPANIES

Economic growth in Indonesia is growing rapidly, this further exacerbates the current environmental conditions which are characterized by high levels of pollution, greenhouse gas effects, global warming and the threat of ecosystem extinction. The emergence of various environmental problems that occur today are caused by various sectors, one of which is the industrial sector. As the largest contributor to GDP in Indonesia, the industrial sector which is an IDX listing company has an obligation to have a sustainability report where this report describes economic, social and environmental activities. This sustainability report can provide information symmetry that can be considered by third parties, both financial institutions and investors. This sustainability report must have external quality and assurance so that it is not just a disclosure but can be a reliable sustainability report.&#x0D; Therefore, this study has an aim to analyze the relationship between the sustainability reports quality, the external assurance quality, usage of external assurance, environmental performance and financial access. The sample population are non-financial sector companies listed on the Indonesia Stock Exchange and PROPER during the 2014-2019 period. The analytical method used is panel data regression analysis using STATA.The result of this study found a significant strongly relationship between environmental performance and the quality of sustainability report disclosures on the company's financial access. In contrast, there is an insignificant effect between the quality of external assurance sustainability report disclosure on the financial access of the main sector and manufacturing companies.&#x0D;