Abstract
In embedded applications that use neural networks (NNs) for classification tasks, it is important to not only minimize the power consumption of the NN calculation, but of the whole system. Optimization approaches for individual parts exist, such as quantization of the NN or analog calculation of arithmetic operations. However, there is no holistic approach for a complete embedded system design that is generic enough in the design process to be used for different applications, but specific in the hardware implementation to waste no energy for a given application. Therefore, we present a novel framework that allows an end-to-end ASIC implementation of a low-power hardware for time series classification using NNs. This includes a neural architecture search (NAS), which optimizes the NN configuration for accuracy and energy efficiency at the same time. This optimization targets a custom designed hardware architecture that is derived from the key properties of time series classification tasks. Additionally, a hardware generation tool is used that creates a complete system from the definition of the NN. This system uses local multi-level RRAM memory as weight and bias storage to avoid external memory access. Exploiting the non-volatility of these devices, such a system can use a power-down mode to save significant energy during the data acquisition process. Detection of atrial fibrillation (AFib) in electrocardiogram (ECG) data is used as an example for evaluation of the framework. It is shown that a reduction of more than 95% of the energy consumption compared to state-of-the-art solutions is achieved.
Highlights
It uses a fixed-point library to exactly model the arithmetic behavior of the hardware on bit level, which leads to the aforementioned name
The ONNX model is used in our hardware generation and parametrization tool, which parses and analyzes the network definition and creates an HDL design based on hardware components that we designed
Our framework is not limited to a specific toolset, because the hardware components are available as HDL description or hardware libraries
Summary
Daniel Reiser 1, * , Peter Reichel 2 , Stefan Pechmann 3 , Maen Mallah 4 , Maximilian Oppelt 4 , Amelie Hagelauer 3,5 , Marco Breiling 4 , Dietmar Fey 1 and Marc Reichenbach 6. Fraunhofer Institute for Microsystems and Solid State Technologies (EMFT), 80686 Munich, Germany
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