Expression For Threshold Voltage Research Articles

Analysis of temperature dependence of CMOS transistors' threshold voltage

In this paper an investigation of influence of the metal-semiconductor work function difference on the threshold voltage of high-temperature (up to 473 K) operating CMOS transistors, which is often neglected in the literature, is presented. Expressions for temperature dependence of the threshold voltage of both Al-gate and Si-gate CMOS transistors, which take into account the influence of the metal-semiconductor work function difference, are derived starting from the standard expression for the MOS transistor threshold voltage. The temperature coefficient of the threshold voltage is considered in more detail, to provide a simple approximate model for the temperature dependence of the threshold voltage. It is shown that neglecting the temperature dependence of the metal-semiconductor work function difference significantly affects accuracy in prediction of the threshold voltage temperature behavior.

Characterization of the inverse-narrow-width effect

The inverse-narrow-width effect, the reduction in the threshold voltage with decreasing device width, is modeled and experimentally measured. A fringing gate capacitance model is extended to include the effects of the sidewall interface charge. Two- and three-dimensional simulations are used to illustrate the enhanced sidewall potential and current, and the effect of sidewall interface charge on the electrical behavior of MOSFET's with fully recessed isolation oxides. We compare the closed-form analytical threshold voltage expression developed with experimental data from small-geometry NMOS devices and find very good agreement.

A three-dimensional threshold voltage expression for MOSFETs with deep-trench isolation

A three-dimensional threshold voltage expression for MOSFETs with deep-trench isolation

A threshold voltage expression for small-size MOSFET's based on an approximate three-dimensional analysis

A simple threshold voltage expression based on an approximate three-dimensional analysis has been obtained for MOSFET's with the LOCOS isolation structure. It predicts both the short-channel and the narrow-width effects on the threshold voltage of MOSFET's, and the results match the experimental data. In addition, the threshold expression is more general than any other existing models. It includes all the relevant device parameters, such as the drain voltage, the oxide and surface charges, and the fringe field through the oxide sidewalls.

Analytical MOSFET Model with Easily Extracted Parameters

A model for MOSFET's is presented which can accurately represent devices over a wide variety of process parameters, geometries, and regions of operation. The model is analytic in all regions, contains only 5 parameters, and is easily implemented in circuit simulation programs. Threshold shifts due to substrate bias for a wide variety of channel doping profiles can be represented by the unique mathematical function used in the expression for threshold voltage. Each parameter of the model dominates a specific region of the I-V curves, making the parameter extraction process a simpler matter of calculating each parameter from measurements in its own region of dominance. No optimization is needed. Curves generated by the model are compared with data from a specific process. Above threshold and subthreshold Id-Vds, threshold voltage versus substrate bias, and transconductance curves are presented.

An analytical model for the threshold voltage of a narrow-width MOSFET

A closed form analytical expression is derived to predict the threshold voltage of a narrow-width MOSFET. The present calculation utilizes the Fourier transform technique to analyze the voltage over the width cross section of the basic MOS device structure. No fitting parameter with experimental data is necessary because the fringe electric field is calculated directly from the relevant physical parameters to deduce the threshold voltage. The dependence of threshold voltage on channel width and substrate bias thus obtained is in reasonable agreement with experimental and numerical results. The effects of field doping and field oxide thickness on the threshold voltage are also taken into consideration. A comparison is made of the present analytical expression for threshold voltage with that, based on an adjustable weighting factor, of earlier analytical models.

Imaging latch-up sites in LSI CMOS with a laser photoscanner : Daniel J. Burns and Jeffrey M. Kendall. IEEE 21st Ann. Proc. Reliab. Phys. 118 (1983)

In this paper an investigation of influence of the metal-semiconductor work function difference on the threshold voltage of high-temperature (up to 473 K) operating CMOS transistors, which is often neglected in the literature, is presented. Expressions for temperature dependence of the threshold voltage of both Al-gate and Si-gate CMOS transistors, which take into account the influence of the metal-semiconductor work function difference, are derived starting from the standard expression for the MOS transistor threshold voltage. The temperature coefficient of the threshold voltage is considered in more detail, to provide a simple approximate model for the temperature dependence of the threshold voltage. It is shown that neglecting the temperature dependence of the metal-semiconductor work function difference significantly affects accuracy in prediction of the threshold voltage temperature behavior.

A simple model for short-channel effects of a buried-channel MOSFET on the buried insulator

A majority-carrier distribution model and a channel potential-profile model, in which the barrier-lowering effect is taken into account, are proposed for a buried-channel MOSFET (BC-MOSFET/ SOI). Simple expressions for threshold voltage and drain breakdown voltage were derived from the models for a short-channel BC-MOSFET/ SOI. The comparison between theory and experimental results shows reasonable agreement. The drain-bias coefficient γ of threshold voltage for BC-MOSFET's/ SOI is approximately proportional to TN D -1L eff -2, where T, N D , and L eff are the temperature, the doping concentration in the channel region, and the channel length, respectively. The coefficient γ depends slightly on the drain bias. BC-MOSFET's/SOI are able to be more miniaturized than surface-channel MOSFET's (SC-MOSFET's) at the small power source voltage, and SC-MOSFET's are able to be more miniaturized than BC-MOSFET's/SOI at the large drain bias. It is shown that the conventional, simple scaling scheme, which holds the constant electric field, is not applicable to BC-MOSFET's/SOI. The power source voltage has to be fixed when dimensions and doping concentrations are scaled down. On the other hand, only the channel region thickness has to be fixed when the power source voltage is scaled down.

A closed-form threshold voltage expression for a small-geometry MOSFET

An analytical expression is developed to predict the threshold voltage of a small-geometry MOSFET. The expression includes the effects of field doping encroachment at the channel edges, and charge sharing with the source and drain regions.

An analytical expression for the threshold voltage of a small geometry MOSFET

A closed form analytical expression for the threshold voltage of a small geometry MOSFET is developed. The threshold voltage expression is derived from a three dimensional geometrical approximation of the bulk charge. The threshold voltage is expressed as a function of gate oxide thickness, channel doping concentraton, junction-depth, backgate bias and channel length and width. The theory is compared with experimental results and the agreement is close.

Threshold voltage of a narrow-width MOSFET

A simple closed-form analytical expression of the threshold voltage for a narrow-width MOSFET is developed. The narrow-width model gives a threshold voltage expression as a function of gate oxide thickness, channel doping concentration, backgate bias and channel width. The theory is compared with experimental results and the agreement is close.

Theory of the fully depleted SOS/MOS transistor

The subject of full film depletion of the SOS/MOS transistor and its impact on threshold voltage and the weak inversion slope factor is addressed. A rigorous one dimensional field analysis of the SOS transistor is performed. The silicon/sapphire interface is treated in the analysis as a discrete interface. The depletion approximation is invoked in order to obtain relatively simple expressions for threshold voltage and the weak inversion slope factor. Experimental data is then compared with data generated by the mathematical models. Both the experimental and model data indicate increase in both absolute threshold voltage and weak inversion slope factor with decreasing epitaxial film thickness.

An analysis of the threshold voltage for short-channel IGFET's

For short-channel insulated-gate field-effect transistors (IGFET) operating with source-to-substrate reverse bias, the threshold voltage is in general a function of channel length and drain-to-source voltage. It is shown in this analysis that these dependences can be attributed to the two-dimensional distribution of the depletion charges. Starting from two fundamental relations, the overall charge neutrality and the voltage relations based on the energy band diagram, a generalized threshold voltage equation in integral form is derived. A closed-form threshold equation is then obtained using a regional approximation with a simplified piecewise-linear depletion profile. The equation includes as new factors, the channel length, junction depth and drain voltage, and passes to the conventional form for increasing channel length. The theoretical threshold voltage expression is found to predict the correct tendencies and is shown to be in reasonable agreement with experimental measurements.