Despite the widening gap between scaled feature sizes and optical exposure wavelengths, integrated circuit transistor density so far has kept pace with Moore’s Law. The absence of viable lens materials for smaller wavelengths precludes exposure wavelengths below 193nm for refractive optical tools. Reflective optical exposure tools using extreme ultraviolet (EUV) light have been under intense development over the past decade but, mainly due to light source power shortfalls, have not yet achieved performance levels needed for high volume production. Alternatives to optical pattern transfer are also under development, including electron beam direct write, and nano-imprint lithography (NIL) systems. Until EUV or an alternative technology meets high-volume production requirements, next-generation integrated circuit process nodes will rely upon 193nm immersion lithography tools augmented with novel optical and process technologies to achieve feature pitches below the single exposure resolution limit. Squeezing more information through the limited spatial bandwidth of 193nm systems imposes limitations on design layout freedoms. Designers can no longer draw arbitrary patterns even when minimum line and space dimension constraints are met. The types of layout restrictions demanded by alternative lithography approaches, and their impact on patterning resolution and noise trade-offs, are explored in the context of evolving IC end-use values, such as density, performance, and power efficiency.