Exponentiation In GF Research Articles

High-performance computing VLSI system for bit-parallel exponentiation in GF(2m)

Finite or Galois fields are used in numerous applications like error correcting codes in digital communication, pseudorandom number generation and cryptography. These applications often require computing exponentiation in which is a very computationally intensive operation. This article presents a high-performance computing method for performing exponentiation in . The key contribution of this article is to extend the bit-parallel structure for multiplication and division where bits of operands are processed at the same time, each bit traveling over a different path in the circuits to perform exponentiation. In addition, we also simplify the structure of parallel modules and pipelining stages in the proposed bit-parallel structure for exponentiation by considering the properties of and hardwiring many constant terms. The circuit architecture for the developed structure is shown for the example case of , and compared with existing approaches with respect to latency, hardware cost, area, delay, throughput and power dissipation for to . The results show that the proposed system has a low latency, hardware costs, area, delay and power dissipation that do not increase rapidly with increasing and a high throughput that does not decrease rapidly as increases compared with existing approaches.

Low-complexity Parallel and Serial Systolic Architectures for AB2 Multiplication in GF(2m)

Efficient arithmetic is essential for fast implementation of cryptographic applications based on finite fields. This paper presents a new parallel systolic AB2 multiplier for exponentiation in GF(2m) that has a low cell delay and high throughput. In addition, a serial systolic AB2 multiplier that can be applied well in space-limited hardware is presented. Thus, exponentiation can be implemented more efficiently by repeatedly applying AB2 multiplication rather than AB multiplication. The proposed parallel (serial) multipliers produce the results at a rate of one per 1 (m/2) cycles with a latency of 2m+m/2-1(2m+m/2-1) cycles using O(m3)(O(m2)) area-time complexity. As compared to related works, both multipliers have lower area-time complexity, cell delay and latency and higher throughput and include the features of regularity, modularity, unidirectional data flow and local interconnection.

Nonlinear network coding based on multiplication and exponentiation in GF(2 m)

This article proposes a novel nonlinear network code in the GF(2 m ) finite field. Different from previous linear network codes that linearly mix multiple input flows, the proposed nonlinear network code mixes input flows through both multiplication and exponentiation in the GF(2 m ). Three relevant rules for selecting proper parameters for the proposed nonlinear network code are discussed, and the relationship between the power parameter m and the coding coefficient K is explored. Further analysis shows that the proposed nonlinear network code is equivalent to a linear network code with deterministic coefficients.

Efficient parallel exponentiation in [formula omitted] using normal basis representations

Von zur Gathen proposed an efficient parallel exponentiation algorithm in finite fields using normal basis representations. In this paper we present a processor-efficient parallel exponentiation algorithm in GF ( q n ) which improves upon von zur Gathen's algorithm. We also show that exponentiation in GF ( q n ) can be done in O ( ( log 2 n ) 2 / log q n ) time using n / ( log 2 n ) 2 processors. Hence we get a processor-time bound of O ( n / log q n ) , which matches the best known sequential algorithm. Finally, we present an efficient on-line processor assignment scheme which was missing in von zur Gathen's algorithm.

A low-complexity power-sum circuit for GF(2/sup m/) and its applications

This brief presents a new hardware-efficient bit-parallel circuit for computing C+AB/sup 2/ in finite fields GF(2/sup m/) over the canonical basis. It consists of two parts: a normal poser-sum part and modular-reduction part, where each part is realized in a binary XOR tree structure. The proposed power-sum circuit works for the general-form generating polynomial and requires 3 m/sup 2/-2 m AND gates and 3 m/sup 2/-4 m+2 XOR gates to reach low time complexity of O(log/sub 2/ m). As compared to the conventional cellular-array structures for C+AB/sup 2/ in GF(2/sup m/), the proposed one involves less hardware complexity and achieves a significant reduction in time complexity. The hardware requirement can further be reduced when a special-form generating polynomial is adopted. The corresponding reduced structures based on three special-form generating polynomials, including the trinomial x/sup m/+x+1, the all-one polynomial, and the equally spaced polynomial, are given to demonstrate this property. A versatile structure, which can be programmed to compute inverses/divisions and exponentiations in GF(2/sup m/), is also constructed based on the proposed power-sum circuit.

VLSI architectures for computing exponentiations, multiplicative inverses, and divisions in GF(2/sup m/)

A modified parallel-in-parallel-out linear-systolic power-sum circuit designed to perform AB/sup 2/+C computations in the finite field GF(2/sup m/) is presented, where A, B, and C are arbitrary elements of GF(2/sup m/). On the basis of the linear-systolic power-sum circuits, a VLSI architecture for exponentiation in GF(2/sup m/) is developed. Furthermore, two modified architectures that can be used to compute inverses and divisions over GF(2/sup m/) are proposed. All the architectures are constructed from m-1 linear-systolic power-sum circuits. It should be noted that the presented exponentiator, inverter, and divider are the only such circuits having a throughput of 100%. The latency of the presented pipeline exponentiator, inverter, and divider is m(m-1) clock cycles. The cycle time (i.e., clock period) of the presented architectures is only two logic gate delays plus a short routing delay. For moderate values of m, say m/spl les/10, the circuit complexity of the presented circuits is realizable using presently available VLSI technology. The computation time of near two gate delays and 100% throughput enables the greatest computation speed in finite field arithmetic.

ACE: a VLSI chip for Galois field GF(2/sup m/) based exponentiation

Finite or Galois fields are used in numerous applications like error correcting codes, digital signal processing and cryptography. These applications often require computing exponentiations in GF(2/sup m/) which is a very computationally intensive operation. The methods proposed in the literature achieve exponentiation by iterative methods using repeated multiplications and the hardware implementations use a number of Galois field multipliers in parallel resulting in expensive hardware. In this paper, we present a new algorithm based on a pattern matching technique for computing exponentiations in GF(2/sup m/), for values of m/spl les/8. A systolic array processor architecture was developed by the authors for performing multiplication and division in GF(2/sup m/) in [13]. A similar strategy is proposed in this paper for achieving exponentiation at the rate of a new result every clock cycle. A prototype VLSI chip Called ACE implementing the proposed architecture for Galois field GF(2/sup 4/) has been designed and verified using CMOS 2 /spl mu/m technology. The chip can yield a computational rate of 40 million exponentiations per second.

Bit-level systolic array for fast exponentiation in GF(2/sup m/)

This paper presents a new parallel-in-parallel-out bit-level systolic array with unidirectional data flow for computing exponentiation in GF(2/sup m/). The array is highly regular, modular, and thus well suited to very-large-scale-integration implementation. In addition, it can provide the maximum throughput in the sense of producing new results at a rate of one per clock cycle. As compared with a previously known systolic GF(2/sup m/) exponentiator with the same throughput performance, the proposed system requires much less chip area, has small latency, and is easier to incorporate fault-tolerant design.< <ETX xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">&gt;</ETX>

Low complexity architecture for exponentiation in GF(2 m )

A pipeline bit serial multiplier architecture for the Galois field GF (2m) is presented. A structure for finite field exponentiation is developed based on the multiplier. The structure is regular, area efficient and suitable for VLSI implementation for large fields.

A VLSI design for computing exponentiations in GF(2/sup m/) and its application to generate pseudorandom number sequences

A VLSI design for computing exponentiation in finite fields is developed. An algorithm to generate a relatively long pseudorandom number sequence is presented. It is shown that the period of this sequence is significantly increased compared to that of the sequence generated by the most commonly used maximal length shift register scheme.< <ETX xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">&gt;</ETX>

Architectures for exponentiation in GF(2/sup m/)

Several VLSI architectures for performing exponentiation in GF(2/sup m/) are presented. Two approaches to the architecture design are taken. In the first, all intermediate products of the exponentiation are computed in a sequential fashion to minimize the silicon area. In the second approach, all values of raised to the 2/sup ei/ power, O >