Low-complexity Parallel and Serial Systolic Architectures for AB2 Multiplication in GF(2m)

Abstract

Efficient arithmetic is essential for fast implementation of cryptographic applications based on finite fields. This paper presents a new parallel systolic AB2 multiplier for exponentiation in GF(2m) that has a low cell delay and high throughput. In addition, a serial systolic AB2 multiplier that can be applied well in space-limited hardware is presented. Thus, exponentiation can be implemented more efficiently by repeatedly applying AB2 multiplication rather than AB multiplication. The proposed parallel (serial) multipliers produce the results at a rate of one per 1 (m/2) cycles with a latency of 2m+m/2-1(2m+m/2-1) cycles using O(m3)(O(m2)) area-time complexity. As compared to related works, both multipliers have lower area-time complexity, cell delay and latency and higher throughput and include the features of regularity, modularity, unidirectional data flow and local interconnection.