Exponential Circuit Research Articles

Shallow-Depth Quantum Circuit for Unstructured Database Search

Grover’s search algorithm (GSA) offers quadratic speedup in searching unstructured databases but suffers from exponential circuit depth complexity. Here, we present two quantum circuits called HX and Ry layers for the searching problem. Remarkably, both circuits maintain a fixed circuit depth of two and one, respectively, irrespective of the number of qubits used. When the target element’s position index is known, we prove that either circuit, combined with a single multi-controlled X gate, effectively amplifies the target element’s probability to over 0.99 for any qubit number greater than seven. To search unknown databases, we use the depth-1 Ry layer as the ansatz in the Variational Quantum Search (VQS), whose efficacy is validated through numerical experiments on databases with up to 26 qubits. The VQS with the Ry layer exhibits an exponential advantage, in circuit depth, over the GSA for databases of up to 26 qubits.

Hay from the Haystack: Explicit Examples of Exponential Quantum Circuit Complexity

The vast majority of quantum states and unitaries have circuit complexity exponential in the number of qubits. In a similar vein, most of them also have exponential minimum description length, which makes it difficult to pinpoint examples of exponential complexity. In this work, we construct examples of constant description length but exponential circuit complexity. We provide infinite families such that each element requires an exponential number of two-qubit gates to be generated exactly from a product and where the same is true for the approximate generation of the vast majority of elements in the family. The results are based on sets of large transcendence degree and discussed for tensor networks, diagonal unitaries and maximally coherent states.

A Low-Cost Hardware-Friendly Spiking Neural Network Based on Binary MRAM Synapses, Accelerated Using In-Memory Computing

In recent years, the scaling down that Moore’s Law relies on has been gradually slowing down, and the traditional von Neumann architecture has been limiting the improvement of computing power. Thus, neuromorphic in-memory computing hardware has been proposed and is becoming a promising alternative. However, there is still a long way to make it possible, and one of the problems is to provide an efficient, reliable, and achievable neural network for hardware implementation. In this paper, we proposed a two-layer fully connected spiking neural network based on binary MRAM (Magneto-resistive Random Access Memory) synapses with low hardware cost. First, the network used an array of multiple binary MRAM cells to store multi-bit fixed-point weight values. This helps to simplify the read/write circuit. Second, we used different kinds of spike encoders that ensure the sparsity of input spikes, to reduce the complexity of peripheral circuits, such as sense amplifiers. Third, we designed a single-step learning rule, which fit well with the fixed-point binary weights. Fourth, we replaced the traditional exponential Leak-Integrate-Fire (LIF) neuron model to avoid the massive cost of exponential circuits. The simulation results showed that, compared to other similar works, our SNN with 1184 neurons and 313,600 synapses achieved an accuracy of up to 90.6% in the MNIST recognition task with full-resolution (28 × 28) and full-bit-depth (8-bit) images. In the case of low-resolution (16 × 16) and black-white (1-bit) images, the smaller version of our network with 384 neurons and 32,768 synapses still maintained an accuracy of about 77%, extending its application to ultra-low-cost situations. Both versions need less than 30,000 samples to reach convergence, which is a >50% reduction compared to other similar networks. As for robustness, it is immune to the fluctuation of MRAM cell resistance.

Design of a range-segmented CMOS current-mode exponential circuit

Design of a range-segmented CMOS current-mode exponential circuit

Wide Range High Precision CMOS Exponential Circuit Based on Linear Least Squares Approach

Wide Range High Precision CMOS Exponential Circuit Based on Linear Least Squares Approach

Switching sliding-mode control strategy based on multi-type restrictive condition for voltage control of buck converter in auxiliary energy source

In this paper, a switching sliding-mode control strategy is proposed for the voltage control of a buck converter in auxiliary energy source. The aim of this study is to solve the singularity problem of the terminal sliding-mode control strategy and simplify the implementation of the exponential operation of the non-singular terminal sliding-mode control strategy in practical applications. To achieve this goal, the state-space model of the buck converter in the auxiliary energy source is established. Furthermore, a novel switching sliding surface is defined based on the non-singular terminal sliding-mode control strategy. To ensure the stability of the switching sliding-mode control system, a multi-type restrictive condition, including non-singular type and reachable type, is designed based on equivalent control law and Lyapunov stability criterion, respectively. Simulations and experiments are presented to verify the effectiveness of the proposed switching sliding-mode control strategy. The results show that both the non-singular terminal sliding-mode control and the switching sliding-mode control can effectively solve the singularity problem. Compared with the terminal sliding-mode control strategy, the non-singular terminal sliding-mode control and the switching sliding-mode control strategies have over 18% and 34.4% settling-time improvement of voltage adjustment to deal with the large load variation, respectively. The proposed switching sliding-mode control strategy can not only ensure the robust voltage control of the buck converter in the auxiliary energy source, but also simplify the implementation of exponential circuit in practical applications.

On the limits of gate elimination

Although a simple counting argument shows the existence of Boolean functions of exponential circuit complexity, proving superlinear circuit lower bounds for explicit functions seems to be out of reach of the current techniques. There has been a (very slow) progress in proving linear lower bounds with the latest record of 3186n−o(n). All known lower bounds are based on the so-called gate elimination technique. A typical gate elimination argument shows that it is possible to eliminate several gates from a circuit by making one or several substitutions to the input variables and repeats this inductively. In this paper we prove that this method cannot achieve linear bounds of cn beyond a certain constant c, where c depends only on the number of substitutions made at a single step of the induction.

A Low-Power Wideband dB-Linear Variable Gain Amplifier With DC-Offset Cancellation for 60-GHz Receiver

This paper presents a two-channel (I+Q) variable gain amplifier (VGA) for low power 60-GHz wireless receiver. The VGA consists of four-stage gain cells, an efficient DC-offset cancelling circuit and an output buffer for test purposes. To achieve wide bandwidth and low power consumption, a modified Cherry—Hooper amplifier gain cell is used. With a tunable transistor and its parasitic capacitance, a dB-linear characteristic and a flat gain response are achieved without any additional exponential circuit. The DC-offset is cancelled effectively with two proposed feedback loops. The measurement results show that the VGA achieves a gain range of 6 to 44 dB, an OP1dB of 1 dBm, and a 3-dB bandwidth of over 1 GHz with an excellent flat gain response. Fabricated in a 65-nm CMOS technology, the two-channel VGA core occupies a silicon area of only 0.055 mm2 and consumes only 10 mA from a 1.2 V power supply.

A High-Accurate Exponential Function Generator Based on a New Pseudo-Approximation Method by TLBO Optimization Algorithm

A compact and low-voltage CMOS exponential function generator circuit based on a new pseudo-approximation method is designed in 180-nm CMOS standard technology. The proposed approximation method is based on the TLBO evolutionary algorithm and shows a close characteristic to the ideal exponential function behavior over wide input range. Simulation results using HSPICE validate the theoretical analysis and verify the efficiency of proposed circuit which shows more than 66 dB output dynamic voltage range while the error is less than $${\pm }0.5\,\hbox {dB}$$ . The total power consumption is below 0.17 mW with a $${\pm }0.75\,\hbox {V}$$ power supply.

High output dynamic range exponential function synthesizer

The paper presents two original high-accuracy exponential function synthesizers with wide output dynamic ranges. The improved accuracies of the proposed computational structures are obtained using new superior-order approximation functions. In order to additionally improve the circuits' output dynamic ranges, an original method based on proper variable changing will be used and implemented. As a result of the new proposed design methods, the performances of the exponential structures are only slightly affected by technological errors. The best original proposed architecture of the exponential synthesizer has an output dynamic range of 100dB, for an approximation error smaller than ±1dB. The exponential circuits are designed for implementing in 0.18µm CMOS technology and they present a low-voltage low-power operation – the minimal supply voltage is about 0.7V, while the power consumption is smaller than 2μW. The chip area is about 4.5µm2 for an implementation in 0.18µm CMOS technology of the best proposed exponential circuit.

PWL Current-Mode CMOS Exponential Circuit Based on Maximum Operator

A novel technique to implement an exponential pre-distortion circuit based on a piecewise-linear (PWL) construction method is presented. The technique is based on a maximum operator together with rectified affine functions. The proposed circuit is implemented with current mirrors and a Winner-Take-All circuit, thus achieving a technology-independent exponential circuit with no range limit, ideally. The proposed technique avoids the propagation and accumulation of the linear segment errors, which affect the exponential approximation only locally. To demonstrate the technique, a prototype was fabricated in 0.13 $\mu\mbox{m}$ CMOS technology and measurement results were obtained revealing a linear-in-decibel range around 41 dB with an error of ±1 dB and 535 $\mu\mbox{W}$ power consumption.

A Hybrid Scheme of Public-Key Encryption and Somewhat Homomorphic Encryption

We introduce a hybrid homomorphic encryption that combines public-key encryption (PKE) and somewhat homomorphic encryption (SHE) to reduce the storage requirements of most somewhat or fully homomorphic encryption (FHE) applications. In this model, messages are encrypted with a PKE and computations on encrypted data are carried out using SHE or FHE after homomorphic decryption. To obtain efficient homomorphic decryption, our hybrid scheme combines IND-CPA PKE without complicated message padding with SHE with a large integer message space. Furthermore, if the underlying PKE is multiplicative, the proposed scheme has the advantage that polynomials of arbitrary degree can be evaluated without bootstrapping. We construct this scheme by concatenating the ElGamal and Goldwasser-Micali schemes over a ring ℤ <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">N</sub> for a composite integer N whose message space is ℤ <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">N</sub> <sup xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">×</sup> . To accelerate the homomorphic evaluation of the PKE decryption, we introduce a method to reduce the degree of the exponentiation circuit at the cost of additional public keys. Using the same technique, we present an efficient partial solution to an open problem which is to evaluate mod q mod p arithmetic homomorphically for large p. As an independent interest, we also obtain a generic method for converting from private-key SHE to public-key SHE. Unlike the method described by Rothblum, we are free to choose the SHE message space.

Cofactor Sharing for Reversible Logic Synthesis

Improving circuit realization of known quantum algorithms by CAD techniques has benefits for quantum experimentalists. In this article, the problem of synthesizing a given function on a set of ancillea is addressed. The proposed approach benefits from extensive sharing of cofactors among cubes that appear on function outputs. Accordingly, it can be considered a multilevel logic optimization technique for reversible circuits. In particular, the suggested approach can efficiently implement any n -input, m -output lookup table (LUT) by a reversible circuit. This problem has interesting applications in the Shor's number-factoring algorithm and in quantum walk on sparse graphs. Simulation results reveal that the proposed cofactor-sharing synthesis algorithm has a significant impact on reducing the size of modular exponentiation circuits for Shor's quantum factoring algorithm, oracle circuits in quantum walk on sparse graphs, and the well-known MCNC benchmarks.

CMOS automatic gain control circuit with DC offset cancellation for FM/cw ladar

This paper presented an automatic gain control (AGC) circuit suitable for FM/cw ladar. The proposed architecture was based on two-stage variable gain amplifier (VGA) chain with a novel DC offset canceller circuit, which contained an improved Gilbert cell and a Gm-C feedback loop. To keep the VGA with a linearity in dB characteristic, an improved exponential gain control circuit was introduced. The AGC was implemented in 0.18 μm standard CMOS process. Simulation and measurement results verified that its gain ranged from −20 dB to 30 dB, and bandwidth ranged from 100 kHz to 10 MHz. Its power consumption was 19.8 mW under a voltage supply of 3.3 V.

Fast quantum modular exponentiation architecture for Shor's factoring alogrithm

We present a novel and efficient, in terms of circuit depth, design for Shor's quantum factorization algorithm. The circuit effectively utilizes a diverse set of adders based on the Quantum Fourier transform (QFT) Draper's adders to build more complex arithmetic blocks: quantum multiplier/accumulators by constants and quantum dividers by constants. These arithmetic blocks are effectively architected into a quantum modular multiplier which is the fundamental block for the modular exponentiation circuit, the most computational intensive part of Shor's algorithm. The proposed modular exponentiation circuit has a depth of about $2000n^2$ and requires $9n+2$ qubits, where $n$ is the number of bits of the classic number to be factored. The total quantum cost of the proposed design is $1600n^3$. The circuit depth can be further decreased by more than three times if the approximate QFT implementation of each adder unit is exploited.

Factoring 51 and 85 with 8 qubits

We construct simplified quantum circuits for Shor's order-finding algorithm for composites N given by products of the Fermat primes 3, 5, 17, 257, and 65537. Such composites, including the previously studied case of 15, as well as 51, 85, 771, 1285, 4369, … have the simplifying property that the order of a modulo N for every base a coprime to N is a power of 2, significantly reducing the usual phase estimation precision requirement. Prime factorization of 51 and 85 can be demonstrated with only 8 qubits and a modular exponentiation circuit consisting of no more than four CNOT gates.

Low-voltage CMOS current-mode exponential circuit with 70 dB output dynamic range

The paper proposes new accurate exponential circuits, having a multitude of practical applications in analog signal processing. The original method for obtaining the exponential function is based on the utilization of new superior-order approximation functions. The accuracy of the proposed structures is excellent and the output dynamic range is strongly extended as a result of the fourth-order approximation and of the independence of implemented function on technological errors and on temperature variations (the best original proposed architecture of the exponential generator has an output dynamic range of 70dB for an approximation error smaller than ±1dB). The exponential circuits are designed for implementing in 0.18µm CMOS technology, having a low-voltage operation (a minimal supply voltage of 1V). The power consumptions of the proposed exponential circuits are smaller than 0.08mW, for a supply voltage of 1V. As application of the new exponential circuit, a dB-linear VGA circuit with high output dynamic range will be presented. The new computational structures have the possibility of generating any continuous mathematical function, presenting also an increased modularity and controllability and reduced design costs per implemented function.

A WIDEBAND CMOS CASCADED VARIABLE GAIN AMPLIFIER USING UNEQUALLY DISTRIBUTED GAIN CONTROL FOR DVB-S.2 RECEIVER

A fully integrated three stage cascaded radio frequency variable gain amplifier (RFVGA) linearly controlled by exponential current generation circuit is presented. The gain control is unequally distributed in each stage for noise figure (NF) and linearity performance. The dB-linear gain control is realized using pseudo exponential current generated by CMOS current summing circuit with a voltage to current converter. The RFVGA has over 50 dB dynamic range. Gain changes from -38.5 to 16.8 dB according to control voltage that varies from 0.5 to 1.8 V. It operates at 0.95–2.15 GHz. This design is implemented in 0.18 μm CMOS technology.

Some Quantum States Prepared with Polynomial Quantum Circuit

The quantum state preparation involved in quantum information processing greatly depends on the quantum computer models. In this paper we give a novel scheme for some quantum states preparation without any decomposition of global quantum gates. Our circuit reduces the exponential CNOT gates to polynomial of qubit numbers, i.e., n(n−1)/2 without requirements of quantum register. And the depth is changed from the currently known exponential circuits to n blocks, or polynomial for its detailed implementation. This method is also useful for multi-level quantum systems and expected to help in designing and building large-scale quantum applications using present physical technologies.

Design of CMOS current-controlled-gamma corrector

Abstract A high speed and low power CMOS current-mode current-controlled-gamma corrector composed of three approximating natural logarithm circuits and two approximating exponential circuits is proposed. By using companding design with only 17 transistors, we implement a low power and high speed current-controlled-gamma corrector. The gamma corrector was fabricated using a 0.35 μm CMOS technology. The measured bandwidth of the circuit could reach 120 MHz for an input range from 40 μA to 120 μA with a maximum power dissipation of only 1.18 mW.