Excimer Laser Crystallization Research Articles

Micro-Nano Fabrication of Self-Aligned Silicon Electron Field Emitter Arrays Using Pulsed KrF Laser Irradiation

Self-aligned silicon micro-nano structured electron field emitter arrays were fabricated using pulsed krypton fluoride (KrF) excimer laser crystallization (ELC) of hydrogenated amorphous thin silicon films (a-Si:H) on metal coated backplane samples. We investigate the effect of laser processing parameters on the growth of micro-nano conical structures on the surface of the thin silicon films. Randomly oriented conical structures as high as 1 µm were fabricated using laser pulse frequency of 100 Hz and sample stage scanning speed of 0.25 mm/sec. Best field emission (FE) results were measured from samples with the highest surface features with FE currents in the order of 10−6 A and low turn-on emission threshold of ∼14 V/µm. Light emission from the prototype demonstrators was tested using bespoke driver electronics and planar anodes coated with indium tin-oxide (ITO) and medium voltage FE phosphors, to exemplify their usage for future flat panel display technologies.

(Invited) Technology Trend of Poly-Si TFT from Viewpoints of Crystallization and Device Performance

Thin-film transistors (TFTs) utilizing the Low-Temperature Polycrystalline-Si (LTPS) as their active areas are very crucial for the system-on-glass (SOG). The liquid-crystal display (LCD) or organic light emitting diode display are fabricated in the display area and their controls are performed by the micro-computer that is formed in the peripheral area. The application of high-performance poly-Si TFTs to the high-definition LCD light valves for projectors was reported for the first time[1]. Therefore, the requirements for the recrystallized Si film are a high quality, a large grain formation and a position control of the nucleation. To satisfy those requirements, a super lateral growth (SLG)[2] using the excimer laser annealing (ELA), a phase-modulated ELA[3], a solid-phase crystallization followed by ELA[1], a low-temperature solid-phase excimer laser crystallization[4], a Pd:YAG laser crystallization[5], a soft X-ray crystallization (SXC)[6] have been studied. For the device structure, the double gate TFT[7] and the tunnel TFT[8] have been developed. In our group, the low-temperature crystallization methods and the novel TFT utilizing tunnel effect have been researched. Low-temperature crystallization: For the ELA method, the mechanism of multi-pulse ELA crystallization has been clarified and a large grained film with a high-quality[4] was provided. In addition, hydrogens in a-Si film greatly influenced the crystallinity and grain size of the poly-Si[9,10] and we discovered the advantage in ELA of hydrogen–modulation-doped a-Silicon Layer[11]. For the SXC, a low-temperature crystallization of a-Si, Ge and SixGe1-x film was researched and developed using the short undulator as a light source. The fundamental process of the SXC-method is a local excitation of core electrons to vacuum level by photons followed by the atom movement due to the Coulomb repulsion, which results in the lower temperature process. The SXC-method reduced the threshold temperature of crystallization for a-Si, Ge and SixGe1-x film by 100 - 150 degree C as compared with the conv. thermal crystallization. Novel TFT: Although the high-performance TFT with the high carrier mobility and low leakage current utilizing the large single crystalline grains has been intensively researched, it does not successfully operates from the productive viewpoint[12]. Tunneling Dielectric Thin-Film Transistor (TDTFT) was proposed and fabricated in a bottom-gate structure. Using a 1.7-nm-thick SiNx film, it reduced the gate-off current less than 1/10 in comparison with a conv. TFT. In addition, the TDTFT improved the hump effect as shown in Fig.1[13]. It is considered that the fixed charge in the SiNx film suppresses the formation of the parasitic channel in the poly-Si edge by the Coulomb repulsion. We conclude that TDTFT will suitable as a candidate of the next generation TFT structure.

High-Performance Recessed-Channel Germanium Thin-Film Transistors via Excimer Laser Crystallization

This letter demonstrates the excimer laser crystallization (ELC) of germanium (Ge) thin films with the recessed-channel (RC) structure for high-performance p-channel Ge thin-film transistors (TFTs). Using ELC, large longitudinal grains with a single perpendicular grain boundary (GB) in the center of the recessed region were formed. This can be attributed to the lateral grain growth from un-melted Ge solid seeds in the thick region toward the complete melting recessed region during ELC. Consequently, the proposed p-channel RC-ELC Ge TFTs possessing large longitudinal grains without the perpendicular GB in the channel region exhibited a superior field-effect hole mobility of 447 cm2V−1s−1 with minor performance deviation.

Analysis of defects in low-temperature polycrystalline silicon thin films related to surface-enhanced Raman scattering

The analysis of Raman scattering (RS) spectroscopy is presented for low-temperature polycrystalline silicon (poly-Si) thin films on glass substrates fabricated by excimer laser crystallization. In this material, RS is enhanced by specific protrusions at the grain boundary (GB). As a result, the Si lattice mode predominantly reflects the characteristics of GB and its neighborhood. A combination of low-damage hydrogenation and RS analysis enables the detection of lattice defects as Si–hydrogen (H) local vibration modes (LVMs). The characteristics of LVMs peculiar to this material are examined by chemical etching and postannealing. One of the dominant LVMs centered at ∼2000 cm−1 is assigned to H-terminated dangling bonds in the amorphous structures at GB, which is also enhanced by protrusions. The other dominant band centered at ∼2100 cm−1 is attributed to the strained Si–Si lattice near the Si/underlayer interface in grains that is broken and stabilized by extrinsic H atoms.

Formation and characterization of high-performance silicon thin-film transistors with and without location-controlled grain boundary

This paper reports the demonstration of structural effects on excimer laser crystallization (ELC) for the Si strip with a recessed-channel structure on the silicon nitride under-layer (RCS-ULN). We revealed that a single location-controlled grain boundary (GB) oriented normal to the Si strip in the middle site without any other GB in the recessed region can be attained via ELC for the RCS-ULN structures with a short recessed region between neighboring long thick regions in a narrow Si strip. This can be attributed to the effective production of a significant 2D lateral thermal gradient in the recessed region and neighboring thick regions. Consequently, the RCS-ULN TFTs fabricated at the position one-half of such an optimal recessed region can achieve a superior field-effect mobility of 670 with minor performance variations since the single-crystal-like Si channel has been adopted.

Analysis of polydihydrosilane crystallization by excimer laser annealing

Printing of electronics has been gaining a lot of attention over the past decade as a low cost alternative to conventional electronic fabrication methods. A significant development in this area was the possibility to print a silicon precursor, polydihydrosilane, which can directly be transformed into polycrystalline silicon by an excimer laser treatment. Due to the limited laser heat diffusion, low-cost flexible substrates such as plastics and even paper could be used that typically have low thermal budgets. Since the silicon precursor is sensitive to ultraviolet light and may transform in a photochemical reaction, the question arises whether the excimer laser crystallization is predominantly photochemical or rather a thermal reaction. In this work, a model is developed and reflected to experimental data, to understand the physics behind the process. Through finite-element analysis and experimental characterizations it was observed that the physics behind the process was predominantly thermal, and that instead of an intermediate transition to a-Si, a direct transformation to poly-Si exists. By understanding this process, the treatment can be optimized or more efficient tools can be used that would enable a low cost production of high performing silicon devices.

High-performance p-channel thin-film transistors with lightly doped n-type excimer-laser-crystallized germanium films

High-performance polycrystalline-germanium (poly-Ge) thin-film transistors (TFTs) fabricated with lightly doped Ge thin films by excimer laser crystallization (ELC) and counter doping (CD) have been demonstrated. High-quality n-type Ge thin films with a grain size as large as 1 µm were fabricated by ELC in the super lateral-growth regime and CD at a dose of 1 × 1013 cm−2 or higher. Consequently, a superior field-effect mobility of 271 cm2 V−1 s−1 and a high on/off current ratio of 2.7 × 103 have been obtained for p-channel Ge TFTs with the channel width and length of both 0.5 µm fabricated by ELC at 300 mJ/cm2 and CD at a dose of 1 × 1013 cm−2. The effects of ELC conditions and CD dose on the electrical characteristics of p-channel Ge TFTs were also investigated.

Location-Controlled Single-Crystal-Like Silicon Thin-Film Transistors by Excimer Laser Crystallization on Recessed-Channel Silicon Strip With Under-Layered Nitride

High-performance Si thin-film transistors (TFTs) on the recessed-channel Si strips with the under-layered nitride film have been fabricated using excimer laser crystallization (ELC). A nitride film was added as a light absorption layer to suppress solidification along the edge of the Si strip. Thus, only one primary grain boundary perpendicular to the Si strip formed in the middle of the recessed region during ELC. The single-crystal-like Si TFTs fabricated on one-half of the recessed region are capable of excellent field-effect mobility of 640 cm2/V-s, with only minor deviation.

Microsecond Crystallization of Amorphous Silicon Films on Glass Substrates by Joule Heating

Large area crystallization of amorphous silicon (a-Si) thin-films on glass substrates is one of the key technologies for manufacturing flat displays on commercial scales. Low-temperature polycrystalline silicon (LTPS) is a crucial active-layer material for polycrystalline silicon thin-film-transistors (poly-Si TFTs) mounted on thermally susceptible glass substrates. LTPS-TFT backplanes are required for fabricating flat panel displays such as active-matrix liquid-crystal-displays and active-matrix organic-light-emitting diodes (AMOLEDs). The LTPS-TFT backplanes are strongly preferred over a-Si TFTs since several devices, AMOLEDs in particular, operate in a current-driven mode. The crystallization methods used for producing LTPS include solid phase crystallization, metal induced crystallization, and excimer laser crystallization (ELC). The ELC method is currently used for crystallizing the a-Si films in mass production lines. Recently, we developed a novel and highly promising crystallization method named Joule-heating induced crystallization (JIC) by which an entire a-Si film could be crystallized on a glass backplane within tens of microseconds. However, arc instability was observed during the crystallization, which is attributed to the dielectric breakdown in the conductor/insulator/a-Si sandwich-structures at high temperatures during electrical pulsing for crystallization. We devised a method for crystallizing the a-Si films while preventing arc generation; in this method an a-Si active layer was pre-patterned into islands followed by the deposition of a gate oxide and gate electrode. An electric pulse was then applied to the gate electrode formed using a Mo layer. The Mo-layer was used as a Joule-heat source for the crystallization of the pre-patterned active islands of the a-Si films located below the Mo-layer. The JIC-processed poly-Si TFTs were fabricated successfully and the proposed method was found to be compatible with the standard processing of coplanar top-gate poly-Si TFTs. In this report, we will discuss some critical issues concerning the arc generation, glass backplane deformation, and phase-transformation phenomena observed during the JIC process on the basis of theoretical investigations as well as in-situ and ex-situ experiments. Finally, we will discuss the procedure for fabricating stable JIC poly-Si TFTs and optimize the process flow and processing conditions such as the power density and pulsing time for fabricating the JIC poly-Si TFTS. Figure 1

(Invited) Self-Aligned Four-Terminal Low-Temperature Polycrystalline-Silicon Thin-Film Transistors on Glass Substrate Using Continuous-Wave Laser Lateral Crystallization

Low-temperature (LT) polycrystalline-silicon (poly-Si) thin-film transistors (TFTs) are indispensable for applications that involve integrating high-speed and low-power dissipation complementary metal-oxide-semiconductor (CMOS) circuits onto a glass substrate. The on-current of the LT poly-Si TFTs can be enhanced by fabricating a high-quality poly-Si film on the glass substrate. In the current study, the fabrication of these transistors was achieved using continuous-wave laser lateral crystallization (CLC). This method enabled us to form a lateral poly-Si film with high quality and large grain size (the grain area was approximately 100 times larger than that of the conventional excimer-laser crystallization (ELC) poly-Si film) without damaging the substrate. A possible approach to achieve low-power dissipation is by controlling the threshold voltage (Vth). In order to control the Vth of the LT poly-Si TFTs, we fabricated self-aligned four-terminal (4T) LT poly-Si TFTs using high-quality CLC poly-Si film. These TFTs comprise metal gates on the top and bottom. The bottom metal gate was embedded in the glass substrate using a chemical mechanical polish. The top metal gate was fabricated by a self-aligned process of back surface exposure using the bottom metal gate as a photomask. This TFT was fabricated on a fused quartz glass at 550°C. The top and bottom metal gates acted as drive and control gates, respectively, or vice versa. The performance of the fabricated n-channel (n-ch) and p-channel (p-ch) self-aligned 4T CLC LT poly-Si TFTs was evaluated. To evaluate their feasibility, an E/D inverter was utilized by connecting two identical n-ch TFTs on different glass substrates, which were fabricated by identical processes.The self-aligned 4T CLC LT poly-Si TFTs showed excellent Vth controllability. The variation of the Vth of the drive gate TFT, with respect to small variation in the control gate voltage, was found to closely match the theoretically predicted values of the top and bottom gate drives for both n- and p-ch TFTs. The output characteristics of the drive TFTs were found to be sensitive to the varying magnitude of the control gate voltage. The mobility of the n-ch TFTs in the top and bottom drive TFTs was above 300 cm2/Vs. This remarkable performance may be attributed to the high-quality CLC poly-Si film. The mobility varied sensitively against the strength of the vertical electric field, which was changed by varying the control gate voltage. The s.s. values were also found to vary depending on the control gate voltage, and this variation is explained by the change in the position of the channel layer towards the side of either the drive or the control gate. By exploiting the high controllability of the 4T TFTs, an E/D inverter was fabricated and successfully operated at 2.0 V. The Vth of the self-aligned 4T CLC LT poly-Si TFTs was found to be sensitive to a 20-meV variation of the control gate voltage. Utilizing this sensitivity, we further fabricated an extended-gate pH sensor, where the control gate was connected to the glass electrodes, and the pH of the solution varied from 4.1 to 8.8. Consequently, we were able to successfully observe the variation of the drain current in the drive gate TFT depending on the strength of pH. In summary, the results suggest that the high controllability of the self-aligned 4T CLC LT poly-Si TFTs could enable us to fabricate high-speed and low-power-dissipation circuits on a glass substrate. Further, our study suggests the promising potential of such TFTs for applications involving sensor fabrication.

High-performance p-channel polycrystalline-germanium thin-film transistors via excimer laser crystallization and counter doping

High-quality polycrystalline-germanium (poly-Ge) thin films have been successfully fabricated by excimer laser crystallization (ELC). Grains as large as 1 µm were achieved by ELC at 300 mJ/cm2. Meanwhile, the defect-generated hole concentrations in Ge thin films were significantly reduced. Furthermore, the majority carriers could then be converted to n-type by counter doping (CD) with a suitable dose. Then, high-performance p-channel Ge thin-film transistors (TFTs) with a high on/off current ratio of up to 1.7 × 103 and a high field-effect mobility of up to 208 cm2 V−1 s−1 were demonstrated for a channel width and length both of 0.5 µm. It was revealed that ELC combined with CD is effective for attaining high-performance p-channel poly-Ge TFTs.

Sequential Lateral Solidification of Silicon Thin Films on Cu BEOL-Integrated Wafers for Monolithic 3-D Integration

We demonstrate that wafers integrated with copper (Cu) Damascene interconnects are suitable substrates for the excimer laser crystallization of silicon thin films. This approach allows for the monolithic 3-D integration of transistors on the back end of line (BEOL) of silicon wafers for VLSI monolithic 3-D integration. This is supported by a 1-D finite-element method simulation of the integrated structure, which shows that, upon excimer laser irradiation, the temperature of the buried Cu layer stays below 320 °C, which is a favorable condition for monolithic 3-D integration. The crystallization of a 100-nm amorphous silicon layer on a 1-μm SiO <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">2</sub> dielectric is demonstrated on a BEOL-integrated wafer. The Raman spectrum of the silicon layer after laser irradiation shows a polycrystalline peak centered around 513 cm <sup xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">-1</sup> . Optical microscopy shows polycrystalline silicon with no physical damage of the Cu lines. The electrical characterization of the Cu buried layer, with and without undergoing the irradiation process, shows no variation or degradation in Cu conductivity.

Zanesljiv način hitrega izračuna velikosti zrn v polikristalni tanki plasti po UV-laserski kristalizaciji

Zanesljiv način hitrega izračuna velikosti zrn v polikristalni tanki plasti po UV-laserski kristalizaciji

Excimer Laser Crystallization of Nanocrystalline Silicon Thin Films

Nanocrystalline silicon (nc-Si) thin film on glass substrate is subjected to excimer laser crystallized by varying the laser energy density in the range of 50~600 mJ/cm2. The effect of excimer laser crystallization on the structure of silicon film is investigated using Raman spectroscopy, X-ray diffraction, atomic force microscopy and scanning electron microscopy. The results show that polycrystalline silicon thin films can be obtained by excimer laser crystallization of nc-Si films. A laser threshold energy density of 200 mJ/cm2 is estimated from the change of crystalline fraction and surface roughness of the treated films. The growth of grain is observed and the crystallization mechanism is discussed based on the super lateral growth model. The nanocrystalline silicon grains in the films act as seeds for lateral growth to large grains.

Sequential lateral solidification of silicon thin films on low-k dielectrics for low temperature integration

We present the excimer laser crystallization of amorphous silicon on a low dielectric constant (low-k) insulator for very large scale integration monolithic 3D integration and demonstrate that low dielectric constant materials are suitable substrates for 3D integration through laser crystallization of silicon thin films. We crystallized 100 nm amorphous silicon on top of SiO2 and SiCOH (low-k) dielectrics, at different material thicknesses (1 μm, 0.75 μm, and 0.5 μm). The amorphous silicon crystallization on low-k dielectric requires 35% less laser energy than on an SiO2 dielectric. This difference is related to the thermal conductivity of the two materials, in agreement with one dimensional simulations of the crystallization process. We analyzed the morphology of the material through defect-enhanced microscopy, Raman spectroscopy, and X-ray diffraction analysis. SEM micrographs show that polycrystalline silicon is characterized by micron-long grains with an average width of 543 nm for the SiO2 sample and 570 nm for the low-k samples. Comparison of the Raman spectra does not show any major difference in film quality for the two different dielectrics, and polycrystalline silicon peaks are closely placed around 517 cm−1. From X-ray diffraction analysis, the material crystallized on SiO2 shows a preferential (111) crystal orientation. In the SiCOH case, the 111 peak strength decreases dramatically and samples do not show preferential crystal orientation. A 1D finite element method simulation of the crystallization process on a back end of line structure shows that copper (Cu) damascene interconnects reach a temperature of 70 °C or lower with a 0.5 μm dielectric layer between the Cu and the molten Si layer, a favorable condition for monolithic 3D integration.

Charge transfer of single laser crystallized intrinsic and phosphorus-doped Si-nanocrystals visualized by Kelvin probe force microscopy

Isolated intrinsic and phosphorus doped (P-doped) Si-nanocrystals (Si-NCs) on n- and p-Si substrates are fabricated by excimer laser crystallization techniques. The formation of Si-NCs is confirmed by atomic force microscopy (AFM) and conductive AFM measurements. Kelvin probe force microscopy (KPFM) is then carried out to visualize the trapped charges in a single Si-NC dot which derives from the charge transfer between Si-NCs and Si substrates due to their different Fermi levels. The laser crystallized P-doped Si-NCs have a similar Fermi level around the mid-gap to the intrinsic counterparts, which might be caused by the inactivated impurity atoms or the surface states-related Fermi level pinning. A clear rise of the Fermi level in P-doped Si-NCs is observed after a short time thermal annealing treatment, indicating the activation of dopants in Si-NCs. Moreover, the surface charge quantity can be estimated using a simple parallel plate capacitor model for a quantitative understanding of the KPFM results at the nanoscale.

A low‐cost dehydrogenation system of amorphous silicon thin films used for fabricating low‐temperature polycrystalline silicon

Low‐temperature polycrystalline silicon thin‐film transistors were widely employed in active‐matrix flat‐panel displays and giant microelectronics. In general, a‐Si thin films prepared by plasma‐enhanced chemical vapor deposition contain hydrogen. To prevent the ablation caused by sudden hydrogen eruption during excimer laser crystallization (ELC), two dehydrogenation systems are developed in this study to reduce hydrogen content before excimer laser crystallization. One is a ceramic heater‐based dehydrogenation system and the other is a quartz tube radiant heater‐based dehydrogenation system. The hydrogenated amorphous silicon (a‐Si : H) thin films prepared by plasma‐enhanced chemical vapor deposition are dehydrogenated by both systems. Fourier‐transform infrared absorption spectra revealed that the hydrogen content reduces after dehydrogenation processing. Raman measurements confirmed that the a‐Si : H thin films are still amorphous phase. The major potential advantages of quartz tube radiant heater‐based dehydrogenation system include rapid heating speed, good dehydrogenation quality, small footprint and low cost. Two‐steps temperature rise method is a good candidate for dehydrogenation processing because it provides sample with low thermal distortion.

Crystallization of Amorphous Silicon Films Using Joule Heating

Joule heat is generated by applying an electric filed to a conductive layer located beneath or above the amorphous silicon film, and is used to raise the temperature of the silicon film to crystallization temperature. An electric field was applied to an indium tin oxide (ITO) conductive layer to induce Joule heating in order to carry out the crystallization of amorphous silicon. Polycrystalline silicon was produced within the range of a millisecond. To investigate the kinetics of Joule-heating induced crystallization (JIC) solid phase crystallization was conducted using amorphous silicon films deposited by plasma enhanced chemical vapor deposition and using tube furnace in nitrogen ambient. Microscopic and macroscopic uniformity of crystallinity of JIC poly-Si was measured to have better uniformity compared to that of poly-Si produced by other methods such as metal induced crystallization and Excimer laser crystallization.

Bottom-Gate Thin-Film Transistors Fabricated by Excimer Laser Annealing

High performance and device uniformity n-channel low-temperature poly-silicon (LTPS) bottom-gate (BG) thin film transistors (TFTs) with artificially-controlled lateral grain growth have been performed by excimer laser crystallization (ELC). The BG TFTs (W/L = 1.5 μm/1.5 μm) demonstrate field-effect-mobility of 323 cm2/Vs and high Ion/Ioff of 9.5 × 108. The proposed BG TFTs reveal the superior electrical characteristics, device uniformity, and reliability than conventional top-gate ones.

Single-Grain Si TFTs Fabricated by Liquid-Si and Long-Pulse Excimer-Laser

Solution process of silicon using liquid-Si is attractive for fabrication of high-speed flexible electronics. We have fabricated single-grain Si TFTs on location-controlled Si grains with long-pulse excimer laser crystallization of spin-coated liquid Si film. The maximum grain diameter is 3.5μm, and the mobilities for electrons and holes are 423cm2/Vs and 118cm2/Vs, respectively.