Excess Loop Delay Compensation Research Articles

A Single Op-Amp Resonator-Based Continuous-Time Sigma–Delta Modulator With Time-Division Switching for Excess Loop Delay Compensation

A Single Op-Amp Resonator-Based Continuous-Time Sigma–Delta Modulator With Time-Division Switching for Excess Loop Delay Compensation

A 24-kHz BW 90.5-dB SNDR 96-dB DR continuous-time delta-sigma modulator using FIR DAC feedback

This paper presents a single bit continuous time delta-sigma modulator (CTDSM) with finite impulse response (FIR) feedback DAC designed for audio applications. By using FIR feedback in the input stage, the linearity requirements of the first integrator are relaxed, and the clock jitter sensitivity is reduced, as seen in a multi-bit quantizers. The choppers, working in conjunction with the FIR DAC, effectively suppresses in-band aliasing noise generated by the chopper in the first integrator. A fast comparator serves as a single-bit quantizer, and the 9.2% TS loop delay eliminates the need for excess loop delay compensation in the modulator. Energy efficient integrators are implemented using the current-starved OTA. The CTDSM prototype was fabricated using a 180-nm CMOS process, achieving a 90.5 dB SNDR and 96 dB DR with a 24 kHz signal bandwidth. The power consumption is 210 μ W, corresponding to a Schreier figure-of-merit value of 171.1 dB.

A Single-Opamp Third Order CT ΔΣ Modulator With SAB-ELD-Merged Integrator and Three-Stage Hybrid Compensation Opamp

This paper proposes a 3 <sup xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">rd</sup> order continuous-time delta-sigma modulator (CTDSM) with a single amplifier biquad (SAB) and excess loop delay (ELD) merged integrator. The integrator enables a 2 <sup xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">nd</sup> order noise-shaping together with ELD compensation with just a single Opamp and feedback DAC. A three-stage Opamp with a hybrid frequency-compensation scheme is presented, which achieves high gain and large unity-gain bandwidth (UGBW) with low power. The circuit secures an extra order noise-shaping through a passive noise-shaping SAR (NS-SAR) quantizer (QTZ) while further incorporating a preliminary sampling and quantization (PSQ) technique, the 1 <sup xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">st</sup> order NS QTZ can run at 1.5 GHz with 6b. The design, implemented in 28 nm, obtains 74.4 dB SNDR with 50 MHz bandwidth while consuming 10.4 mW from 1.5 V and 1 V power supplies. The prototype attains a dynamic range of 80.6 dB with a Schreier FOM of 171.2 dB. With the presented integrator and Opamp, the loop filter only consumes 14 % of the total DSM power consumption.

A 100-MHz BW 72.6-dB-SNDR CT Δ Σ Modulator Utilizing Preliminary Sampling and Quantization

This article reports a 4th-order 100-MHz bandwidth continuous-time (CT) delta–sigma modulator in 28-nm CMOS. A preliminary sampling and quantization (PSQ) technique is presented, which allows almost a full utilization of the clock period for the quantization to extend the available conversion time of the backend quantizer (QTZ) under a 0.65 excess loop delay (ELD) coefficient. With the PSQ, both the sampling and quantization of the backend QTZ are splitted into two steps, coarse and fine, similar to the subranging architecture to save power. The QTZ runs at 2 GHz achieving 7 bit (1 b error correction) with only 1.4-mW power. By adding a feedforward ELD compensation path in the cascade of integrators of the cascade of integrators in feedforward (CIFF) topology, only one digital-to-analog converter (DAC) is necessary in this design. The modulator attains a signal bandwidth of 100 MHz with 72.6-dB signal-to-noise and distortion ratio (SNDR) while only consuming 16.3 mW from 1.1- and 1.5-V power supplies. The prototype has a dynamic range of 76.3 dB and a Schreier FoM of 174.2 dB with an active area of 0.019 mm2.

Highly Digital Second-Order $\Delta\Sigma$ VCO ADC

A continuous-time second-order $\Delta \Sigma $ analog-to-digital converter (ADC) is presented in this paper. The proposed ADC is based on a novel architecture and uses current starved ring oscillators as integrators to achieve the second-order noise shaping. The proposed architecture does not require excess loop delay compensation or nonlinearity calibration. Static element mismatch in the multi-bit current digital-to-analog converter is high-pass shaped by intrinsic data-weighted averaging. Detailed analysis and insights on the various trade-offs involved in the design of the proposed ADC are presented in this paper. A prototype ADC is implemented in 65-nm CMOS and achieves 64.2-dB SNDR at a bandwidth of 2.5 MHz and a Schreier FoM of 158.2 dB. The ADC operates at 205 MHz and consumes 1 mW of power. The measured power supply rejection ratio is 56.2 dB.

A Highly Digital Second-Order Oversampling TDC

A second-order, single loop ΔΣ time-to-digital converter (TDC) is presented in this letter. The proposed TDC uses two differential current-controlled oscillators as phase domain integrators. The proposed architecture does not require excess loop delay compensation or nonlinearity calibration. Digital differentiation using XOR implements an intrinsic first-order high-pass shaping of static element mismatch in the current steering digital-to-analog converter. A prototype TDC in 65-nm CMOS process has linearity of 8.1 bits, integrated noise of 3.8 ps and energy efficiency of 0.45 pJ/code over a bandwidth of 2.5 MHz.

A Continuous-Time MASH 1-1-1 Delta–Sigma Modulator With FIR DAC and Encoder-Embedded Loop-Unrolling Quantizer in 40-nm CMOS

This paper presents a continuous-time multistage noise-shaping (MASH) delta–sigma modulator (CT- $\Delta \Sigma \text{M}$ ) employing finite impulse response (FIR) digital-to-analog converters (DACs) and encoder-embedded loop-unrolling (EELU) quantizers. The proposed MASH 1-1-1 topology is a cascade of three single-loop first-order CT- $\Delta \Sigma \text{M}$ stages, each of which consists of an active $RC$ integrator, a current-steering DAC, and an EELU quantizer. An FIR filter in the main 1.5-bit DAC improves the modulator’s jitter sensitivity performance. FIR’s effect on the noise transfer function of the modulator is compensated in the digital domain, thanks to the MASH topology. Instead of employing a conventional analog direct feedback path for excess loop delay compensation, a 1.5-bit EELU quantizer based on multiplexing comparator outputs is proposed; this approach is suitable for high-speed operation. Fabricated in a 40-nm low-power CMOS technology, the modulator’s prototype achieves a 67.3 dB of signal-to-noise-and-distortion ratio, 68 dB of signal-to-noise ratio, and 68.2 dB of dynamic range within 50.5 MHz of bandwidth, while consuming 19 mW of total power.

Time‐shifted excess loop delay compensation DAC for 2‐ T s delay in CT‐ΔΣ ADCs

This Letter proposes a new two-sample excess loop delay compensation in continuous-time delta-sigma modulators using time-shifted differentiated digital-to-analogue converter (DAC). This is done by using the information inherently available but ignored in the conventional methods, and therefore no additional hardware is required. Simulation results and mathematical analysis are provided to verify the effectiveness of the proposed structure.

A 10-b Fourth-Order Quadrature Bandpass Continuous-Time $\Sigma \Delta $ Modulator With 33-MHz Bandwidth for a Dual-Channel GNSS Receiver

A fourth-order quadrature bandpass continuous-time sigma–delta modulator for a dual-channel global navigation satellite system (GNSS) receiver is presented. With a bandwidth (BW) of 33 MHz, the modulator is able to digitalize the downconverted GNSS signals in two adjacent signal bands simultaneously, realizing dual-channel GNSS reception with one receiver channel instead of two independent receiver channels. To maintain the loop-stability of the high-order architecture, any extra loop phase shifting should be minimized. In the system architecture, a feedback and feedforward hybrid architecture is used to implement the fourth-order loop-filter, and a return-to-zero (RZ) feedback after the discrete-time differential operation is introduced into the input of the final integrator to realize the excess loop delay compensation, saving a spare summing amplifier. In the circuit implementation, power-efficient amplifiers with high-frequency active feedforward and antipole-splitting techniques are employed in the active RC integrators, and self-calibrated comparators are used to implement the low-power 3-b quantizers. These power saving techniques help achieve superior figure of merit for the presented modulator. With a sampling rate of 460 MHz, current-steering digital–analog converters are chosen to guarantee high conversion speed. Implemented in only 180-nm CMOS, the modulator achieves 62.1-dB peak signal to noise and distortion ratio, 64-dB dynamic range, and 59.3-dB image rejection ratio, with a BW of 33 MHz, and consumes 54.4 mW from a 1.8 V power supply.

A 10.2 mW multi-mode continuous-time ΔΣ ADC with 70–87 dB DR and 0.7–10 MHz bandwidth for TD-SCDMA and LTE digital receivers

This paper presents a low power and area-efficient 3rd-order continuous-time delta-sigma (CT ΔΣ) modulator for LTE/TD-SCDMA digital receivers. In the proposed modulator, the integrators' coefficients are programmable to meet all LTE and TD-SCDMA signal bandwidths and dynamic range requirements. Moreover, to meet both the high performance and low-cost requirements, the proposed analog-to-digital converter (ADC) adopts: a low-cost excess loop delay compensation method, a non-return-to-zero feedback digital-to-analog converter (DAC) which is clocked by low-noise LC phase lock loop, an on-chip tuning scheme to reduce sensitivity to bandwidth variations, and dynamic element matching 9-level DACs. The CT ΔΣ modulator is designed and fabricated in a 0.13 μm 1-poly 6-metal standard CMOS technology and occupies an active area of 0.20 mm2. For all signal bandwidths of LTE/TD-SCDMA standards, the proposed ADC achieves 70---87 dB dynamic range, and 66---84 dB peak SNDR with 8.4---10.2 mW power consumption under 1.5 V power supply.

A 10 MHz Bandwidth, 70 dB SNDR Continuous Time Delta-Sigma Modulator With Digitally Improved Reconfigurable Blocker Rejection

This paper presents a continuous-time third-order low-pass delta-sigma modulator (DSM) with digitally enhanced out-of-band (OOB) signal filtering for enhanced blocker rejection in receiver analog-to-digital converters (ADCs). It is well known that strong OOB interferers define the required dynamic range (DR) of a receiver. Usually, a channel-select filter (CSF) is therefore required, together with the succeeding ADC. The feedback-compensated DSM can relax the CSF with its signal transfer characteristic. In this work, this is improved with a reconfigurable digital filter, which modifies the feedback signal of the outer-loop DAC to increase the OOB blocker rejection of the modulator. As a proof of concept, the digitally improved blocker rejection is shown in a prototype design. Additionally, a reconfigurable excess loop delay compensation technique based on an adaptive delay-locked-loop (DLL) has been implemented. The prototype is realized in a 90 nm CMOS technology, works at 480 MHz clock frequency, requires an area of $0.17\;\text{mm}^2$ , and achieves an in-band (IB) SNDR of 70 dB in a bandwidth of 10 MHz with a power consumption less than 14.4 mW. In the prototype, a digitally reconfigurable blocker rejection is realized achieving 6 dB additional suppression from 20 or 40 MHz on, or even 25 dB at the specific frequency of 20 MHz.

Digital excess loop delay compensation technique with embedded truncator for continuous‐time delta–sigma modulators

A novel implementation is proposed to relax the specifications of the internal feedback path for a continuous-time delta–sigma modulator. A truncator is embedded into the digital excess loop delay (ELD) compensation path. Thermometer-coded truncation is achieved by re-ordering the reference voltages of the internal quantiser. This requires only a small amount of extra digital circuitry compared to the conventional digital ELD compensation. The digital encoder controlling the digital-to-analogue converter is simple, and it only introduces a small ELD.

Compensation method of the excess loop delay in continuous‐time delta‐sigma analog‐to‐digital converters based on model matching approach

Continuous-time (CT) delta-sigma (Δ∑) analog-to-digital converters (ADCs) have one important constrain, namely the excess loop delay. Most excess loop delay compensation methods need to know the exact value of the excess loop delay in advance. However, the value of the excess loop delay is a uniformly distributed random variable. To improve system performance with the same loop filter, a new compensation algorithm for the excess loop delay of CT Δ∑ ADCs based on the model matching method is presented in this study. Compared with previous compensation methods, the model matching algorithm is more practical because the value of the excess loop delay varies randomly every clock period. It is shown through simulation that a mean value based algorithm can improve the SQNR performance of CT Δ∑ ADCs for the most probable values of the excess loop delay.

A 4.5 mW CT Self-Coupled &lt;formula formulatype="inline"&gt;&lt;tex Notation="TeX"&gt;$\Delta\Sigma$&lt;/tex&gt;&lt;/formula&gt; Modulator With 2.2 MHz BW and 90.4 dB SNDR Using Residual ELD Compensation

This paper presents a power-efficient single-loop continuous-time (CT) $\Delta\Sigma$ modulator (DSM) that achieves a SNDR of 90.4 dB over a 2.2 MHz signal bandwidth. The modulator uses a fourth-order feed-forward architecture incorporating the continuous-time self-coupling (CTSC) technique. Moreover, to reduce hardware area, this design utilizes the residual signal for excess loop delay (ELD) compensation. To improve linearity, low-ripple DAC latches and low toggle-rate dynamic element matching (DEM) algorithm are adopted. This DSM is fabricated in a 55 nm LP CMOS technology. Operating at 140 MHz sampling rate, the chip consumes 4.5 mW from power supplies of 1.2 V and 1.8 V. It achieves 90.4 dB SNDR and 92 dB dynamic range (DR) with a 2.2 MHz signal bandwidth, resulting in a Schreier FOM of 177.3 dB and 178.9 dB based on SNDR and DR, respectively. The chip area is 0.09 mm $^{2}$ .

A 0.022 mm&lt;formula formulatype="inline"&gt;&lt;tex Notation="TeX"&gt;$^{{2}}$&lt;/tex&gt;&lt;/formula&gt; 98.5 dB SNDR Hybrid Audio &lt;formula formulatype="inline"&gt;&lt;tex Notation="TeX"&gt;$\Delta \Sigma$&lt;/tex&gt;&lt;/formula&gt; Modulator With Digital ELD Compensation in 28 nm CMOS

This work presents a compact-area hybrid continuous-time delta-sigma modulator (CTDSM) with a shared 6 bit asynchronous successive approximation register (ASAR) quantizer for audio application. It is implemented in a 28 nm CMOS process. The modulator incorporates an analog integrator and a digital filter. Signal is digitized after the analog first stage and processed digitally thereafter. Only the first stage is left in the analog domain. Because of high integration of digital circuitry, it could benefit from process advancement such as low power consumption and small area. Moreover, the excess loop delay (ELD) is compensated in the digital domain, and the conventional analog local feedback DAC for ELD compensation is no longer needed. In addition, resistive DAC (R-DAC) is adopted for low flicker noise. The measured DR and SNDR in 24 kHz BW are 100.6 dB and 98.5 dB, respectively, while occupying 0.022 mm 2 and achieving FOMs (SNDR + 10 $*$ log(BW/Power)) of 171.8 dB.

Digital excess loop delay compensation for high speed delta–sigma modulators

A digital excess loop delay (ELD) compensation suited for high speed delta–sigma modulators is presented. Its operation is based on computing the digital outputs for all the possible values of the ELD compensation feedback and performing the selection in the digital domain. The proposed technique also uses a novel comparator sharing approach which minimises the number of comparators needed in the quantiser.

A Continuous-Time Delta-Sigma Modulator for Biomedical Ultrasound Beamformer Using Digital ELD Compensation and FIR Feedback

This paper presents the design of a continuous-time ΔΣ modulator (CTDSM) to be used in an ultrasound beamformer for biomedical imaging. To achieve better resolution, the prototype modulator operates at 1.2 GHz. It incorporates a digital excess loop delay (ELD) compensation to replace the active adder in front of the internal quantizer. A digitally controlled reference-switching matrix, combined with the data-weighted averaging (DWA) technique, results in a delay-free feedback path. A multi-bit FIR feedback DAC, along with its compensation path, is used to achieve lower clock jitter sensitivity and better loop filter linearity. The modulator achieves 79.4 dB dynamic range, 77.3 dB SNR, and 74.3 dB SNDR over a 15 MHz signal bandwidth. Fabricated in a 65 nm CMOS process, the core modulator occupies an area of only 0.16 mm <sup xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">2</sup> and dissipates 6.96 mW from a 1 V supply. A 58.6 fJ/conversion-step figure of merit is achieved.

An NTF-enhanced time-based continuous-time sigma-delta modulator

Translation of the amplitude axis to the time axis can be a promising approach to alleviate the analog-to-digital converter's resolution problems in low-voltage CMOS circuits. From this point of view, a noise-coupled time-based continuous-time sigma-delta modulator (TCSDM) based on the asynchronous pulse width modulator (APWM) and the time-to-digital converter (TDC) is presented. Noise-coupling is realized by extracting the time quantization error of the TDC and injecting its delayed version to the input of the APWM. By using a novel implementation of the noise-coupling technique in the proposed TCSDM, the modulator's noise-shaping order is improved by one. Unlike the conventional noise-coupled sigma-delta modulators, in the proposed structure, the need of an extra subtractor at the quantizer input is resolved through merging the excess loop delay compensation path with the proposed noise-coupling branch. Comparative analytical calculations and behavioral simulation results are presented to verify the performance of the proposed time-based modulator. To confirm the validity of the proposed structure, the effects of main circuit non-idealities in the modulator's performance are taken into consideration and the related simulation results are investigated. A digital-friendly implementation of the quantizer in the proposed modulator makes it suitable for low-voltage nanometer CMOS technologies.

A 23 mW, 73 dB Dynamic Range, 80 MHz BW Continuous-Time Delta-Sigma Modulator in 20 nm CMOS

This paper presents a continuous-time ΔΣ modulator targeted at optimizing power efficiency for input bandwidth exceeding 50 MHz. Delay in the feedback path is carefully minimized and traditional techniques for DAC mismatch correction and excess loop delay compensation are both replaced with digital schemes. Power is also minimized by relaxing loop filter BW requirements and using a power efficient opamp topology. The modulator achieves 73 dB dynamic range (DR) in 80 MHz BW while consuming 23 mW. The peak SNR is 70 dB and the peak SNDR is 67.5 dB, resulting in FOMs of 168 dB and 163 dB based on DR and SNDR, respectively.

A power‐area‐efficient, 3‐band, 2‐RX MIMO, TD‐LTE receiver with direct‐coupled ADC

SummaryIn this work, a power‐area‐efficient, 3‐band, 2‐RX MIMO, and TD‐LTE (backward compatible with the HSPA+, HSUPA, HSDPA, and TD‐SCDMA) CMOS receiver is presented and implemented in 0.13‐μm CMOS technology. The continuous‐time delta‐sigma A/D converters (CT ∆Σ ADCs) are directly coupled to the outputs of the transimpedance amplifiers, eliminating the need of analog anti‐aliasing filters between RX front‐end and ADCs in conventional structures. The strong adjacent channel interference without low‐pass filter attenuation is handled by proper gain control. A low‐power small‐area solution for excess loop delay compensation is implemented in the CT ∆Σ ADC. At 20 MHz bandwidth, the CT ∆Σ ADC achieves 66 dB dynamic range and 3.5 dB RX chip noise figure is measured. A maximum of 2.4 dB signal‐to‐noise ratio degradation is measured in all the adjacent channel selectivity (ACS) and blocking tests, demonstrating the effectiveness of the strategy against the low‐pass filter removal from the conventional architecture. The receiver dissipates a maximum of 171 mW at 2‐RX MIMO mode. To our best knowledge, it is the first research paper on the design of fully integrated commercial TD‐LTE receiver. Copyright © 2014 John Wiley &amp; Sons, Ltd.