Excess Drain Research Articles

Россия и глобальный водный кризис

Currently, many countries are experiencing a growing shortage of freshwater resources. Aggravation of such situation will have impact on economy and political situation in the countries which do not suffer from water deficiency. So, in the foreseeable future the world may face a global water crisis. The only way to prevent it is to develop new reserves of available water resources and their transborder supplies through formation of international market of fresh water resources and the interregional systems of water logistics. For water exporting countries this will bring not only economic benefits bur greater geopolitical significance. The Russian Federation possesses large reserves of fresh water in great Siberian Rivers that regularly cause catastrophic floods. Projects of transferring part of excess drain (runoff) to arid Central Asian republics were discussed in late years of the USSR. But these projects struck upon indignation of the local ecologically-minded public (ecologists). Since then the Russian Federation does not consider such projects. The author insists that the approach to this problem should to be reconsidered in the light of most recent climate-related events that substantiate the positions of those scientists who forecast a global water crisis until 2050. Active participation in formation of the international market of fresh waters resources has to be included into foreign policy agenda of the Russian Federation. In other words, this country needs to develop its own water diplomacy directed at protection of national interest in this increasingly unstable world – similarly to the experience of some foreign powers. The purpose is to achieve mutually advantageous international agreements on interregional supplies of fresh water. The main obstacle is the resistance of the local ecologists who maintain outdated stereotypes. The situation may be changed by dissemination of proper information on the issue, primarily concerning national ecological interests for participation in international efforts to prevent global water crisis. The refusal of sale of excess volumes of fresh water to neighboring countries may lead to emergency situations there and, consequently, to a burst of illegal migration and even attempts to solve the problem by force.

Managing cholera in limited resource settings: the case of the Lusaka Cholera Epidemic of 2009-2010

Purpose is to illustrate that even with limited resources cholera can still be managed adequately to controllable levels which significantly reduce on the morbidity, mortality and excess drain on resources.
 Material and methods: A situational analysis was made upon whose basis interventions were constituted. These included contact tracing, social marketing and behavioral intervention. Communities were engaged on cholera and their contribution towards its negative impact and how they could help ameliorate the situation.
 Active intervention was done on the stagnant pools of water and to kill the cholera bug.
 Results: There was significant reduction in cholera cases which came down to zero over the three years that the interventions were instituted.
 Conclusion: Even in resource-limited settings, cholera can still be managed adequately if worked on proactively.

Managing Cholera in Limited Resource Settings

Purpose is to illustrate that even with limited resources cholera can still be managed adequately to controllable levels which significantly reduce on the morbidity, mortality and excess drain on resources. Material and methods
 A situational analysis was made upon whose basis interventions were constituted. These included contact tracing, social marketing and behavioral intervention. Communities were engaged on cholera and their contribution towards its negative impact and how they could help ameliorate the situation.
 Active intervention was done on the stagnant pools of water and to kill the cholera bug.
 Results: There was significant reduction in cholera cases which came down to zero over the three years that the interventions were instituted.
 Conclusion: Even in resource-limited settings, cholera can still be managed adequately if worked on proactively.

Effects of Negative-Bias-Temperature-Instability on Low-Frequency Noise in SiGe ${p}$ MOSFETs

We have measured the low-frequency 1/ ${f}$ noise of Si0.55Ge0.45 ${p}$ MOSFETs with a Si capping layer and SiO2/HfO2/TiN gate stack as a function of frequency, gate voltage, and temperature (100–440 K). The magnitude of the excess drain voltage noise power spectral density ( $\textit{S}_{ {vd}}$ ) is unaffected by negative-bias-temperature stress (NBTS) for temperatures below ~250 K, but increases significantly at higher temperatures. The noise is described well by the Dutta-Horn model before and after NBTS. The noise at higher measuring temperatures is attributed primarily to oxygen-vacancy and hydrogen-related defects in the SiO2 and HfO2 layers. At lower measuring temperatures, the noise also appears to be affected strongly by hydrogen-dopant interactions in the SiGe layer of the device.

Ampere Hour (Ah) as a Predictor of CRT ICD Pulse Generator Battery Longevity. A Multi-Center Study

CRT-D devices offer survival benefit in select NYHA class II-IV systolic heart failure patients with QRS >120ms and LVEF <35%. A limitation of 100% CRT pacing is excess battery drain, and earlier pulse generator (PG) replacement for CRT systems. CRT-D pulse generator change is associated with significant infection risk, morbidity, and cost. Ampere-hour or Ah measures residual PG battery capacity and may predict device longevity.

Analysis of the relationship between the kink effect and the indium levels in MOS transistors

Abstract In this work, we investigate the effects of indium ion implantation on the channel of nMOSFETs. Deep level transient spectroscopy (DLTS) and admittance spectroscopy (AS) measurements have been made on a series of indium doped silicon N+P structures and MOS capacitors. To analyse the indium-related levels in nMOSFETs, we used a low frequency (LF) output conductance dispersion analysis, which is based on the Gain-Phase versus frequency at different temperatures. These experiences show that the indium level when operated at low temperatures at which the majority of carriers freeze-out exhibit a kink effect. The effects of indium doping on the kink were studied using the variation of channel conductance gd and transconductance gm versus temperature in the kink zone. The excess drain current versus drain and gate voltage show the maximums of both conductance gd and transconductance gm at around T = 124 K when the indium level is activated.

Fluctuation analysis of an organic semiconductor–insulator interface

The space-charge region of an organic semiconductor (OS)-insulator interface is probed by analyzing the spontaneous, thermally driven drain current fluctuations of a field-effect transistor in which the OS forms the gate electrode. This so called "excess drain current noise" is the outcome of local fluctuations of the Fermi level, resulting from stochastic exchange of electrons between traps near the Fermi level. The power spectral density of this noise is characteristic of a Lorentzian process with a distribution of time constants, which is attributed to the disorder in the OS film. Furthermore, this disorder leads to local inhomogeneity of the work function in the film and a finite correlation length of the work function fluctuations. The measurement of work function noise is only possible within a correlation length of the OS-insulator interface. Through systematic variation of gate voltage, primary doping and secondary doping levels, the correlation length, disorder, and the trapping/de-trapping time constant are examined on polyaniline as a representative OS. A model is proposed for local work function variations and spontaneous charge-carrier fluctuations within polyaniline films with consequences for organic electronics using organic semiconductors.

Excess drain noise simulation in ultrathin oxides MOSFETs

This work presents a simple analytical model for the low frequency noise in ultrathin oxide MOSFETs of advanced bulk CMOS technology. The developed formulations of the gate leakage and drain current noise are based on a flat band voltage concept and analyzed with respect to noise measurements. Its proves very effective in describing the overall drain current noise as well as the gate current one. A special attention is given to the description of the huge excess drain noise experimentally observed in large area devices by sum of the both drain and gate current noise contributions using gate-partitioning coefficients. A comparison with a multi-dimensional macroscopic approach based on the calculation of the spectral density of current fluctuations implemented through the two-dimensional impedance field method is also presented.

Low frequency noise characterization and modelling in ultrathin oxide MOSFETs

This paper presents low frequency noise investigations in ultrathin oxide MOSFETs of advanced bulk CMOS technology. Simple analytical models for the drain and gate-leakage current noise are presented and analyzed with respect to noise measurements. The developed formulations of the different 1/ f noise sources are based on a flat band voltage concept and proves very effective in describing the overall drain current noise as well as the gate current one. In particular, the huge excess drain noise experimentally observed in large area devices is explained by sum of both drain and gate current noise contributions using gate-partitioning coefficients.

Body-Charge-Induced Switching Characteristics in Fully Depleted Silicon-on-Insulator Digital Circuits

Switching characteristics of digital circuits built with fully depleted (FD) silicon-on-insulator (SOI) metal–oxide–semiconductor field effect transistors (MOSFETs) are experimentally investigated. The results show that the switching speed depends on the input-signal frequency even in FD SOI digital circuits, though FD SOI MOSFETs are expected to suppress floating body effects. The switching becomes faster as the input-signal frequency decreases. This is because the body charge dynamically changes during the switching even in FD SOI MOSFETs. FD SOI MOSFETs have no neutral region in the body, while partially depleted (PD) MOSFETs do. Therefore, impact ionization plays a major role in changing the body charge in FD SOI MOSFETs, while charge redistribution does in PD SOI MOSFETs. The accumulation of majority carriers generated by impact ionization increases the body charge, and thus thereshold voltage decreases, which causes an excess drain current. This excess current is the reason for the faster switching in FD SOI digital circuits. Since the impact ionization efficiency decreases as the supply voltage decreases, the dependence of propagation delay time, tpd, on the input signal frequency can be largely reduced for FD SOI digital circuits. We also discuss several ways to efficiently decrease majority carriers accumulated in the body region and thereby minimize the dependence of tpd on the input-signal frequency for FD SOI digital circuits.

Effect of deep-level impurities on the drain characteristics of short-channel metal-semiconductor field effect transistors

The role of deep-level impurities in the drain characteristics of a short-channel metal-semiconductor field effect transistor has been investigated. The drain current of the device has been evaluated for different values of deep-level density and at different temperatures ranging from 300 to 400 K. The presence of deep levels gives rise to an excess drain current resulting from the electronic excitations from the defect levels. The increase in the temperature enhances the current due to increasing ionization of the defects. An analytical expression for the channel conductance is also derived and it is found to be a function of deep-level concentration besides other nonidealities such as interface states and interfacial oxide layer. The effect of gate length shortening also reveals significant changes in the current and conductance.

Bulk Breakdown in AlGaN/GaN HFETs

ABSTRACTA significant source current generated by a carrier multiplication process is observed at large drain voltages in the subthreshold regime, along with simultaneous increase of the gate current and light emission signal. Provided no on-surface premature breakdown takes place, a bulk channel avalanche breakdown process is proposed as the dominant breakdown mechanism for a large range of gate-to-source dc voltages. This process in the GaN channel is responsible for the excess source and drain currents, light emission, and excess gate current beyond its normal value measured in a gate-to-drain diode configuration. The role of the gate bias in controlling the channel vs. the gate breakdown mechanisms is described.

Reduction of kink effect in short-channel MOS transistors

A simple analysis of the kink effect in MOS transistors is proposed. This analysis enables a quantitative description of the excess drain current as a function of channel length to be obtained both at room and liquid-helium temperatures. More specifically, it is demonstrated that a reduction of the normalized kink effect Delta I/sub d//I/sub d/ /sub sat/ in short-channel MOS transistors arises from the combined effects of charge sharing and saturation velocity through the lowering of the depletion capacitance and the normalized saturation transconductance. >

Analysis of the kink effect in MOS transistors

An analysis of the kink effect in MOS transistors that provides a comprehensive view of the kink effect in bulk silicon MOSFETs and SOI devices is presented. This analysis enables a quantitative description of the excess drain current to be obtained for room and liquid-helium temperatures. In particular, it is found that the kink effect in a MOS transistor can be simply modeled by a body effect.< <ETX xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">&gt;</ETX>

Delta -doped FET with sidewall source and drain by atomic layer epitaxy

Summary form only given. The DC and RF performance of planar doped FET devices degrades severely due to parasitic source and drain excess resistances. The authors report a novel approach to reducing these parasitic resistances based on sidewall growth of source and drain using atomic layer epitaxy (ALE). The delta -doped structures were first etched to remove the undoped regions under the source and drain areas, followed by ALE sidewall regrowth at 450 degrees C. The regrown ALE GaAs film is 500 AA thick and has ten planes of Se atoms with equivalent carrier concentrations of 2*10/sup 19//cm/sup 3/. ALE allows the uniform regrowth of the sidewalls, since it proceeds at a monolayer/cycle irrespective of the orientation of the etched structure. The grown layer thus makes a direct contact to the channel of the delta -doped FET and reduces both R/sub s/ and R/sub D/. The performances of delta -doped FETs with the same ALE contacting layers were compared for both etched and nonetched structures. Even with nonalloyed sidewall source and drain contacts, the excess source and drain resistances were reduced by 30-40%. >

Excess drain current in heterojunction FETs due to substrate space-charge-limited current

A comparison of gated and ungated heterostructure FETs shows that high output conductance, poor pinchoff, and kinks in the I-V characteristics of heterojunction FETs (HFETs) are related to space-charge-limited conduction (SCLC) associated with deep traps in the substrate. The dominant trap level was determined from I-V measurements of an ungated structure as a function of temperature and the trap density was determined from SCLC characteristics. Reduction in excess drain current can be achieved by using a high trap concentration substrate and by increasing the electron barrier between the channel and the substrate. >

Performance analysis of sub-micron gate GaAs MESFETs

A novel 2-D numerical model incorporating nonstationary electron dynamics is used to investigate the complex transport phenomena governing the operation of sub-micron gate GaAs MESFET's. A detailed theoretical analysis of different phenomena observed in subhalf micron devices is given. These include velocity overshoot, stationary and travelling domain formation, soft pinch off, excess drain current etc. The small signal parameters g m , g d and C gs and their dependence on bias condition are evaluated. The effects of physical quantities such as mobility and interface barrier on carrier injection and transport and consequently on device performance are presented.

Influence of substrate freeze-out on the characteristics of MOS transistors at very low temperatures

The low temperatures current-voltage characteristics of N-channel MOS transistors have been analysed. An excess drain current is observed for intermediate values of drain voltage. This anomalous drain current is explained in terms of substrate freeze-out, since at very low temperatures the MOS structure has a type of floating substrate potential within the depletion region. Due to the increase of the majority carrier current, flowing through the substrate to the source at increasing drain voltage, this substrate potential increases and causes a change of threshold voltage. This change is observed in the current-drain voltage characteristics of the MOSFET. Various experiments, such as measurements of substrate current, effects of temperature, gate and substrate voltages, support this interpretation. MOS transistors with various geometries and various dopings are analysed.

A Precision Sample and Hold Circuit with Subnanosecond Switching

This paper is concerned with the analysis, design, and physical embodiment of a sample and hold circuit for use in a high speed, high performance (9-digit) PCM system. A precision bilateral gate employing gallium arsenide diodes is at the heart of the circuit. Subnanosecond recovery time, low capacitance (<1 pf), and large forward conductance characterize the gate diodes. Switching of the gate is accomplished at about a 12 Mc/sec sampling rate by a fast driver circuit. To prevent excess current drain from the signal source a constant current source is switched in by the driver to dominate charging of the holding capacitor when the difference between the input and held voltages is large. As the input and output signals approach correspondence, RC charging from the signal source predominates. The approximate dual mode operation of the gate permits a piecewise linear analysis applicable to transmission and switching performance. An equivalent block diagram for the sample and hold circuit is developed that contains linear filters and zero memory nonlinear networks. Nonlinear distortion is evaluated for a bandlimited white noise probe. To approach an over-all system performance limited largely by quantizing noise, the sample and hold circuit must be designed to introduce minimum signal impairment. This necessitates switching in less than one nanosecond and maintenance of the held waveform flat to within about one part in 5,000. Achievement of these difficult requirements is assured through careful analysis, design, and embodiment and has been verified by experiment.