Abstract
This paper is concerned with the analysis, design, and physical embodiment of a sample and hold circuit for use in a high speed, high performance (9-digit) PCM system. A precision bilateral gate employing gallium arsenide diodes is at the heart of the circuit. Subnanosecond recovery time, low capacitance (<1 pf), and large forward conductance characterize the gate diodes. Switching of the gate is accomplished at about a 12 Mc/sec sampling rate by a fast driver circuit. To prevent excess current drain from the signal source a constant current source is switched in by the driver to dominate charging of the holding capacitor when the difference between the input and held voltages is large. As the input and output signals approach correspondence, RC charging from the signal source predominates. The approximate dual mode operation of the gate permits a piecewise linear analysis applicable to transmission and switching performance. An equivalent block diagram for the sample and hold circuit is developed that contains linear filters and zero memory nonlinear networks. Nonlinear distortion is evaluated for a bandlimited white noise probe. To approach an over-all system performance limited largely by quantizing noise, the sample and hold circuit must be designed to introduce minimum signal impairment. This necessitates switching in less than one nanosecond and maintenance of the held waveform flat to within about one part in 5,000. Achievement of these difficult requirements is assured through careful analysis, design, and embodiment and has been verified by experiment.
Published Version
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