Excellent Electrostatic Discharge Robustness Research Articles

$\pi$ -SCR Device for Broadband ESD Protection in Low-Voltage CMOS Technology

Electrostatic discharge (ESD) protection design is needed for integrated circuits; however, the ESD protection devices near the I/O pad may cause negative impacts on the high-frequency performance. To achieve both excellent ESD robustness and good broadband performance, a silicon-controlled rectifier (SCR) with trigger diodes, a matching inductor, and a reversed diode to form a novel $\pi $ -SCR device is presented in this brief. As compared with the conventional $\pi $ -diode in silicon, the $\pi $ -SCR can reduce the clamping voltage during the critical positive-to- $V_{\text {SS}}$ (PS) ESD test, and the high-frequency performance is not seriously degraded (insertion loss $\pi $ -SCR device does not suffer the latch-up issue in low-voltage CMOS technology, and it has the potential to further reduce the clamping voltage during other ESD tests. Therefore, the novel $\pi $ -SCR device will be a good choice for broadband ESD protection in low-voltage CMOS technology.

Design of ESD Protection Diodes With Embedded SCR for Differential LNA in a 65-nm CMOS Process

The pin-to-pin electrostatic discharge (ESD) issue for a differential low-noise amplifier (LNA) was studied in this work. A new design of ESD protection diodes with an embedded silicon-controlled rectifier (SCR) was proposed to protect the gigahertz differential LNA. The proposed ESD protection design was modified from the conventional ESD protection design without adding any extra device. The SCR path was established directly from one differential input pad to the other differential input pad so the pin-to-pin ESD robustness can be improved. This design had been verified in a 65-nm CMOS process. Besides, this design had been further applied to a 24-GHz LNA in the same 65-nm CMOS process. Experimental results had shown that the proposed ESD protection design for the differential LNA can achieve excellent ESD robustness and good RF performances.

Correlation of reverse leakage current conduction mechanism and electrostatic discharge robustness of transient voltage suppression diode

Five transient voltage suppression (TVS) diodes with breakdown voltages (BV) of 6, 7, 11, 13 and 15 V have been developed using low-temperature (LT) epitaxy technology and an LT fabrication process. The electrostatic discharge (ESD) performance and temperature dependency of reverse leakage current are investigated by applying the IEC61000-4-2 (IEC) standard and an I-V-T analysis. The TVS diodes exhibited excellent ESD robustness, exceeding the standard ESD requirement of IEC level 4, 8 kV in contact discharge, while also maintaining the reverse leakage current level below 10−9 A. Excellent ESD performance was found to be relevant for lower breakdown voltage TVS diodes. The reverse leakage currents showed substantial changes in thermal activation energy from 0.43 to 0.6 eV with respect to BV control from 6 to 15 V. The increased activation energy at high BV was attributed to the transition of the conduction mechanism from tunneling mode to generation-recombination mode. The reduction of reverse leakage current from a generation-recombination to tunneling conduction mechanism is expected to improve the ESD performance of TVS diodes.

Effects of Electrostatic Discharge Stress on Current-Voltage and Reverse Recovery Time of Fast Power Diode

Fast recovery diodes (FRDs) were developed using the <TEX>$p^{{+}{+}}/n^-/n^{{+}{+}}$</TEX> epitaxial layers grown by low temperature epitaxy technology. We investigated the effect of electrostatic discharge (ESD) stresses on their electrical and switching properties using current-voltage (I-V) and reverse recovery time analyses. The FRDs presented a high breakdown voltage, >450 V, and a low reverse leakage current, < <TEX>$10^{-9}$</TEX> A. From the temperature dependence of thermal activation energy, the reverse leakage current was dominated by thermal generation-recombination and diffusion, respectively, at low and high temperature regions. By virtue of the abrupt junction and the Pt drive-in for the controlling of carrier lifetime, the soft reverse recovery behavior could be obtained along with a well-controlled reverse recovery time of 21.12 ns. The FRDs exhibited excellent ESD robustness with negligible degradations in the I-V and the reverse recovery characteristics up to <TEX>${\pm}5.5$</TEX> kV of HBM and <TEX>${\pm}3.5$</TEX> kV of IEC61000-4-2 shocks. Likewise, transmission line pulse (TLP) analysis reveals that the FRDs can handle the maximum peak pulse current, <TEX>$I_{pp,max}$</TEX>, up to 30 A in the forward mode and down to - 24 A in the reverse mode. The robust ESD property can improve the long term reliability of various power applications such as automobile and switching mode power supply.

Reverse Current Conduction Mechanism of Transient Voltage Suppression Diode under Electrostatic Discharge Stress

A transient voltage suppression (TVS) diode with abrupt junctions was fabricated using low-temperature epitaxy. The effect of electrostatic discharge (ESD) stress on the reverse leakage current conductive mechanism of the TVS diode was investigated using IEC61000-4-2 (IEC) standard analysis, in accordance with temperature-dependent current-voltage (I-V) characteristics. The fabricated TVS diode showed excellent ESD robustness, with negligible degradation up to «19.5 kV and failure at «20 kV stress. The ESD stress evidently led to the generation of shallow and deep defect states in the depletion region located 0.52­1.08 eV below the conduction band, and these states served as a main contributor to the resulting reverse leakage current. In devices to which IEC peak voltage stresses of less than «19.5 kV had been applied, reverse conduction was dominated by generation-recombination current; the application of the «20 kV failure stress caused reverse conduction to become dominated by a combination of tunneling current via deep defects and Poole-Frenkel barrier lowering. The proposed TVS can serve as a highly stable and reliable ESD protector of electronic components, serving an evolving need in nanoscale technology. [doi:10.2320/matertrans.M2014214]

Effects of Electrostatic Discharge Stress on Electrical Properties of Bidirectional TVS Zener Diode with Abrupt Junctions

A bidirectional transient voltage suppressor (TVS) Zener diode was fabricated with abrupt junctions using the low-temperature epitaxy process. The effects of various electrostatic discharge (ESD) stresses on the electrical properties are demonstrated, such as the current­voltage (I­V) and 1/f noise power spectral density (PSD). Very sharp and uniform bidirectional multi-junctions result in good symmetric I­V behavior over a wide range of operating temperatures of 300­450K. The differential resistance in the breakdown region is only 0.2 ³, and the reverse leakage current density is completely suppressed to 1.5 © 10 ¹4 A/m 2 . The thermal activation energy obtained from the Arrhenius plot is nearly equal to half the band gap of Si, indicating that the reverse leakage current is dominated by thermal generation at the depletion edges for the entire reverse bias regions. The manufacture bidirectional TVS devices exhibit excellent ESD robustness, regardless of the stress conditions of the human body model and electrical fast transient. However, a «4.5kV machine model and «13kV IEC61000-4-2 stresses led to severe damage of the epitaxially grown junction, resulting in rapid increases in both the reverse leakage current and 1/f noise PSD. [doi:10.2320/matertrans.M2013144]

Design of differential low-noise amplifier with cross-coupled-SCR ESD protection scheme

Abstract The pin-to-pin electrostatic discharge (ESD) stress was one of the most critical ESD events for differential input pads. The pin-to-pin ESD issue for a differential low-noise amplifier (LNA) was studied in this work. A new ESD protection scheme for differential input pads, which was realized with cross-coupled silicon-controlled rectifier (SCR), was proposed to protect the differential LNA. The cross-coupled-SCR ESD protection scheme was modified from the conventional double-diode ESD protection scheme without adding any extra device. The SCR path was established directly from one differential input pad to the other differential input pad in this cross-coupled-SCR ESD protection scheme, so the pin-to-pin ESD robustness can be improved. The test circuits had been fabricated in a 130-nm CMOS process. Under pin-to-pin ESD stresses, the human-body-model (HBM) and machine-model (MM) ESD levels of the differential LNA with the cross-coupled-SCR ESD protection scheme are >8 kV and 800 V, respectively. Experimental results had shown that the new proposed ESD protection scheme for the differential LNA can achieve excellent ESD robustness and good RF performances.

A 5-GHz Differential Low-Noise Amplifier With High Pin-to-Pin ESD Robustness in a 130-nm CMOS Process

Two electrostatic discharge (ESD)-protected 5-GHz differential low-noise amplifiers (LNAs) are presented with consideration of pin-to-pin ESD protection. The pin-to-pin ESD issue for differential LNAs is addressed for the first time in the literature. Fabricated in a 130-nm CMOS process, both ESD-protected LNAs consume 10.3 mW under 1.2-V power supply. The first LNA with double-diode ESD protection scheme exhibits the power gain of 17.9 dB and noise figure of 2.43 dB at 5 GHz. Its human-body-model (HBM) and machine-model (MM) ESD levels are 2.5 kV and 200 V, respectively. With the same total parasitic capacitance from ESD protection devices, the second LNA with the proposed double silicon-controlled rectifier (SCR) ESD protection scheme has 6.5-kV HBM and 500-V MM ESD robustness, 17.9-dB power gain, and 2.54-dB noise figure at 5 GHz. The ESD test results have shown that the pin-to-pin ESD test is the most critical ESD-test pin combination for the conventional double-diode ESD protection scheme. With the proposed double-SCR ESD protection scheme, the pin-to-pin ESD robustness can be significantly improved without degrading RF performance. Experimental results have shown that the ESD protection circuit for LNA can be co-designed with the input matching network to simultaneously achieve excellent ESD robustness and RF performance.

Optimization of broadband RF performance and ESD robustness by [formula omitted]-model distributed ESD protection scheme

Large electrostatic discharge (ESD) protection devices close to the I/O pins, beneficial for ESD protection, have an adverse effect on the performance of broadband radio-frequency (RF) circuits for impedance mismatch and bandwidth degradation. A new proposed ESD protection structure, π -model distributed ESD ( π -DESD) protection circuit, composed of one pair of ESD devices near the I/O pin, the other pair close to the core circuit, and a coplanar waveguide with under-grounded shield (CPWG) connecting these two pairs, can successfully achieve both excellent ESD robustness and good broadband RF performance. Cooperating with the active power-rail ESD clamp circuit, the experimental chip in a 0.25-μm CMOS process can sustain the human-body-model (HBM) ESD stress of 8 kV.

ESD robust and area-efficient circle-type layout design for CMOS output buffers

This paper presents an area-efficient multiple circular layout cells that provide an excellent electrostatic discharge (ESD) robustness for CMOS output buffers. Experimental results using a 0.35 μm nonsilicided CMOS process from the Institute of Microelectronics (IME) has demonstrated that the ESD robustness of the proposed layout design based on the human body model (HBM) is enhanced when compared to the traditional finger-type layout approach. The pMOS and nMOS output transistors achieve higher driving/sinking current by using the proposed layout design. In the meantime, the layout area requirement is reduced and hence producing a lower drain-to-bulk parasitic capacitance. These attributes of the new circle-type layout design make it judiciously suitable for utilization in high-density and high-speed applications.

ESD robust and area-efficient circle-type layout design for CMOS output buffers

This paper presents an area-efficient multiple circular layout cells that provide an excellent electrostatic discharge (ESD) robustness for CMOS output buffers. Experimental results using a 0.35 μm nonsilicided CMOS process from the Institute of Microelectronics (IME) has demonstrated that the ESD robustness of the proposed layout design based on the human body model (HBM) is enhanced when compared to the traditional finger-type layout approach. The pMOS and nMOS output transistors achieve higher driving/sinking current by using the proposed layout design. In the meantime, the layout area requirement is reduced and hence producing a lower drain-to-bulk parasitic capacitance. These attributes of the new circle-type layout design make it judiciously suitable for utilization in high-density and high-speed applications.