ESD robust and area-efficient circle-type layout design for CMOS output buffers

Abstract

This paper presents an area-efficient multiple circular layout cells that provide an excellent electrostatic discharge (ESD) robustness for CMOS output buffers. Experimental results using a 0.35 μm nonsilicided CMOS process from the Institute of Microelectronics (IME) has demonstrated that the ESD robustness of the proposed layout design based on the human body model (HBM) is enhanced when compared to the traditional finger-type layout approach. The pMOS and nMOS output transistors achieve higher driving/sinking current by using the proposed layout design. In the meantime, the layout area requirement is reduced and hence producing a lower drain-to-bulk parasitic capacitance. These attributes of the new circle-type layout design make it judiciously suitable for utilization in high-density and high-speed applications.