Excellent Data Retention Research Articles

Low-Voltage Organic Nonvolatile Thin-Film Transistor Memory Based on a P(MMA-GMA)–Al–O Complex Layer

An organic nonvolatile thin-film transistor memory is demonstrated by an inset complex layer between the active layer and the gate dielectric layer, which is realized by heat treating a thin Al layer (2.5 nm) on polymer poly(methyl methacrylate co glycidyl methacrylate) in an oven. The memory window and the memory ratio have a prominent dependence on the V <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">GS</sub> sweeping rate, with the largest values of 13.3 V and 2010 which can be obtained at the rate of -0.2 V/S. At a low programming/erasing voltage of ±15 V, the transistors exhibit excellent memory circle characteristics and long data retention property. At last, the possible operation mechanisms of present transistor memories are discussed.

Recent Advances in Ferroelectric-Gate Field-Effect-Transistor Technology

Recent developments of ferroelectric-gate field-effect transistor (FeFETs) and their applications to integrated circuits are described. The FeFETs with Pt/SrBi2Ta2O9/Hf-Al-O/Si gate stacks possessing excellent data retention characteristics can also operate at elevated temperature and have small transistor threshold voltage (Vth) distribution. The Vth can be adjusted by controlling channel impurity density for both n-channel and p-channel FeFETs. These performance characteristics are now suitable for application to integrated circuits with nonvolatile functions. Fundamental properties for applications to ferroelectric-complementary-metal-oxide-semiconductor (FeCMOS) nonvolatile logic-circuits and to ferroelectric-NAND flash memories are demonstrated.

Low Voltage and High Speed SONOS Flash Memory Technology: The Strategies and the Reliabilities

The flash memory has been evolved from floating gate to the nitride-trapping storage type-SONOS, and even progresses toward the nano-crystal memory in the future. Among them, floating gate flash memory has been one of the most successful nonvolatile memories for the largest volume production, in the past two decades. In comparison, SONOS-type trapping storage has reliability issue and has yet not been fully approved for mass production. However, floating gate flash memory requires high control gate voltage for programming which limits the device scaling and reliability. The SONOS type flash needs to overcome the reliability issues, especially the tunnel oxide and data retention. In this paper, we address different strategies for designing SONOS-type flash memories with low voltage operation, for achieving good reliability while keeping high speed performance. Various operating schemes will be demonstrated to meet the low voltage and high speed requirements. Also, the strategies for achieving excellent data retention will be specifically presented.

Recent Progress of Ferroelectric-Gate Field-Effect Transistors and Applications to Nonvolatile Logic and FeNAND Flash Memory

We have investigated ferroelectric-gate field-effect transistors (FeFETs) with Pt/SrBi2Ta2O9/(HfO2)x(Al2O3)1−x (Hf-Al-O) and Pt/SrBi2Ta2O9/HfO2 gate stacks. The fabricated FeFETs have excellent data retention characteristics: The drain current ratio between the on- and off-states of a FeFET was more than 2 × 106 after 12 days, and the decreasing rate of this ratio was so small that the extrapolated drain current ratio after 10 years is larger than 1 × 105. A fabricated self-aligned gate Pt/SrBi2Ta2O9/Hf-Al-O/Si FET revealed a sufficiently large drain current ratio of 2.4 × 105 after 33.5 day, which is 6.5 × 104 after 10 years by extrapolation. The developed FeFETs also revealed stable retention characteristics at an elevated temperature up to 120 °C and had small transistor threshold voltage (Vth) distribution. The Vth can be adjusted by controlling channel impurity densities for both n-channel and p-channel FeFETs. These performances are now suitable to integrated circuit application with nonvolatile functions. Fundamental properties for the applications to ferroelectric-CMOS nonvolatile logic-circuits and to ferroelectric-NAND flash memories are demonstrated.

Flexible Resistive Switching Memory Device Based on Graphene Oxide

A resistive switching memory device based on graphene oxide (GO) is presented. It is found that the resistive switching characteristic has a strong dependence on electrode material and GO thickness. In our experiment, an Al/GO/ITO structure with 30-nm-thick GO shows good switching performance with an on/off resistance ratio of 103, low set/reset voltage, and excellent data retention. The GO memory is also fabricated on a flexible substrate with no degradation in switching property, even when the substrate is bent down to 4-mm radius, indicating that the GO memory is an excellent candidate to be a memory device for future flexible electronics.

Metal-oxide-high-k-oxide-silicon memory structure incorporating a Tb2O3 charge trapping layer

In this paper, we proposed a metal-oxide-high-k-oxide-silicon (MOHOS)-type memory structure fabricating a high-k Tb2O3 charge trapping layer for flash memory applications. The high-k Tb2O3 MOHOS-type memories annealed at 800 °C exhibited large threshold voltage shifting (memory window of ∼1.41 V operated at Vg=8 V at 0.1 s), excellent data retention (charge loss of ∼10% measured time up to 104 s and at 85 °C), and good endurance characteristics (program/erase cycles up to 105) because of the high probability and deep trap level for trapping the charge carrier due to the formation of the crystallized Tb2O3 with a high dielectric constant of 11.8.

Bipolar Resistive Switching Memory Using Cu Metallic Filament in Ge[sub 0.4]Se[sub 0.6] Solid Electrolyte

A bipolar resistive switching memory device with a low power operation (200 μA X 1.3 V) in a W/Ge 0.4 Se 0.6 /Cu/Al structure is investigated. A high quality Ge 0.4 Se 0.6 solid electrolyte is confirmed by X-ray photoelectron spectroscopy. The resistive memory device with a small via size of 0.2 μm has a large threshold voltage of >0.4 V, high resistance ratio (R high /R low ) of > 10 2 , and good uniformity. The switching mechanisms are due to the Cu metallic filament formation and dissolution from the Ge 0.4 Se 0.6 solid electrolyte under positive and negative biases, respectively, which have been confirmed by high resolution transmission electron microscopy image and energy-dispersive X-ray spectroscopy analysis. The strong Cu filament formation can also be investigated by monitoring the erase voltage and erase current. Good endurance of > 10 5 cycles is obtained. Excellent data retention characteristics at 85 °C are observed after 24 h of retention time, owing to the strong Cu metallic filament formation in the Ge 0.4 Se 0.6 solid electrolyte.

Silicon-oxide-high-κ-oxide-silicon memory using a high-κ Y2O3 nanocrystal film for flash memory application

In this article, the authors developed a silicon-oxide-high-κ-oxide-silicon (SOHOS) memory structure using a high-κ Y2O3 nanocrystal film as the charge-trapping layer for flash memory applications. From x-ray photoelectron spectroscopic and atomic-force microscopy analyses, they found that the Y2O3 nanocrystal layer formed after O2 and N2O annealing. When using the channel hot-electron injection for charging and the band-to-band hot hole for discharging, the high-κ Y2O3 SOHOS memory devices prepared under the N2O gas annealing exhibited large threshold-voltage shifting (memory window of ∼3V), superior endurance characteristics (program/erase cycles of up to 105), and excellent data retention (charge loss of ∼7.5% measured time up to 104s and at room temperature). These results indicate the higher probability of charge-carrier trapping in the Y2O3 film.

A Study of Self-Aligned Nitride Erasable OTP Cell by 45-nm CMOS Fully Compatible Process

This brief proposes a new 45-nm erasable one-time programming cell with a self-aligned nitride (SAN) storage node for logic nonvolatile memory (NVM) applications. The CMOS fully logic-compatible cell was successfully demonstrated using 45-nm CMOS technology with a very small cell size of 0.1188 mum2. This cell-adapting source-side-injection programming scheme has a wide on/off window and superior program efficiency. The SAN cell with five terminals for various operational conditions uses an asymmetrical read voltage to verify the position of the stored charge. This cell also exhibits excellent data retention capability even when the thickness of the logic gate oxide is less than 20 A, and the gate length is shorter than 40 nm. This new cell provides a promising solution for logic NVM beyond a 90-nm node.

Low-voltage operation and excellent data retention characteristics of metal-ferroelectric-insulator-Si devices based on organic ferroelectric films

Metal-ferroelectric-insulator-Si (MFIS) diodes using poly(methyl methacrylate) (PMMA)-blended poly(vinylidene fluoride)-trifluoroethylene [P(VDF-TrFE)] as a gate ferroelectric film were fabricated and their electrical characteristics were investigated. A wide memory window of 1.2 V was observed in a Au/3 wt % PMMA-blended P(VDF-TrFE) (46 nm)/HfTaO(6 nm)/Si MFIS diode for the voltage sweep between −3 and +3 V. Excellent data retention characteristics were also observed in these MFIS diodes. After a small programing voltage of 3 V is applied, the high and low capacitances remained very stable for the retention period over 4 h.

Metal-oxide-high-k-oxide-silicon memory structure using an Yb2O3 charge trapping layer

In this letter, we proposed a metal-oxide-high-k-oxide-silicon (MOHOS)-type memory structure using a high-k Yb2O3 charge trapping layer for flash memory applications. When using Fowler-Nordheim for charging and discharging, the high-k Yb2O3 MOHOS-type memories that had been annealed at 800 °C exhibited large threshold voltage shifting (memory window of ∼2.2 V) and excellent data retention (charge loss of ∼6% measured time up to 104 s and at room temperature) because of the higher probability for trapping the charge carrier due to the formation of the Yb-silicate layer and the smooth surface roughness.

Novel Self-Aligned Nitride One Time Programming with 2-bit/Cell Based on Pure 90-nm Complementary Metal–Oxide–Semiconductor Logic Technology

A novel 2-bit/cell one time programming (OTP) cell with a nitride-based storage node was developed for programmable logic applications. The fully-logic-compatible cell was successfully demonstrated using 90-nm complementary metal–oxide–semiconductor (CMOS) technology with a cell size of 0.358 µm2. This cell adopting source-side injection (SSI) programming scheme has a very large on/off window and superior writing efficiency. The self-aligned nitride storage node exhibits excellent data retention even at a logic gate oxide thickness of less than 2 nm. This new cell supports a promising solution for logic non-volatile memory (NVM) beyond the 90-nm node.

Fabrication and characterization of metal-ferroelectric-insulator-Si diodes and transistors with different HfSiON buffer layer thickness

Metal-ferroelectric-insulator-Si (MFIS) structures using HfSiON as buffer layers were fabricated, and the impact of buffer layer thickness on the electrical properties of the MFIS devices was investigated. HfSiON films with thickness ranging from 1 to 4 nm were deposited by electron beam evaporation, which exhibited much reduced leakage current when compared to that of SiO2 with the same equivalent oxide thickness. From the viewpoint of polarization and charge injection, the flatband voltage and memory window width dependent on the sweeping voltages were discussed for the MFIS diodes with 1-, 2-, and 4-nm-thick HfSiON buffer layers. Small leakage current as well as excellent long-term data retention characteristics were found for all of these samples. It was also found that MFIS diodes with 2-nm-thick HfSiON buffer layer have the largest memory window width. Ferroelectric-gate transistors fabricated with a Pt/SBT(300nm)/HfSiON (2 nm)/Si gate structure showed a memory window of 0.8 V and a high drain current on/off ratio of 108 for the gate voltage sweep between +4 and −4 V. All of these excellent electrical properties proved that HfSiON acts as an excellent barrier for suppressing both leakage current and atomic interdiffusion.

High-Performance High-$k$$\hbox{Y}_{2}\hbox{O}_{3}$ SONOS-Type Flash Memory

In this paper, we propose a novel high-k Y <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">2</sub> O <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">3</sub> poly-Si-oxide-nitride-oxide-silicon (SONOS)-type flash memory. The structural and morphological features of Y <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">2</sub> O <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">3</sub> films were studied using atomic force microscopy, transmission electron microscopy, and X-ray photoelectron spectroscopy. These high-k Y <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">2</sub> O <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">3</sub> SONOS-type memories exhibited large threshold voltage shifting (memory window of 1.9-4.33 V), almost negligible read and gate disturb (threshold voltage shift of ~2-mV operation at V <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">G</sub> = 3 V and V <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">D</sub> = 4 V and ~4-mV operation at V <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">G</sub> =8 V, respectively), excellent data retention (charge loss of ~4% measured time up to 10 <sup xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">4</sup> s and at room temperature, expected ~22% charge loss for ten years at 125degC), and superior endurance characteristics (program/erase cycles up to 10 <sup xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">5</sup> ) because of the higher probability for trapping charge carriers. These Y <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">2</sub> O <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">3</sub> films appear to be a very promising charge trapping layer for high-density two-bit nonvolatile flash memory applications.

CHARACTERISTICS OF METAL-FERROELECTRIC-INSULATOR-SILICON DEVICES USING HFSION BUFFER LAYERS

ABSTRACT In this work, metal-ferroelectric-insulator-silicon (MFIS) devices were fabricated using HfSiON as buffer layers and their electrical properties were studied. Ultra-thin HfSiON films were fabricated by electron-beam evaporation at room temperature and post-annealed using different parameters such as temperature, time in O2. By annealing a 2 nm-thick HfSiON film at 800°C for 60s in O2, a negligible hysteresis loop and small equivalent oxide thickness of 2.3 nm were obtained with a corresponding leakage current density of 6.8 × 10− 5 A/cm2 at a voltage shifted from the flat band voltage by 1 V. In the fabrication of MFIS diodes, Sr0.8Bi2.2Ta2O9 (SBT) films with 400 nm thickness were formed by chemical solution deposition. For Pt/SBT (400 nm)/HfSiON(2 nm)/Si diodes, a memory window of 0.8 V in width was observed during double capacitance-voltage sweep between +5 and –5 V. At the same time, excellent data retention properties were observed. The high and low capacitances in the hysteresis loop were well distinguishable even after 24 h had elapsed.

A high-k Y2O3 charge trapping layer for nonvolatile memory application

In this letter, a silicon-oxide-high-k-oxide-silicon memory structure using a high-k Y2O3 film as the charge trapping layer is reported for nonvolatile memory application. From x-ray photoelectron spectroscopic analysis, we found that the Y2O3 layer formed after annealing at 700°C for 30s. When using channel hot electron injection for charging and band-to-band hot hole for discharging, the high-k Y2O3 memories exhibited large threshold voltage shifting (memory window of 2.3V), excellent data retention (charge loss of 8% at room temperature), and good endurance characteristics (program/erase cycles up to 105) because of the higher probability for trapping the charge carrier due to the formation of a well-crystallized Y2O3 structure.

The Interfacial States between Metal/Oxide and the RRAM - Part II

AbstractSwitching resistance of a metal/oxide/metal structure (Pt/PrxCa1-xMnO3/Pt) upon the stimulation of electric pulse has triggered vast research interests and activities for next generation resistive RAM application. Continued from an earlier paper [1] that studied the mechanism of switching resistance, this paper extends to the switching endurance discussion using admittance spectra. Experimental data indicated that there exist interfacial dipoles (or states) at metal/oxide interfaces. Switching resistance comes from the change of interfacial dipoles. However, those interfacial dipoles are all meta-stable indicating the problem of long term switching endurance. We have tested many metal/PCMO contact combinations and characterized those contacts with basic memory criteria: bit separation, data retention, switch endurance, switching speed, and readout limitations. Among them, TiN/PCMO showed large bit separation, excellent data retention, and fast switching speed, but failed long term switching endurance test. Furthermore, the poor switch endurance is discussed using energy-well diagram. Therefore, a material system providing bi-stable states with reasonably large free energy separations is a must for this type of RRAM application. These energy levels can come from either structure or electrochemical potential differences at the metal/oxide interfaces.

Polysilicon–Oxide–Nitride–Oxide–Silicon-Type Flash Memory Using an Y[sub 2]O[sub 3] Film as a Charge Trapping Layer

A polysilicon-oxide-nitride-oxide-silicon-type flash memory using a high-k yttrium oxide (Y 2 O 3 ) film as the trapping storage layer is developed. This high-k Y 2 O 3 charge trapping layer memory exhibited large threshold voltage shifting (memory window of 3 V), excellent data retention (charge loss of 5 and 10% measured time up to 10 4 s and recorded at room temperature and 125°C, respectively), and superior endurance characteristics (program/erase cycles up to 10 5 ) because of the higher probability for trapping the charge carrier. This film appears to be a very promising charge trapping layer for high-density, two-bit nonvolatile flash memory application.

Optimized ONO thickness for multi-level and 2-bit/cell operation for wrapped-select-gate (WSG) SONOS memory

In this paper, highly reliable wrapped-select-gate (WSG) silicon–oxide–nitride–oxide–silicon (SONOS) memory cells with multi-level and 2-bit/cell operation have been successfully demonstrated. The source-side injection mechanism for WSG-SONOS memory with different ONO thickness was thoroughly investigated. The different programming efficiencies of the WSG-SONOS memory under different ONO thicknesses are explained by the lateral electrical field extracted from the simulation results. Furthermore, multi-level storage is easily obtained, and good VTH distribution presented, for the WSG-SONOS memory with optimized ONO thickness. High program/erase speed (10 µs/5 ms) and low programming current (3.5 µA) are used to achieve the multi-level operation with tolerable gate and drain disturbance, negligible second-bit effect, excellent data retention and good endurance performance.

Ferroelectric and switching behavior of poly(vinylidene fluoride-trifluoroethylene) copolymer ultrathin films with polypyrrole interface

Thin polypyrrole-poly(styrene sulfonate) acid film is employed as interface layers between both bottom and top metal electrodes of a ferroelectric polymer, poly(vinylidene fluoride-trifluoroethylene) copolymer capacitor. The sandwiched structure Titanium∕polypyrrole-poly(styrene sulfonate)∕poly(vinylidene fluoride-trifluoroethylene)∕polypyrrole-poly(styrene sulfonate)∕titanium shows prominent ferroelectric properties even as the thickness of P(VDF-TrFE) film is down to 500Å. The coercive voltage as low as 2.6V is obtained with a remanent polarization of 86mC∕m2 and a switching time of 30μs. The cell remains good ferroelectric properties at 60°C, which is the operating temperature for many electronics. Moreover, the sandwiched structure shows excellent data retention, after more than 1×107 of switching cycles, the remanent polarization remains as high as 69mC∕m2. The soft conductive polymer electrodes not only increase the crystallinity but also enhance the crystal dipole orientation comparing with the conventionally used metal electrodes.