eWLB Technology Research Articles

Broadband packaging solution in embedded wafer level ball grid array technology for D-band PMCW radar

Abstract A system-in-package for a wideband digital radar, in D-band, requires broadband, high-gain antennas combined with broadband chip-to-package and package-to-printed circuit board (PCB) interconnects. This paper demonstrates a wideband, low-loss quasi-coaxial signal transition, and a novel electric split ring resonator (eSRR)-based antenna-in-package (AiP) with a modified reflector concept, for improved gain, in embedded wafer level ball grid array (eWLB) technology. A complete chip-to-package-to-PCB interconnect is also demonstrated by combining the quasi-coaxial transition with a chip-to-package interconnect. The quasi-coaxial signal transition has the largest impedance bandwidth among ball grid array-based quasi-coaxial signal transitions. For the modified reflector concept, a horn-shaped cavity is micromachined in the PCB substrate and remetallized with aerosol-jet printing, placing the reflector 0.25λ from the antenna. The antenna gain is improved with up to 5.3 dB. The AiP with the horn-shaped reflector is the single element with the highest gain, in eWLB technology, above 100 GHz.

D‐band waveguide‐to‐microstrip transition implemented in eWLB packaging technology

This Letter presents a non-galvanic D-band (110-170 GHz) interconnect realised in embedded wafer level ball grid array (eWLB) packaging technology. The interconnect consists of a patch-radiator-based waveguide transition implemented using one of the technology's redistribution layers. The patch radiates to a WR-6.5 standard waveguide perpendicular to its plane. An electromagnetic band-gap structure realised by metal patches is used to suppress undesired modes and improve the performance of the transition. The proposed solution is experimentally verified, and measurement results show that the transition exhibits an average insertion loss of 2 dB across the frequency range 122-146 GHz which, to the best of the authors' knowledge, is the lowest reported loss for a D-band packaging solution in eWLB technology and hence addresses one of the main integration challenges facing millimetre-wave systems.

Innovative Integration Solutions for SiP Packages Using Fan-Out Wafer Level eWLB Technology

Abstract Fan-Out Wafer Level Packaging (FOWLP) has been established as one of the most versatile packaging technologies in the recent past and already accounts for a market value of over 1 billion USD due to its unique advantages. The technology combines high performance, increased functionality with a high potential for heterogeneous integration and reduced overall form factor as well as cost effectiveness. The increasing complexities in achieving a higher degree of performance, bandwidth and better power efficiency in various markets are pushing the boundaries of emerging packaging technologies to smaller form factor packaging designs with finer line/width spacing as well as improved thermal/electrical performance and the integration of System-in-Package (SiP) or 3D capabilities. SiP technology has been evolving through utilization of various package technology building blocks to serve the market needs with respect to miniaturization, higher integration, and smaller form factor as cited above, with the added benefits of lower cost and faster time to market as compared to silicon (Si) level integration, which is commonly called system-on-chip or SoC. As such, SiP incorporates flip chip (FC), wire bond (WB), and fan-out wafer-level packaging (FOWLP) as its technology building blocks and serves various end applications ranging from radio frequency (RF), power amplifiers (PA), Micro-Electro-Mechanical-Systems (MEMS) and Sensors, and connectivity, to more advanced application processors (AP), and other logic devices such as graphics processing units (GPUs)/central processing units (CPUs). FOWLP, also referred to as advanced embedded Wafer Level Ball Grid Array (eWLB) technology, provides a versatile platform for the semiconductor industry's technology evolution from single or multi-die 2D package designs to 2.5D interposers and 3D SiP configurations. This paper presents developments in SiP applications with eWLB/Fan-out WLP technology, integration of various functional blocks such as wire bonding, Package-on-Package (PoP), 2.5D, 3D, smaller form factor, embedded passives, multiple redistribution layer routing and z-height reduction. Test vehicles have been designed and fabricated to demonstrate and characterize these low profile and integrated packaging solutions for mobile products including Internet of Things (IoT)/wearable electronics (WE), MEMS and sensors. Finer line/width spacing of 2/2mm with multiple redistribution layers (RDL) are fabricated and implemented on the eWLB platform to enable higher interconnect density and signal routing. Assembly process details, component level reliability, board level reliability and characterization results for eWLB SiP will be discussed.

Integration of MEMS in Fan-Out Wafer-Level Packaging Technology based System-in-Package (WLSiP)

The Internet of Things/ Everything (IoT/E) will require billions of single or multiple MEMS/Sensors integrated in modules together with other functional building blocks like processor, memory, connectivity, built-in security, power management, energy harvesting, and battery charging. The success of IoT/E will also depend on the selection of the right Packaging Technology. The winner will be the one achieving the following key targets: best electrical and thermal system performance, miniaturization by dense system integration, effective MEMS/Sensors fusion into the systems, manufacturability in high volume at low cost. MEMS/Sensors packaging in low cost molded packages on large manufacturing formats has always been a challenge, whether because of the parameter drift of the sensors caused by the packaging itself or, as in many cases, the molded packaging technology is not compatible to the way MEMS/Sensors are working. Wafer-Level Packaging (WLP), namely Fan-Out WLP (FOWLP) technologies such as eWLB, WLFO, RCP, M-Series and InFO are showing good potential to meet those requirements and offer the envisioned system solutions. FOWLP will grow with CAGR between 50–80% until 2020, forecasted by the leading market research companies in this field. System integration solutions (WLSiP and WL3D) will dominate FOWLP volumes in the future compared to current single die FOWLP packages for mobile communication. The base technology is available and has proven maturity in high volume production, but for dense system integration of MEMS/Sensors, additional advanced building blocks need to be developed and qualified to extend the technology platform. The status and most recent developments on NANIUM's WLFO technology, which is based on Infineon's/Intel's eWLB technology, aiming to overcome the current limits for MEMS/Sensors integration, will be presented in this paper. This will cover the processing of Keep-Out Zones (KOZ) for MEMS/Sensors access to environment in molded wafer-level packages, mold stress relief on dies for MEMS/Sensors die decoupling from internal package stress, thin-film shielding using PVD seed layer as functional layer, and heterogeneous dielectrics stacking, in which different dielectric materials fulfill different functions in the package, including the ability to integrate Microfluidic.

Advanced 3D eWLB-SiP (embedded Wafer Level Ball Grid Array – System in Package) Technology

FO-WLP (Fan-Out Wafer Level Packaging) has been established as one of the most versatile packaging technologies in the recent past and is already accounting for a market value of over 1 billion USD due to its unique advantages. The technology combines high performance, increased functionality with a high potential for heterogeneous integration and reduce the total form factor as well as cost-effectiveness. The emerging of advanced of silicon node technology down to 10 nanometer (nm) in support of higher performance, bandwidth and better power efficiency in mobile products pushes the boundaries of emerging packaging technologies to smaller form-factor packaging designs with finer line/spacing as well as improved thermal electrical/performance and integration of SiP or 3D capabilities. Advanced eWLB FO-WLP technology provides a versatile platform for the semiconductor industry's technology evolution from single or multi-die 2D package designs to 2.5D interposers and 3D System-in-Package (SiP) configurations. This paper reports developments that extend multi-die and 3D SiP applications with eWLB technology, including ultra thin devices or/and with an interposer substrate attachment. Test vehicles have been designed and fabricated to demonstrate and characterize integrated packaging solutions for network, mobile products including IoT and wearable electronics. The test vehicles have ranged from ~30mm2 to large sizes up to ~230mm2 and 0.4mm ball pitch. Assembly process details including 3D vertical interconnect, laser ablation, RDL processes and mechanical reliability characterizations are to be discussed with component and board level reliability results. In addition, warpage behavior and the PoP stacking process will also be presented. Innovative structure optimization that provides dual advantages of both height reduction and enhanced package reliability are reported. To enable higher interconnection density and signal routing, packages with multiple redistribution layers (RDL) and fine line/width spacing are fabricated and implemented on the eWLB platform. Successful reliability and electrical characterization results on multi-die and 3D eWLB-SiP configurations are reported as an enabling technology for highly integrated, miniaturized, low profile and cost effective solutions.

Application of SU-8 photoresist as a multi-functional structural dielectric layer in FOWLP

Microelectromechanical Systems (MEMS) are a fast growing technology for sensor and actuator miniaturization finding more and more commercial opportunities by having an important role in the field of Internet of Things (IoT). On the same note, Fan-out Wafer Level Packaging (FOWLP), namely WLFO technology of NANIUM, which is based on Infineon/ Intel eWLB technology, is also finding further applications, not only due to its high performance, low cost, high flexibility, but also due to its versatility to allow the integration of different types of components in the same small form-factor package. Despite its great potential it is still off limits to the more sensitive components as micro-mechanical devices and some type of sensors, which are vulnerable to temperature and pressure. In the interest of increasing FOWLP versatility and enabling the integration of MEMS, new methods of assembling and processing are continuously searched for. Dielectrics currently used for redistribution layer construction need to be cured at temperatures above 200°C, making it one of the major boundary for low temperature processing. In addition, in order to accomplish a wide range of dielectric thicknesses in the same package it is often necessary to stack very different types of dielectrics with impact on bill of materials complexity and cost. In this work, done in cooperation with the International Iberian Nanotechnology Laboratory (INL), we describe the implementation of commercially available SU-8 photoresist as a structural material in FOWLP, allowing lower processing temperature and reduced internal package stress, thus enabling the integration of components such as MEMS/MOEMS, magneto-resistive devices and micro-batteries. While SU-8 photoresist was first designed for the microelectronics industry, it is currently highly used in the fabrication of microfluidics as well as microelectromechanical systems (MEMS) and BIO-MEMS due to its high biocompatibility and wide range of available thicknesses in the same product family. Its good thermal and chemical resistance and also mechanical and rheological properties, make it suitable to be used as a structural material, and moreover it cures at 150°C, which is key for the applications targeted. Unprecedentedly, SU-8 photoresist is tested in this work as a structural dielectric for the redistribution layers on 300mm fan-out wafers. Main concerns during the evaluation of the new WLFO dielectric focused on processability quality; adhesion to multi-material substrate and metals (copper, aluminium, gold, ¦); between layers of very different thicknesses; and overall reliability. During preliminary runs, processability on 300 mm fan-out wafers was evaluated by testing different coating and soft bake conditions, exposure settings, post-exposure parameters, up to developing setup. The outputs are not only on process conditions and results but also on WLFO design rules. For the first time, a set of conditions has been defined that allows processing SU-8 on WLFO, with thickness values ranging from 1 um to 150 um. The introduction of SU-8 in WLFO is a breakthrough in this fast-growing advanced packaging technology platform as it opens vast opportunities for sensor integration in WLP technology.

Ultra Fine Pitch RDL Development in Multi-layer eWLB (embedded Wafer Level BGA) Packages

The market for portable and mobile data access devices connected to a virtual cloud access point is exploding and driving increased functional convergence as well as increased packaging complexity and sophistication. This is creating unprecedented demand for higher input/output (I/O) density, higher bandwidths and low power consumption in smaller package sizes. There are exciting interconnect technologies in wafer level packaging such as eWLB (embedded Wafer Level Ball Grid Array), 2.5D interposers, thin PoP (Package-on-Package) and TSV (Through Silicon Via) interposer solutions to meet these needs. eWLB technologies with the ability to extend the package size beyond the area of the chip are leading the way to the next level of high density, thin packaging capability. eWLB provides a robust packaging platform supporting very dense interconnection and routing of multiple die in very reliable, low profile, low warpage 2.5D and 3D solutions. The use of these embedded eWLB packages in a side-by-side configuration to replace a stacked package configuration is critical to enable a more cost effective mobile market capability. Combining the analog or memory device with digital logic device in a semiconductor package can provide an optimum solution for achieving the best performance in thin, multiple-die integration aimed at very high performance. One of the greatest challenges facing wafer level packaging at present is the availability of routing and interconnecting high I/O fine pitch area array. RDL (redistribution layer) allows signal and supply I/O's to be redistributed to a footprint larger than the chip footprint in eWLB . Required line widths and spacing of 2/2 μm for eWLB applications support the bump pitch of less than 40um. Finer line width and spacing are critical for further design flexibility as well as electrical performance improvement. This paper highlights the rapidly moving trend towards eWLB packaging technologies with ultra fine 2/2um line width and line spacing and multi-layer RDL. A package design study, process development and optimization, and mechanical characterization will be discussed as well as test vehicle preparation. JEDEC component level reliability test results will also be presented.

Ultra Fine Pitch RDL Development in Multi-layer eWLB (embedded Wafer Level BGA) Packages

The market for portable and mobile data access devices connected to a virtual cloud access point is exploding and driving increased functional convergence as well as increased packaging complexity and sophistication. This is creating unprecedented demand for higher input/output (I/O) density, higher bandwidths and low power consumption in smaller package sizes. There are exciting interconnect technologies in wafer level packaging such as eWLB (embedded Wafer Level Ball Grid Array), 2.5D interposers, thin PoP (Package-on-Package) and TSV (Through Silicon Via) interposer solutions to meet these needs. eWLB technologies with the ability to extend the package size beyond the area of the chip are leading the way to the next level of high density, thin packaging capability. eWLB provides a robust packaging platform supporting very dense interconnection and routing of multiple die in very reliable, low profile, low warpage 2.5D and 3D solutions. The use of these embedded eWLB packages in a side-by-side configuration to replace a stacked package configuration is critical to enable a more cost effective mobile market capability. Combining the analog or memory device with digital logic device in a semiconductor package can provide an optimum solution for achieving the best performance in thin, multiple-die integration aimed at very high performance. This paper highlights the rapidly moving trend towards eWLB packaging technologies with ultra fine 2/2μm line width and line spacing and multi-layer RDL. A package design study, process development and optimization, and mechanical characterization will be discussed as well as test vehicle preparation. JEDEC component level reliability test results will also be presented.

SiPs in the medical domain and in the defense and industrial domain produced with WDoDTM technology

Based on Wire free Die on Die disruptive technology (WDoDTM), complex SiPs can be manufactured in a small factor package size. Stacking known good rebuilt wafers allows high yields while integrating high performance devices (1). Wafer processing is done with e-WLB technology and a specific redistribution layer (RDL) is designed to match with 3D PLUS bus metal edge interconnect technology. 300 mm rebuilt wafers are processed and thinned down to 200 μm before stacking and polymer bonding. Bonding alignment is within ±5 μm allowing small lateral pitches demonstrating WDoDTM versatility with denser IO products such as FPGA. Besides, this new process integration scheme allows the stacking of both conventional boards with SMDs not available at wafer level together with rebuilt wafers made of known good dies. WDoDTM technology has been successfully used with different kind of products in the defense and medical markets. A calculator node including a 484 I/O FPGA with 2 mDDR and an EEPROM in addition to more than 150 decoupling capacitors was manufactured and is exhibiting better electrical performance when compared to the 2 dimensions version. Moreover, a medical implant has been successfully developed embedding 2 ASICS and several PICS capacitors allowing an 8 times shrink of the electronics compared to advance lead based pacemakers.. With this new technology, 3D PLUS is highlighting the way to highly integrated System in Package (SiP) and demonstrates its know-how in the three dimensional integration.

Low-cost eWLB packaging for automotive radar MMICs in the 76–81 GHz range

Embedded wafer-level ball grid array (eWLB) is investigated as a low-cost plastic package for automotive radar applications in the 76–81 GHz range. Low transmission losses from chip to package and board are achieved by appropriate circuit and package design. Special measures are taken to effectively remove the heat from the package and to optimize the package process to achieve automotive quality targets. A 77 GHz radar chip set in eWLB package is developed, which can be applied on the system board using standard solder reflow assembly. These radar MMICs provide excellent radio frequency (RF) performance for the next generation automotive radar sensors. The potential for even higher system integration is shown by a radar transceiver with antennas integrated in the eWLB package. These results demonstrate that eWLB technology is an attractive candidate to realize low-cost radar systems and to enable radar safety affordable for everyone in the near future.

Next Generation eWLB (Embedded Wafer Level BGA): Advanced 3D SiP Packaging Solution

Current and future demands of mobile/portable electronic systems in terms of performance, power consumption, reliable system at a reasonable price are met by developing advanced/appropriate silicon process technology, innovative packaging solutions with use of chip-package-system co-design, low cost materials, advanced assembly and reliable interconnect technologies. In this article packaging evolution for hand held application is discussed with special focus on next generation chip embedding technology called eWLB in detail. To meet the above said challenges eWLB was developed which offers additional space for routing higher I/O chips on top of Silicon chip area which is not possible in conventional WLP or WLB. It also offers comparatively better electrical, thermal and reliability performance at reduced cost with possibility to address more Moore [decreasing technology nodes with low-k dielectrics in SoC] and more than Moore [heterogeneous integration of chips with different wafer technology as SiP solution in multi die or 3D eWLB approaches]. Currently 1st generation eWLB technology is available in the industry with 200mm and 300mm carrier size. This paper will highlight some of the recent advancements in progress development and mechnical characterization in component level and board level reliaiblity of next generation eWLB technologies of double-side 3D eWLB. Standard JEDEC tests were carried out to investigate component level reliability and both destructive/non-destructive analysis was performed to investigate potential structural defects. Daisychain Test vehicles were prepared and also tested for drop and TcoB (Temperature on Board) reliaiblity in industry standard test conditions. There was significant improvement of characteristic lifetime with thined eWLB in TcoB performance because of its enhanced flexibility of package. And there was study of board level reliabiilty with underfill in SMT for large size eWLB packages. This paper will also present study of package warpage behavior with temperature profile as well as failure analysis with microsturctural observation for comprehensive understanding of mechanical behavior of next generation eWLBs.

High resolution analyzes of resistance behavior in eWLB metal contacts

The embedded Wafer Level Ball Grid Array (eWLB) technology is a new packaging solution that allows a minimum package size for any number of interconnects at a given pitch and the possibility of further system integration in x-, y- and z-direction. The eWLB is a fan-out wafer level package solution realized by a thin film redistribution layer above the semiconductor chip and using standard thin-film processes. The eWLB technology is driven by smaller form factor and better electrical performance with respect to high frequency applications. For optimum electrical performance, it is important to measure and control the contact resistance at interfaces caused by intermediate layers of the electrical re-routing. This paper presents a case study for high resolution analyzes at the eWLB metallization system Al/TiW/Cu with different intermetallic resistance behavior. First, we investigate different eWLB metallization systems after different process step variations. We observe chemically high resistance intermediate layers using Time-of-Flight Mass Spectrometry (ToF-SIMS). These results show that the intermediate layer consists of carbon, oxygen, fluorine, chlorine and sulfur. Second, we applied Focused Ion Beam (FIB) preparation and Transmission Electron Microscopy (TEM) as well as High Resolution Transmission Electron Microscopy (HRTEM) experiments to investigate the metallization interface Al/TiW/Cu. We resolve a porous 2–10 nm thin layer. We show that control of different humidity concentration out of the mold compound and different pre-clean etch rates at warped wafer parts are crucial for optimum contact resistance. The results demonstrate that high resolution analyzes and combinations of different analytical methods (e.g. HRTEM and ToF-SIMS) are very important for optimum process developments in modern package technology.