Event Building Research Articles

The Belle II Pixel Detector Data Acquisition and Reduction System

The upcoming Belle II experiment is designed to work at a luminosity of 8×10 <sup xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">35</sup> cm <sup xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">-2</sup> s <sup xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">-1</sup> , 40 times higher than its predecessor. The pixel detector of Belle II with its ~ 8 million channels will deliver ten times more data than all other sub-detectors together. A data rate of 22 Gbytes/s is expected for a trigger rate of 30 kHz and an estimated pixel detector occupancy of 3%, which is by far exceeding the specifications of the Belle II event builder system. Therefore a realtime data reduction of a factor > 30 is needed. A hardware platform capable of processing this amount of data is the ATCA based Compute Node (CN). Each CN consists of an xTCA carrier board and four AMC/xTCA daughter boards. The carrier board supplies the high bandwidth connectivity to the other CNs via Rocket-IO links. In the current prototype design, each AMC board is equipped with a Xilinx Virtex-5 FX70T FPGA, 4 GB of memory, Gbit Ethernet and two bi-directional optical links allowing for a bandwidth of up to 12.5 Gbits/s. IPMI control of mother and daughter board is foreseen. One ATCA shelf containing 10 mother boards/40 daughter boards is sufficient to process the data from the 40 front end boards. The data reduction on the CN is done in two steps. First, the event data delivered by the front end electronics via optical links is stored in memory until the high level trigger (HLT) decision has been made. The HLT rejects >2/3 of these events. In a second step, pixel data of positively triggered events is reduced with the help of regions of interest (ROI), calculated by the HLT from projecting trajectories back to the pixel detector plane. The design allows additional ROI inputs computed from hit cluster properties or tracklets from the surrounding silicon strip detector. The final data reduction is achieved by sending only data within these ROIs to the main event builder.

New Backend Processor Card for the Pipelined Readout System at Belle II

The Belle II experiment at the Super KEKB storage ring at KEK will search New Physics beyond the Standard Model, with 40 times higher luminosity than at KEKB. Much higher event rates are accounted for by moving all front-end digitizers inside or near the detector, and the resulting data received by a common pipeline readout platform developed in KEK. There are about 200 such platforms in the Belle II experiment. We have developed a new Intel Atom based processor card to handle the data and send it to the event building system in three steps. We fully utilize the PCI bus bandwidth and meet the high data rate requirement. In this report, we describe this processor card and the results from testing it in a realistic setup.

Table of Contents

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New data acquisition system for the COMPASS experiment

The modern market offers low cost high performance FPGAintegrated circuits equipped with dozens of multi gigabit seriallinks making them ideal devices for data transmission and datasorting applications. Therefore we have designed the new DAQ systemthat would perform the detector readout and event building in acustom made FPGA based hardware. The software part will provide thecontrol and monitoring function. Currently, the prototypes of thenew FPGA card are being tested and the control and monitoringsoftware is being prepared for the tests with the real hardware.

Modeling event building architecture for the triggerless data acquisition system for PANDA experiment at the HESR facility at FAIR/GSI

A novel architecture is being proposed for the data acquisition and trigger system of the PANDA experiment at the HESR facility at FAIR/GSI. The experiment will run without hardware trigger signal using timestamps to correlate detector data from a given time window. The broad physics program in combination with the high rate of 2 * 107 interactions per second requires very selective filtering algorithms accessing information from many detectors. Therefore the effective filtering will happen later than in today's systems ie. after the event building. To assess that, the complete architecture will be built of two stages: the data concentrator stage providing event building and the rate reduction stage. For the former stage, which requires a throughput of 100 GB/s to perform event building, we propose two layers of ATCA crates filled with Compute Nodes - modules designed at IHEP and University of Giessen for trigger and data acquisition systems. Currently each board is equipped with 5 Virtex4 FX60 FPGAs and high bandwidth connectivity is provided by 8 front panel RocketIO ports and 12 backplane ports for the inter-module communication.We designed simplified models of the components of the architecture and using the SystemC library as support for the discrete event simulations, demonstrate the expected throughput of the full-size system. We also show impact of some architectural choices and key parameters on the architecture's performance.

Evolution of the Trigger and Data Acquisition System for the ATLAS experiment

The ATLAS experiment at the Large Hadron Collider at CERN relies on a complex and highly distributed Trigger and Data Acquisition (TDAQ) system to gather and select particle collision data at unprecedented energy and rates. The TDAQ is composed of three levels which reduces the event rate from the design bunch-crossing rate of 40 MHz to an average event recording rate of about 200 Hz. The first part of this paper gives an overview of the operational performance of the DAQ system during 2011 and the first months of data taking in 2012. It describes how the flexibility inherent in the design of the system has be exploited to meet the changing needs of ATLAS data taking and in some cases push performance beyond the original design performance specification. The experience accumulated in the TDAQ system operation during these years stimulated also interest to explore possible evolutions, despite the success of the current design. One attractive direction is to merge three systems - the second trigger level (L2), the Event Builder (EB), and the Event Filter (EF) - within a single homogeneous one in which each processing node executes all the steps required by the trigger and data acquisition process. Appealing aspects of this design are: a simplification of the software architecture and of its configuration, a better exploitation of the computing resources, the caching of fragments already collected for L2 processing, the automated load balancing between L2 and EF selection steps, the sharing of code and services on HLT nodes. Furthermore, the full treatment of the HLT selection on a single node allows more flexible approaches, for example “incremental event building” in which trigger algorithms progressively enlarge the size of the analyzed region of interest, before requiring the building of the complete event. To spot possible limitations of the new approach and to demonstrate the benefits out-lined above, a prototype has been implemented. The preliminary measurements are positive and further tests are scheduled for the next months.

Upgrade of the CMS Event Builder

The Data Acquisition system of the Compact Muon Solenoid experiment at CERN assembles events at a rate of 100 kHz, transporting event data at an aggregate throughput of 100 GB/s. By the time the LHC restarts after the 2013/14 shut-down, the current computing and networking infrastructure will have reached the end of their lifetime. This paper presents design studies for an upgrade of the CMS event builder based on advanced networking technologies such as 10/40 Gb/s Ethernet and Infiniband. The results of performance measurements with small-scale test setups are shown.

NOvA Event Building, Buffering and Data-Driven Triggering From Within the DAQ System

The NOvA experiment is a long baseline neutrino experiment design to make precision probes of the structure of neutrino mixing. The experiment features a unique deadtimeless data acquisition system that is capable acquiring and building an event data stream from the continuous readout of the more than 360,000 far detector channels. In order to achieve its physics goals the experiment must be able to buffer, correlate and extract the data in this stream with the beam-spills that occur that Fermilab. In addition the NOvA experiment seeks to enhance its data collection efficiencies for rare class of event topologies that are valuable for calibration through the use of data driven triggering.The NOvA-DDT is a prototype Data-Driven Triggering system. NOvA-DDT has been developed using the Fermilab artdaq generic DAQ/Event-building toolkit. This toolkit provides the advantages of sharing online software infrastructure with other Intensity Frontier experiments, and of being able to use any offline analysis module-unchanged-as a component of the online triggering decisions. We have measured the performance and overhead of NOvA-DDT framework using a Hough transform based trigger decision module developed for the NOvA detector to identify cosmic rays. The results of these tests which were run on the NOvA prototype near detector, yielded a mean processing time of 98 ms per event, while consuming only 1/16th of the available processing capacity. These results provide a proof of concept that a NOvA-DDT based processing system is a viable strategy for data acquisition and triggering for the NOvA far detector.

The ALICE electromagnetic calorimeter high level triggers

The ALICE (A Large Ion Collider Experiment) detector yields a huge sample of data from different sub-detectors. On-line data processing is applied to select and reduce the volume of the stored data. ALICE applies a multi-level hardware trigger scheme where fast detectors are used to feed a three-level (L0, L1, and L2) deep chain. The High-Level Trigger (HLT) is a fourth filtering stage sitting logically between the L2 trigger and the data acquisition event building. The EMCal detector comprises a large area electromagnetic calorimeter that extends the momentum measurement of photons and neutral mesons up to pT = 250 GeV/c, which improves the ALICE capability to perform jet reconstruction with measurement of the neutral energy component of jets. An online reconstruction and trigger chain has been developed within the HLT framework to sharpen the EMCal hardware triggers, by combining the central barrel tracking information with the shower reconstruction (clusters) in the calorimeter. In the present report the status and the functionality of the software components developed for the EMCal HLT online reconstruction and trigger chain will be discussed, as well as preliminary results from their commissioning performed during the 2011 LHC running period.

Software design of the ATLAS Muon Cathode Strip Chamber ROD

The ATLAS Cathode Strip Chamber system consists of two end-caps with 16 chambers each. The CSC Readout Drivers (RODs) are purpose-built boards encapsulating 13 DSPs and around 40 FPGAs. The principal responsibility of each ROD is for the extraction of data from two chambers at a maximum trigger rate of 75 KHz. In addition, each ROD is in charge of the setup, control and monitoring of the on-detector electronics. This paper introduces the design of the CSC ROD software. The main features of this design include an event flow schema that decentralizes the different dataflow streams, which can thus operate asynchronously at its own natural rate; an event building mechanism that associates data transferred by the asynchronous streams belonging to the same event; and a sparcification algorithm that discards uninteresting events and thus reduces the data occupancy volume. The time constraints imposed by the trigger rate have made paramount the use of optimization techniques such as the curiously recurrent template pattern and the programming of critical code in assembly language. The behaviour of the CSC RODs has been characterized in order to validate its performance.

Development of a ReadOutDriver (ROD) for ATLAS micromegas

Microstructured gaseous detectors are a possible replacement technology for the inner part of the forward muon spectrometer of the ATLAS detector, when the luminosity of the LHC will increase beyond the design value. During the shutdown 2011/2012, several small micromegas detectors have been installed in ATLAS between the inner tracker and the calorimeter as well as on the small wheel section. To read out these detectors along with the other ATLAS systems, a readout driver has to be developed, that integrates this subsystem into the ATLAS data acquisition infrastructure, including the trigger handling, slow control, event building and data formatting.

The data acquisition system of the SuperB-SVT beam test

Prototypes of a new hybrid pixel detector and a high resistivity detector with short strips, developed by the VIPIX Collaboration and aimed at equipping the layer-0 of the SuperB vertex detector, have been tested in September 2011 with a 120GeV pion beam at the SPS H6 beam line at CERN. They are placed at the center of a reference telescope consisting of six planes of silicon detector with a double-sided strip readout. Both the telescope and the detectors under test (DUT) are equipped with a custom-design, data-push digital readout. The main elements of the trigger and data acquisition system are two VME boards (EDRO) organized in a master-slave configuration and responsible for programming the front-end chips of both the telescope and the DUT. The master board distributes a global synchronization clock and the triggers to all devices, including two 3×3 analog-maps matrices placed behind the DUT and supplied with an independent readout. Both EDROs act as event-fragment builders. These are sent out to a remote PC for event building, buffering and storage.

Central FPGA-based destination and load control in the LHCb MHz event readout

The readout strategy of the LHCb experiment is based on complete event readout at 1MHz. A set of 320 sub-detector readout boards transmit event fragments at total rate of 24.6MHz at a bandwidth usage of up to 70GB/s over a commercial switching network based on Gigabit Ethernet to a distributed event building and high-level trigger processing farm with 1470 individual multi-core computer nodes. In the original specifications, the readout was based on a pure push protocol. This paper describes the proposal, implementation, and experience of a non-conventional mixture of a push and a pull protocol, akin to credit-based flow control. An FPGA-based central master module, partly operating at the LHC bunch clock frequency of 40.08MHz and partly at a double clock speed, is in charge of the entire trigger and readout control from the front-end electronics up to the high-level trigger farm. One FPGA is dedicated to controlling the event fragment packing in the readout boards, the assignment of the farm node destination for each event, and controls the farm load based on an asynchronous pull mechanism from each farm node. This dynamic readout scheme relies on generic event requests and the concept of node credit allowing load control and trigger rate regulation as a function of the global farm load. It also allows the vital task of fast central monitoring and automatic recovery in-flight of failing nodes while maintaining dead-time and event loss at a minimum.This paper demonstrates the strength and suitability of implementing this real-time task for a very large distributed system in an FPGA where no random delays are introduced, and where extreme reliability and accurate event accounting are fundamental requirements. It was in use during the entire commissioning phase of LHCb and has been in faultless operation during the first two years of physics luminosity data taking.

ATLAS TDAQ System: Current Status and Performance

Abstract In this paper we will report on the operation and the performance of the ATLAS data-flow system during the 2011 physics run of the Large Hadron Collider at 7 TeV. The data-flow system is responsible for reading out, formatting and conveying the event data, eventually saving the selected events into the mass storage. In 2010 the ATLAS Trigger and Data Acquisition system has been operated with an overall e_ciency of 96%, while meeting evolving and demanding conditions. By the end of the proton run, the instantaneous peak luminosity had increased by 5 orders of magnitudes. Correspondingly, the ATLAS first-level trigger rate grew by a factor 100, reaching 40 kHz, roughly half of the design rate. Concurrently, the event building and data saving rates reached and exceeded the design performance. Moreover, the installation of additional computing power yielded a system whose characteristics are now comparable with the final ones. In this paper we report on achievements and problems encountered during 2010 and 2011. On this basis, we will follow discussing the preparations for the remaining 2011 data-taking period, in particular with respect to the expected increase in luminosity and the predicted reaching of the design first-level trigger rate.

The Performance of the ATLAS Trigger System in the LHC Proton-Proton Collisions

In this paper we will report on the operation and the performance of the ATLAS data-flow system during the 2011 physics run of the Large Hadron Collider at 7 TeV. The data-flow system is responsible for reading out, formatting and conveying the event data, eventually saving the selected events into the mass storage. In 2010 the ATLAS Trigger and Data Acquisition system has been operated with an overall efficiency of 96%, while meeting evolving and demanding conditions. By the end of the proton run, the instantaneous peak luminosity had increased by 5 orders of magnitudes. Correspondingly, the ATLAS first-level trigger rate grew by a factor 100, reaching 40 kHz, roughly half of the design rate. Concurrently, the event building and data saving rates reached and exceeded the design performance. Moreover, the installation of additional computing power yielded a system whose characteristics are now comparable with the final ones. In this paper we report on achievements and problems encountered during 2010 and 2011. On this basis, we will follow discussing the preparations for the remaining 2011 data-taking period, in particular with respect to the expected increase in luminosity and the predicted reaching of the design first-level trigger rate.

The Data Acquisition System for the KOTO Detector

Abstract The Data Acquisition (DAQ) for the KOTO detector is designed around a 14-bit 125 MHz ADC module, which measures the energy and the time of photomultiplier pulses from about 4000 readout channels. The Trigger has a two-tiered design, with a first level decision based on the time-aligned energy sum over the entire calorimeter and a second level decision based on clustering and in-time veto signal rejection. Data accepted by the second level trigger are read out via Gigabit Ethernet and passed to a computer farm for event building and data storage.

An event builder network for LHCb upgrade and the simulations on its performance

The LHCb experiment is considering an upgrade towards a trigger-free Data Acquisition (DAQ) system. All detector information will be readout at full collision rate (40 MHz) and sent to a large processing farm which performs event building and filtering. According to the physics simulation result, the DAQ system requires a large event builder network (also called DAQ network) with an aggregate bandwidth more than 34 Tb/s.In this paper we present a new architecture of the event builder network, which is a multistage network using low-cost 10-Gigabit Ethernet switches. To evaluate the performance of the full scale system, several simulations have been done. This paper describes different DAQ protocols and the simulation developed for the event builder network based on the framework OMNeT++. The buffer occupancy of the switches has been studied.

A First-level Event Selector for the CBM Experiment at FAIR

The CBM experiment at the upcoming FAIR accelerator aims to create highest baryon densities in nucleus-nucleus collisions and to explore the properties of super-dense nuclear matter. Event rates of 10 MHz are needed for high-statistics measurements of rare probes, while event selection requires complex global triggers like secondary vertex search. To meet these demands, the CBM experiment uses self-triggered detector front-ends and a data push readout architecture.The First-level Event Selector (FLES) is the central physics selection system in CBM. It receives all hits and performs online event selection on the 1 TByte/s input data stream. The event selection process requires high-throughput event building and full event reconstruction using fast, vectorized track reconstruction algorithms. The current FLES architecture foresees a scalable high-performance computer. To achieve the high throughput and computation efficiency, all available computing devices will have to be used, in particular FPGAs at the first stages of the system and heterogeneous many-core architectures such as CPUs for efficient track reconstruction. A high-throughput network infrastructure and flow control in the system are other key aspects. In this paper, we present the foreseen architecture of the First-level Event Selector.

Operating the ATLAS data-flow system with the first LHC collisions

In this paper we will report on the operation and the performance of the ATLAS data-flow system during the 2010 physics run of the Large Hadron Collider (LHC) at 7 TeV. The data-flow system is responsible for reading out, formatting and conveying the event data, eventually saving the selected events into the mass storage. By the second quarter of 2010, for the first time, the system will be capable of the full event building capacity and improved data-logging throughput.We will in particular detail the tools put in place to predict and track the system working point, with the aim of optimizing the bandwidth and the computing resource sharing, and anticipate possible limits. Naturally, the LHC duty cycle, the trigger performance, and the detector configuration influence the system working point. Therefore, numerical studies of the data-flow system capabilities have been performed considering different scenarios. This is crucial for the first phase of the LHC operations where variable running conditions are anticipated due to the ongoing trigger commissioning and the detector and physics performance studies. The exploitation of these results requires to know and track the system working point, as defined by a set of many different operational parameters, e.g. rates, throughput, event size. Dedicated tools fulfill this mandate, providing integrated storage and visualization of the data-flow and network operational parameters.

CMS silicon strip tracker calibration workflow and tools

The silicon strip tracker of CMS is by far the biggest detector of its kind ever operated. Its 15 000 detector modules and 9 million readout channels are individually calibrated in order to achieve the optimal data quality for the experiment. Software tools were designed to automate the operations and reduce the need for maintenance as much as possible, taking care to use pre-existing software frameworks, when possible. The calibration software implements a dedicated scheme of event building, on-line distributed analysis, storage management, data analysis and configuration archival. Dedicated user interfaces and web-applications were developed to ease the operations, speed-up the calibration process, monitor its quality, and track the problems. A complete set of monitoring analyses are also performed online during data taking to validate the data acquired. The calibration parameters are measured continuously, and the values are fed back to the calibration database in order to refine the on-line event reconstruction. A review of the software tools and calibration processes is given here and the obtained results are discussed.