Ethernet System Research Articles

The Alohanet - surfing for wireless data [History of Communications

The following article provides a concise, clearly written discussion of the history of the well-known Aloha protocol by Prof. Norman Abramson, the key individual responsible for its invention, development, and initial deployments in a variety of applications involving joint use of a given medium by potentially interfering systems. He discusses the use of this protocol and its various incarnations, continuing to this day, in such disparate applications as wired Ethernet, satellite communications, and mobile wireless systems, among others. What is, in my mind, so amazing about this scheme is its basic simplicity, yet profound ability to find application in such a widespread range of communication systems. The protocol, in its most concise form, says transmit at will. If interference is detected, retransmit some random time later. What can be simpler? Yet, despite its apparent simplicity, such a protocol was not at all obvious at the time of its invention and initial deployment. Enjoy reading this article!

25 Gbit/s 1.3 µm InGaAlAs-based electroabsorption modulator integrated with DFB laser for metro-area (40 km) 100 Gbit/s Ethernet system

A high-performance 1.3 µm InGaAlAs electroabsorption modulator integrated with a DFB laser for the metro-area 100 Gbit/s Ethernet system (100GBASE-LR4 and -ER4) has been developed. 40 km transmission under 25 Gbit/s operation on singlemode fibre that is required for 100GBASE-ER4 application at 40°C is demonstrated for the first time.

A Proposal for a Generic Real-Time Ethernet System

After the introduction of fieldbus technology, real-time Ethernet (RTE) systems now form the second generation of industrial communication systems (2G ICS). A lot of different approaches for RTEs appeared during the last years, most of them optimized for specific use cases or application domains. From a user's perspective, the transition from a proved fieldbus system to a RTE only makes sense, if multiple system properties are improved significantly in comparison to the state-of-the-art. In order to address such main requirements of machine builders, we introduced three building blocks as key components for a generic RTE system, these includes topology-based addressing, optimized datagram transfer, and synchronous scheduling.

Compensation of Chromatic Dispersion by Modal Dispersion in MMF- and VCSEL-Based Gigabit Ethernet Transmissions

Multimode vertical-cavity surface-emitting lasers (VCSELs) with large spectral widths are widely used with multimode fibers (MMFs) in Gigabit Ethernet (GbE) systems. MMFs exhibit large chromatic dispersion values that can strongly impact the performance of these systems for high bit rates and/or long distances. Here, we show that in 10-GbE systems using VCSELs and MMFs, the chromatic dispersion can be compensated for by the modal dispersion of the MMF.

Low-Complexity Echo and NEXT Cancellers for High-Speed Ethernet Transceivers

Gigabit and multigigabit transceivers require very long adaptive filters for echo and near-end crosstalk (NEXT) cancellation. Implementation of these filters not only occupies large silicon area but also consumes significant power. These problems become even worse when the Tomlinson-Harashima precoding (THP) technique is used in applications such as 10-Gigabit Ethernet over Copper (10 GBASE-T) as the input to the echo and NEXT cancellers is no longer a simple PAM-M signal. To reduce the complexity of these cancellers, in this paper, a novel method based on word-length reduction technique is proposed. The proposed design is derived by replacing the original input to the echo and NEXT cancellers with a finite-level signal, which is the sum of the input to the TH precoder and a finite-level compensation signal. Then, this modified input signal is recoded to have shorter word-length compared with the original input. Hence, the overall complexity can be reduced by using the proposed method. To further reduce the complexity of these cancellers, an improved design is proposed by exploiting the property of the compensation signal. Compared with the traditional design, the proposed echo and NEXT cancellers have exact input and do not suffer from the quantization problem, and thus they are more suitable for VLSI implementation. The proposed method can also be applied to design adaptive echo and NEXT cancellers with little modification. The performance evaluation is performed by simulations to verify the proposed design. It is shown that, by applying the proposed method to a 10 GBASE-T Ethernet system, the hardware complexity of echo and NEXT cancellers can be reduced by about 10.82% without performance loss, compared with the traditional design.

Cost-Effective Joint Echo-NEXT Canceller Designs for 10GBase-T Ethernet Systems Based on a Shortened Impulse Response Filter (SIRF) Scheme

Echo canceller plays an important role in the full-duplex communication system. Conventional implementations of echo cancellers are often the adaptive transversal filter architectures due to the simplicity and robustness of stability and convergence. However, the conventional echo cancellers suffer from high cost problem especially when the response time of the echo is long. In this paper, a new cost-efficient architecture of echo cancellers, targeting on 10GBase-T Ethernet System, is presented. The proposed scheme inherits the concept of channel shortening which is widely employed in DSL systems. A shortened impulse response filter is implemented at the receiver to shorten the impulse response of the echo signal. Hence, the overall cost of echo cancellers can be reduced. We generalize the channel shortening architecture to a joint multi-channel shortening scheme. The joint multi-channel shortening architecture can be applied to multiple-input multiple-output wireline communication systems to further reduce both the cost of echo and near-end crosstalk (NEXT) cancellers. We apply the proposed scheme to 10GBase-T Ethernet system. The simulation results show that the proposed echo and NEXT cancellers can save up to 35% hardware cost compared to the conventional transversal implementations.

Conquering control in a harsh environment [industrial sand mining

Fairmount minerals are one of the largest producers of industrial sand in the United States. Its Illinois-based subsidiary, Wedron Silica, producing high-purity round-grain silica sand. The Wedron facility's biggest producing segment is for the fracturing sand market. When Wedron Silica wanted to upgrade its Ethernet system it opted for a full industrial Ethernet redundancy ring that monitors and controls the entire mining facility.

Parallel computing efficiency analysis of BOR‐FDTD code on a Beowulf cluster

AbstractIn this communication, we investigate the efficiency of a parallel BOR‐FDTD code on a commonly used Beowulf cluster which is connected via an Ethernet or Myrinet networking system. The efficiency of a parallel BOR‐FDTD code is relatively high since it only requires data exchanging between the processors on the subdomain boundary. A satellite reflector antenna is simulated by using the parallel BOR‐FDTD code in order to verify the parallel code we developed. Numerical experiments have demonstrated both software design and networking system play an important role in the efficiency of parallel processing. © 2007 Wiley Periodicals, Inc. Microwave Opt Technol Lett 49: 1398–1401, 2007; Published online in Wiley InterScience (www.interscience.wiley.com). DOI.10.1002/mop.22423

Pipelined Parallel Decision-Feedback Decoders for High-Speed Ethernet Over Copper

One of the powerful yet simple algorithms to decode trellis codes as well as to combat intersymbol interference (ISI) is the parallel decision-feedback decoding algorithm. However, for high-speed applications, such as Gigabit Ethernet over copper (1000BASE-T), the design and implementation of a parallel decision-feedback decoder (PDFD) is challenging due to the long critical path in the decoder structure. Straightforward pipelined designs usually introduce significant hardware overhead. To solve these problems, in this paper, first, based on an optimized scheduling of the computations in the parallel decision-feedback decoding algorithm, a low-complexity pipelined PDFD is proposed. Next, a novel retiming and reformulation technique is presented for the decision-feedback unit (DFU) in the PDFD, which can remove the DFU from the critical path of the PDFD with negligible hardware overhead. Based on these two techniques, two modified low-complexity pipelined PDFDs are derived. Compared with similar designs in the literature, the proposed design can reduce hardware overhead by 60% while achieving similar speed-up for Gigabit Ethernet systems. The savings are even greater for a pulse amplitude modulation (PAM) system with larger constellation

A Burst-Mode Bit-Synchronization IC With Large Tolerance for Pulse-Width Distortion for Gigabit Ethernet PON

A burst-mode bit-synchronization IC applied to the upstream transmission in a gigabit Ethernet passive optical network (PON) was experimentally verified to have a large tolerance for pulse-width distortion within <tex xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">$pm$</tex> 0.66 UI. The extra tolerance of 0.22 UI over the IEEE 802.3ah specification can be assigned to additional distortion generated at an optical receiver incorporated into an optical line terminal. Such a large tolerance was attained by precisely generated eight-phase clocks based on theoretical analyses of distortion tolerance considering real circuit parameters and by an enhanced data selector incorporating a pulse-width detector to monitor the pulse-widths of isolated bits. The IC developed includes a burst into series transformer to permit connection to commercially available PON LSI developed for serial data transmission in Ethernet systems. The theoretical study into the numbers of allowable bit errors and consecutive pattern matches in byte synchronization established following two conditions: 1) allowable error more than one bit in synchronization pattern with 10-bit length was required to hold the synchronization loss rate to less than a few times per year and 2) consecutive pattern matching more than twice was required to hold the synchronization error rate to less than a few times per year.

Co-design for an SoC embedded network controller

With the development of Ethernet systems and the growing capacity of modern silicon technology, embedded communication networks are playing an increasingly important role in embedded and safety critical systems. Hardware/software co-design is a methodology for solving design problems in processor based embedded systems. In this work, we implemented a new 1-cycle pipeline microprocessor and a fast Ethernet transceiver and established a low cost, high performance embedded network controller, and designed a TCP/IP stack to access the Internet. We discussed the hardware/software architecture in the forepart, and then the whole system-on-a-chip on Altera Stratix EP1S25F780C6 device. Using the FPGA environment and SmartBit tester, we tested the system's throughput. Our simulation results showed that the maximum throughput of Ethernet packets is up to 7 Mbps, that of UDP packets is up to 5.8 Mbps, and that of TCP packets is up to 3.4 Mbps, which showed that this embedded system can easily transmit basic voice and video signals through Ethernet, and that using only one chip can realize that many electronic devices access to the Internet directly and get high performance.

25 Gbit/s electrical duobinary transmission over FR-4 backplanes

25 Gbit/s electrical duobinary transmission over an FR-4 backplane is demonstrated for the first time. The BER performance is better than 10/sup -13/. This has been achieved using a two-tap finite impulse response filter for pre-emphasis and a high-speed duobinary-to-binary converter at the receiver. This work provides a potential path for realising 100 Gbit/s Ethernet systems using existing backplane technology.

Integration of Scalable Safety and Security Actions in IEC 61499 Control Applications

In the last decade, manufacturing automation systems have experienced a strong trend towards an increasing complexity, variability and flexibility caused by growing product spectra and declining lot sizes. To cope with the growing requirements of today's automation system, the application of modular mechatronical units have been explored resulting in distributed control systems. An upcoming standard, the IEC 61499 Function Blocks, provides the according programming technologies for the engineer to handle such systems.With the application of distributed control systems and the integration of new communication technologies as for example Industrial Ethernet communication systems the communication within control systems grows up and reaches a new level were system safety and security get a higher impact on the applicability of manufacturing systems. These two aspects are not yet directly covered by the IEC 61499 standard. Within this paper a possible way of integration of necessary activities to ensure system safety and security (so called Safety and Security Actions) in a standard conform way in a distributed control system is described.

Global Open Ethernet (GOE) System and its Performance Evaluation

This paper presents an overview of global open Ethernet (GOE) architecture as a cost-effective Ethernet-based virtual private network (VPN) solution, and discusses a hardware and software implementation of a prototype system. Three main approaches have been proposed for a VPN solution on metro-area network: resilient packet ring, Ethernet over multiprotocol label switching (EoMPLS), virtual bridged local area network-tag stacking (Q-in-Q). None of these schemes can satisfy the following requirements at the same time: network topology flexibility, affordable network functionalities, low equipment cost, and low operational cost. The proposed GOE system is designed to solve VPN management problems of these approaches with MPLS VPN functionality at a low cost of Ethernet-based solution. The key components of GOE are: 1) a novel GOE tag for high-speed switching and 2) a novel routing and protection module via per-destination multiple rapid spanning tree protocol (PD-MRSTP). Via the analytical performance evaluation of EoMPLS, Q-in-Q, and GOE, we show that the memory cost and the network utilization of GOE is two-three times smaller and 22% higher than the other approaches, respectively. We also have developed a GOE prototype system and obtained the following remarkable hardware and software performance results. The GOE core switch delivered 100% of theoretical maximum throughput (10 G) with zero packet loss even with the field programmable gate array platform, and its 10-G port density is 1.5 times denser than the best currently available products. The GOE switch using PD-MRSTP also delivered a significantly fast protection switching time (1.975 ms), which was significantly faster than legacy Ethernet switches. These performance evaluation results prove that the proposed GOE system can be used as a cost-effective high-performance Ethernet-based VPN solution.

Network traffic behaviour in switched Ethernet systems

Measurements on a high-performance Ethernet are shown to match well a truncated Cauchy probability distribution, with a much better fit over smaller file/request sizes than the commonly used Pareto distribution. We observe self-similar characteristics in the traffic at both file servers and at a CPU server elsewhere in the network, which targets, predominantly, file and web servers. This suggests propagation of self-similarity. A simulation model of a single server with Poisson arrivals and Cauchy service demands yields a departure process that follows a power law and matches closely the observed traffic. The simulation is also used to investigate the link between the power laws in the request size distribution and the network traffic by using Lévy distributions for the request sizes. This suggests a link between file/request size distribution and self-similarity in traffic, leading to the possibility of using conventional queueing network performance models with processor sharing queueing discipline. This idea is further supported by an additional simulation experiment and suitable models are proposed.

Time-utility function-driven switched ethernet: packet scheduling algorithm, implementation, and feasibility analysis

We present a MAC-layer, soft real-time packet scheduling algorithm called UPA. UPA considers a message model where message packets have end-to-end timeliness requirements that are specified using Jensen's time-utility functions (TUFs). The algorithm seeks to maximize system-wide, aggregate packet utility. Since this scheduling problem is NP-hard, UPA heuristically computes schedules with a quadratic worst-case cost, faster than the previously best CMA algorithm. Our simulation studies show that UPA performs the same as or significantly better than CMA for a broad set of TUFs. Furthermore, we implement UPA and prototype a TUF-driven switched Ethernet system. The performance measurements of UPA from the implementation reveal its strong effectiveness. Finally, we derive timeliness feasibility conditions of TUF-driven switched Ethernet systems that use the UPA algorithm.

Optimization of baud-rate timing recovery for equalization

This paper suggests the use of a prefilter before baud-rate timing recovery (Mueller and Muller 1976). It is shown that the timing phase of the baud-rate timing synchronizer can be set to a desirable timing phase, at which point a digital equalizer performs best, by proper prefiltering. The procedure for the optimal design of such a prefilter is developed under the assumption that the channel impulse response and desirable timing phase for equalization are known. Application of the proposed scheme to the gigabit Ethernet system demonstrated that prefiltering can improve receiver performance.

The importance of modal bandwidth in Gigabit Ethernet systems

AbstractThis article deals with the evaluation of bandwidth measurements in Gigabit Ethernet Systems using an empirical data model. It concentrates on the use of multimode fibers due to the advent of Vertical Surface Emitting Laser (VCSEL) technology that improves the performance of multimode fiber optics. Copyright © 2001 John Wiley &amp; Sons, Ltd.

Home information wiring system using UTP cable for IEEE1394 and Ethernet systems

IEEE1394 and Ethernet systems are being extensively adopted for data communications equipment, including audiovisual equipment and personal computers. This paper proposes a wiring system that enables the simultaneous transmission of IEEE1394 signals and Ethernet signals along a single UTP-CAT5 cable consisting of four twisted pairs. The requirements of this wiring system were determined by taking into account the specifications of both IEEE1394 and Ethernet systems and the actual domestic environment. Home network adapters were developed to connect IEEE1394 and Ethernet cable to UTP cable. Insertion loss, crosstalk, and eye-diagrams were measured to evaluate the system's performance. The results show that our proposed wiring system is capable of transmitting both the IEEE1394 signal and the Ethernet signal simultaneously at 100 Mbps up to a distance of 100 m along a UTP-CAT5 cable.

The effects of controlling capture on multimedia traffic for shared Ethernet systems

The IEEE 802.3 Ethernet standard is evolving to support much higher data rates and improved quality of service. Even low cost half?duplex CSMA/CD networks can be improved using an enhanced backwards?compatible collision arbitration algorithm known as the Binary Logarithmic Arbitration Method (BLAM) now being proposed as the IEEE 802.3w draft standard. BLAM is designed to co?exist fairly with the existing Binary Exponential Backoff (BEB) algorithm, while eliminating its short?term unfairness problems. In this paper, we focus on how BLAM improves Ethernet performance for multimedia data transport. Analytical, simulation, and prototype hardware experimental results using synthetic, trace, and actual measured traffic are presented. It is shown that BLAM Ethernets can support significantly greater numbers of video streams than existing BEB Ethernets and if the delivery requirements for the video traffic are not too strict, that BLAM Ethernets can even support video if the network is completely saturated with data traffic.