Layer Etching Research Articles

Ring-Opening Polymerization of Surface Ligands Enables Versatile Optical Patterning and Form Factor Flexibility in Quantum Dot Assemblies.

The evolution of display technologies is rapidly transitioning from traditional screens to advanced augmented reality (AR)/virtual reality (VR) and wearable devices, where quantum dots (QDs) serve as crucial pure-color emitters. While solution processing efficiently forms QD solids, challenges emerge in subsequent stages, such as layer deposition, etching, and solvent immersion. These issues become especially pronounced when developing diverse form factors, necessitating innovative patterning methods that are both reversible and sustainable. Herein, a novel approach utilizing lipoic acid (LA) as a ligand is presented, featuring a carboxylic acid group for QD surface attachment and a reversible disulfide ring structure. Upon i-line UV exposure, the LA ligand initiates ring-opening polymerization (ROP), crosslinking the QDs and enhances their solvent resistance. This method enables precise full-color QD patterns with feature sizes as small as 3µm and pixel densities exceeding 3788 ppi. Additionally, it supports the fabrication of stretchable QD composites using LA-derived monomers. The reversible ROP process allows for flexibility, self-healing, and QD recovery, promoting sustainability and expanding QD applications for ultra-fine patterning and on-silicon displays.

Investigation of the atomic layer etching mechanism for Al2O3 using hexafluoroacetylacetone and H2 plasma.

Atomic layer etching (ALE) is required to fabricate the complex 3D structures for future integrated circuit scaling. To enable ALE for a wide range of materials, it is important to discover new processes and subsequently understand the underlying mechanisms. This work focuses on an isotropic plasma ALE process based on hexafluoroacetylacetone (Hhfac) doses followed by H2 plasma exposure. The ALE process enables accurate control of Al2O3 film thickness with an etch rate of 0.16 ± 0.02 nm per cycle, and an ALE synergy of 98%. The ALE mechanism is investigated using Fourier transform infrared spectroscopy (FTIR) and density functional theory (DFT) simulations. Different diketone surface bonding configurations are identified on the Al2O3 surface, suggesting that there is competition between etching and surface inhibition reactions. During the Hhfac dosing, the surface is etched before becoming saturated with monodentate and other hfac species, which forms an etch inhibition layer. H2 plasma is subsequently employed to remove the hfac species, cleaning the surface for the next half-cycle. On planar samples no residue of the Hhfac etchant is observed by FTIR after H2 plasma exposure. DFT analysis indicates that the chelate configuration of the diketone molecule is the most favorable surface species, which is expected to leave the surface as volatile etch product. However, formation of the other configurations is also energetically favorable, which explains the buildup on an etch inhibiting layer. The ALE process is thus hypothesized to work via an etch inhibition and surface cleaning mechanism. It is discussed that such a mechanism enables thickness control on the sub-nm scale, with minimal contamination and low damage.

Kinetics and dynamics of atomic-layer dissolution on low-defect Ag.

Electrochemical metal dissolution reaction is a fundamental process in various critical technologies, including metal anode batteries and nanofabrication. However, experimentally revealing the kinetics and dynamics of active sites of metal dissolution reactions is challenging. Herein, we investigate metal dissolution on near-perfect single-crystal surfaces of Ag within regions of a few hundred nanometers isolated by scanning electrochemical cell microscopy (SECCM). Potential oscillation is observed under constant current conditions for dissolution. The one-to-one correspondence between the dissolution charge and the geometry of the dissolution pit from colocalized imaging allows ambiguous correlation, which suggests that each oscillation cycle corresponds to the dissolution of one atomic layer. The oscillation behavior is further explained in a kinetic model, which reveals that the oscillation comes from the dynamic evolution of the number of different active sites as the dissolution progresses on each atomic layer. In addition to the fundamental interest, the ability to observe layer-by-layer dissolution in electrochemical measurements suggests a potential pathway for developing electrochemical atomic layer etching for fabricating structures and devices with atomic precision.

Mitigating Passivation Layer Damage and Lowering Contact Resistivity of TOPcon Solar Cells Through Low PbO Content Ag Paste.

The development of front-side pastes suitable for devices with high sheet resistance such as tunnel oxide passivated contact (TOPCon), is of great significance but remains a considerable challenge. The optimization of the Ag-Si contact interface is crucial for enhancing contact and improving the efficiency of these devices. This work investigates the front-side Ag pastes with low Al content (<2 wt.%) and different frit compositions for TOPCon. It is found that the paste with low-addition frit effectively prevents excessive etching of passivation layers and minimizes additional damage to boron emitters while ensuring favorable contact. Meanwhile, the lowly FT (fire through) paste promotes Ag nanoparticles with larger particle sizes and higher quantities in the interfacial glass, thereby enhancing the conductivity of the interfacial glass and reducing contact resistivity. A low contact resistivity of ≈1 mΩ·cm2 and superior photovoltaic conversion efficiency of 25.19% are achieved on TOPCon with a sheet resistance of ≈350 Ω/□. This work demonstrates the application potential of Ag-Al paste with low Al content suitable for high sheet resistance emitters by modulating the Ag-Si interface structure. The coupling between microstructure and device performance is elucidated offering an innovative approach for developing silver paste suitable for high sheet resistance TOPCon.

Comparisons of atomic layer etching of silicon in Cl2 and HBr-containing plasmas

This paper reports an experimental investigation of Cl2 versus HBr for plasma atomic layer etching of silicon. An inductively coupled plasma (ICP) source with a constant flow of Ar carrier gases and HBr or Cl2 as a dosing gas was used for etching Si (100). Two modes of dosing were investigated: plasma gas dosing, in which pulsed flows of Cl2 or HBr are partially dissociated with the ICP with no substrate bias, and gas dosing, where the ICP is off during the dosing step. Following either dosing mode, a purge step of up to 5 s is followed by a 1 s period of ICP and substrate bias power, leading to etching of the halogenated surface layer. Optical emission spectroscopy was used to follow relative yields of SiCl, SiCl2, and SiBr, and scanning electron microscopy and profilometry were used to measure etching rates. Plasma gas dosing resulted in etching rates three to four times higher than gas dosing. Small differences were found between the two etchant feed gases, with Cl2 exhibiting about 3%–15% higher etching rate. Etched profiles for HBr plasma gas dosing produced little or no microtrench adjacent to the SiO2-masked line, while HBr gas dosing or Cl2 with either mode of dosing produced microtrenches at the bottom of the Si sidewall.

(Invited) One Dimensional Anodic TiO2 Nanotubes for Energy and Catalytic Applications

Self-organized TiO2 nanotube (TNT) layers, prepared by anodization of Ti have in suitable electrolytes, attracted considerable scientific and technological interest, especially due to their wide range of applications including (photo-) catalysis, hydrogen generation and biomedical uses [1,2].The advantages of anodic TNT layers compared to TiO2 nanotubes prepared by other methods (e.g. hydrothermal) are the tunability of dimensions, their directionality, the ability to absorb significant amount of incident light, and the possibility to utilize nanotube interiors and exteriors for decoration or coating with secondary materials [2].The presentation will review the recent advancements in TNT layer synthesis for their use for the photocatalytic degradation of pollutants in the liquid and in the gas phase. This will include the upscaling of TNT layers from the laboratory scale to several dozens of cm2 [3-6], with a strong focus on the anodization of 3D Ti substrates by bipolar electrochemistry, which cannot be directly connected to the potentiostat (such as Ti meshes) [5-6]. The application of these large scale TiO2 nanotube layers in flow-through photocatalytic reactors will be discussed [3-6]. Additionally, the selective etching of double wall TiO2 nanotube layers towards single wall TiO2 nanotube layers [7] and single nanotube powders [8, 9] will be presented, showing the possibility of preparing magnetically guidable single nanotube photocatalysts by a decoration with Fe3O4.The presentation will also summarize recent advancements in the utilization of TNT layers in energy conversion and energy storage applications [10], in particular Li-ion microbatteries. Experimental details and photocatalytic and battery results will be presented and discussed.

An Assessment of the Lateral Selective Etching, with HCl, of High Versus Low Ge Content SiGe Layers

We have evaluated the feasibility of performing, with gaseous HCl, a lateral selective etching of high versus low Ge content SiGe layers. Such a know-how might be useful to fabricate, besides Complementary Field Effect Transistors, other types of devices relying on stacked nanosheets and multiple selective etchings such as 3D Resistive or Oxyde Random Access Memories (for In-Memory Computing).To that end, we have grown {20 to 25 nm thick Si / ~ 12-15 nm thick Si0.8Ge0.2 or Si0.75Ge0.25 / ~ 11-14 nm thick Si0.5Ge0.5} multilayers on SOI substrates. After a low temperature capping with SiN, such stacks were patterned into regular arrays of square mesas or lines with a stop on the buried oxide, to laterally have access to the layers of interest. The temperature used, in our 300 mm Reduced Pressure - Chemical Vapor Deposition chamber, to grow such stacks was 550°C. Meanwhile, the in-situ HCl etch temperature was always 500°C. The aim of such low process temperatures was to minimize the thermal budget multilayers were submitted to, in order to minimize elastic relaxation and avoid plastic relaxation while still having reasonable growth and etch rates. The overall compressive strain was indeed high in such stacks given the number, individual thicknesses and Ge concentrations of SiGe layers. Multilayers grown at 550°C, 20 Torr with (i) a SiH2Cl2 + GeH4 chemistry for Si0.5Ge0.5, (ii) a Si2H6 +GeH4 chemistry for Si0.75Ge0.25 or Si0.8Ge0.2 and (iii) pure Si2H6 for Si were in some places defective, with the presence on the surface of islands. Such defects were likely due to Si2H6 mass-flows which were too large, resulting in gas phase nucleation and, in some places, the formation of defects that increased in size as growth happened. We thus proceeded differently. Instead of Si2H6 + GeH4, we have used a SiH4 + GeH4 chemistry for the epitaxy of SiGe 20% or 25% layers. We succeeded in having reasonable SiGe 20% and 25% growth rates at 550°C, 20 Torr, which was not a given with that chemistry. We also showed that a x/(1-x) = 2.81*F(GeH4)/F(SiH4) relationship perfectly accounted for the almost linear increase of the Ge concentration x with the F(GeH4)/F(SiH4) mass-flow ratio. We otherwise reduced the Si2H6 mass-flow and added HCl to minimize gas phase nucleation and suppress the formation of amorphous inclusions in the Si layers. The linear dependency of the 550°C, 20 Torr Si growth rate on the Si2H6 and HCl mass-flows was modelled with the following phenomenological relationship: Si Growth Rate (nm min.-1) = 3260*F(Si2H6)/F(H2) – 1070*F(HCl)/F(H2).We then determined, at 500°C, 600 Torr, the (001) blanket HCl etch rates of SiGe 30% and 40%: 1.37 and 5.28 nm min.-1. Based on such data, we should have the following SiGe 50%, 25% and 20% etch rates: 20.0, 0.70 and 0.36 nm min.-1, respectively. Meanwhile, the pure Si etch rate should be negligible: 0.025 nm min.-1 only. Should we then define theoretical selectivities as being ratios between (i) SiGe 50% and (ii) SiGe 25%, SiGe 20% or pure Si blanket (001) etch rates, we would obtain promising selectivities (29, 56 and 800) when laterally etching of SiGe 50% versus SiGe 25% SiGe 20% and Si.We then switched over to patterned wafers. The lateral selective etching of Si0.5Ge0.5 versus Si0.8Ge0.2 (and Si) was feasible. The following features were highlighted: (i) Si0.5Ge0.5 lateral etch rates along the <110> directions were much smaller than in the [001] direction and (ii) because of micro-loading, lateral etch rates were definitely higher for squares than for lines (0.9 - 1.1 nm min.-1 for lines, to be compared with 1.7 – 2.1 nm min.-1 for squares). Meanwhile, the lateral selective etching of Si0.5Ge0.5 versus Si0.75Ge0.25 was far from being perfect, with much higher Si0.5Ge0.5 etch rates and a significant Si0.75Ge0.25 recessing at tunnel entrances (see Figure 1). Si0.75Ge0.25 floors and ceilings were otherwise far more etched and thus tilted than Si0.8Ge0.2 ones. Inserting very thin Si spacers between Si0.5Ge0.5 cores and Si0.75Ge0.25 claddings partly solved those issues, with no recessing and lesser etchings at the entry points of tunnels, then (see Figure 2). Figure 1

Enabling in-Line Silicon Wafer Porosification: An Experimental and Simulation Study

Silicon is the dominant material of microelectronic and solar cell devices but also a very promising material for Li-ion battery anodes. For many of these applications thin silicon layers are needed for which a layer transfer is a very efficient way to produce them. In this paper, results of large-scale etched porous silicon wafers using an in-line pilot production tool will be presented. The tool uses a wet chemical front-side contact that periodically changes polarity and thus just needs one side of the wafer in contact to the electrolyte. However, the proportion of the wafer that is exposed to each polarity is a function of its current location, leading to large current density fluctuations. Therefore, multiple electrodes have been positioned within the half-cells of the setup. Voltage and current data were recorded as a function of time, and the respective position of wafer, for all electrodes. A finite element simulation using COMSOL allowed for a very good reproduction of these in-operando measured data. A clear correlation to lateral and vertical porosity variations within the porous layers has been found.All etching inhomogeneities in the porous layer can be clearly explained by changes in the series resistance and the corresponding voltage losses as the wafer is moving through the setup. These series resistance changes are almost exclusively related to the geometrical shape of the half cells and the positions of the counter electrodes. This means that the passive series resistance network is the reason for non-perfect etching of the porous layers rather than non-linear electrochemical processes. This network also includes the anode and the cathode that are used for contacting the electrochemical half cells. The smart contacting scheme of the in-line etching tool showed up to be fully reliable. The COMSOL studies displayed, that changes of the half-cell geometries can drastically decrease the current fluctuations. Adjustments have shown that a decrease from an initial 40% fluctuation to less than 6% fluctuation are achievable. This allows for the etching of laterally homogeneous porous layers suitable for a layer transfer.

Seiichi Iwamatsu, the Inventor of Atomic Layer Etching: The Conception of Cycled Exposures of Silicon to Halogens and Pulses of Heat, Ions, and More

The history of Atomic Layer Deposition (ALD) has been extensively researched in the VPHA-project (www.vph-ald.com/) initiated in 2013 by R. Puurunen [1]. It is commonly accepted that Atomic Layer Deposition (ALD) was conceived in the Baltic area as a unique ultrathin-film growth method based on the repeated, self-terminating gas-solid half-reactions of at least two volatile compounds on a solid substrate surface. Originally, in the 1960’s, the Russians Alekskovski and Kol'tsov [2]) named this method Molecular Layering and exactly 50 years ago, in 1974 the Finnish inventors Suntola and Antson [3] patented the method as Atomic Layer Epitaxy. This fact has been officially celebrated at the 24th ALD Conference in Helsinki (Aug. 5, ’24 ald2024.avs.org).Atomic Layer Etching (ALE) has lagged behind ALD. For long [4,5] the first patent published on ALE was thought to have been initiated by Max Yoder [6]. In 1987 he conceived the idea on diamond etching with intermittent pulsing of nitrogen dioxide and noble gas ions mixed with hydrogen gas. However, it was Seiichi Iwamatsu (Fig. 1) of Seiko Epson, Japan, who filed in 1981 an application on Si-etching by repeated exposure to iodine (I2) chemistry at moderate temperatures (20 °C to 100 °C) followed by a light or heat pulse up to ~ 300 °C [7]; see Fig. 2. This patent was followed by several others on ALE [8]. One of these patents disclosed quasi-ALE (named “digital etching”) via Si-surface modification by “lamination” of a single Cl-atomic layer from exposure to Cl2 gas, followed by a removal step carried out by Ar+-ion bombardment to etch off “one atomic layer or at most three atomic layers by controlling the kinetic energy” [9].This presentation will highlight the groundbreaking work and background of the Japanese inventor Seiichi Iwamatsu. Born in 1939 in Kyoto to a family of doctors - his father being a practicing physician- he grew up and studied in Osaka, after which he spent many years as a ‘master inventor’ (over 1200 patents filed in his name) for Seiko Epson (~1970-1990) and others afterwards. He played key roles in thin-film technology and e-beam lithography. He also contributed to the success story of Seiko’s quartz watch, a masterpiece in micromachining a miniature tuning fork from crystalline fused silica, tuning/trimming it to 32,768 Hz (=215 Hz), packaging it in a hermetically sealed case and integrating it with flip-flop frequency dividing and counting electronic circuitry and a step motor [10].From the above it is clear that Mr. Iwamatsu can be recognized as the original inventor of Atomic Layer Etching.----------------------------------------------------AcknowledgementThe authors would like to thank Dr. Masanobu Honda (Tokyo Electron Miyagi Ltd., Japan) for his support in retrieving some of the historic facts mentioned herewith about Dr. Iwamatsu.

(Invited) In Situ Measurements during ALD/ALE Processes

Atomic layer deposition (ALD) and atomic layer etching (ALE) provide exquisite control over the addition and removal of thin film materials and are invaluable tools for semiconductor manufacturing and a wide range of other applications. However, it is not always clear why some ALD/ALE processes succeed while others fail. Performing in situ measurements during ALD/ALE can unravel the detailed surface chemistries underlying these processes to elucidate the reaction mechanisms and ultimately yield more robust and reliable processes. In this presentation, I will motivate the need for in situ measurements during ALD/ALE and provide detailed examples of the techniques used under typical ALD conditions including quartz crystal microbalance, mass spectrometry, infrared spectroscopy, spectroscopic ellipsometry, and optical emission spectroscopy for plasma-based processes. I will also describe some of the high vacuum in situ methods that have been exploited such as X-ray photoelectron spectroscopy and scanning probe microscopy. In addition, I will discuss synchrotron X-ray based methods for in situ study of ALD/ALE reactions.

Atomically Dispersed Transition Metal Catalysts for Electrochemical Chlorine Evolution Reaction

Chlorine evolution reaction (CER) is a crucial anodic reaction in the chlor–alkali process. For 50 years, dimensionally stable anode (DSA) has been extensively used for CER. However, the DSA requires about 30 at% of precious metals, such as iridium and ruthenium, and also catalyzes oxygen evolution reaction as a parasitic reaction, invoking the cost and selectivity issues, respectively. In this work, we have synthesized atomically dispersed non-precious metal (M; M = Fe, Co, Ni, and Cu)-based CER catalysts to unravel their CER catalytic trends. The catalysts were synthesized by coating carbon nanotube (CNT) with polyaniline layers, adsorption of a metal precursor, silica layer overcoating, thermal annealing, followed by silica layer etching. The resulting M1/aniCNT catalysts showed over 90% CER selectivity. Among the catalysts, Ni1/aniCNT exhibited the best CER activity, surpassing that of DSA. The high CER activity of Ni1/aniCNT is attributed to the asymmetric Ni–N3 structure with Ni1+ oxidation state. This work highlights the dependency of activity on the structure of atomically dispersed catalysts and broadens the range of CER catalysts.

(Invited) Surface Analysis of GaN by Cyclic Etching Process for ALE of III-V Materials

In the fabrication of next-generation power electronic devices based on the III-V materials i.e. gallium nitride (GaN), AlGaN, etc., atomic layer etching (ALE) with the cyclic process of ion irradiation and Cl adsorption steps has been attracted for the reduction of plasma induced damages and the precise definition of etch depth. For controlling the GaN ALE, we investigated the surface layer of GaN at each Ar ion and Cl radical reaction step using a beam experiments with in situ X-ray photoelectron spectroscopy (XPS).[1,2]Samples were GaN films on a sapphire substrate by Hydride Vapor Phase Epitaxy (HVPE) method. Native oxide on GaN surface was removed by wet cleaning (5% HF) and Ar ion sputtering before the beam experiments. The wet cleaned surface was exposed to Cl radicals generated in Cl2 gas plasma. Then, Ar ions were irradiated with the accelerating voltage of 100 V or 200 V.The one cycle consisted of these Cl radical exposure and Ar ion irradiation. To stabilize the GaN surface, five cyclic processes were carried out. The GaN surface at each step was analyzed by angle-resolved XPS with the take-off-angles (TOA) of 20, 30, 40, 60, and 90 degrees with respect to the wafer surface. The depth profiles were analyzed by the maximum entropy method.In the GaN cycle process by Cl adsorption and Ar ion irradiation, the reaction in the Cl adsorption step is saturated at the order of 1019 cm−2. The reaction in the Ar ion irradiation step was saturated by Ar ion irradiation of the order of 1016 cm−2, and the formation of Ga dangling bonds occurred with the etching of Ga chloride and the desorption of N atoms. Increasing the Ar ion energy increased the amount of Ga dangling bonds formation and the subsequent increase of Cl adsorbed amount by the radical irradiation. At the same time, higher the Ar ion energy, higher the required doses of Cl and Ar ions to saturate the reaction in each step.The Cl adsorption behavior was depended on the depth profile of the Ga dangling bonds and varied with Ar ion energy. At 47.6 eV, which is below the energy of GaN ALE window, the Ga chloride could not be desorbed, but ions in this energy break Ga-N bonds and desorb N atoms. At 86.8 eV, which is the energy band of the ALE window of GaN, Ga chloride and N atoms can be desorbed, and it was confirmed that the Cl adsorption behavior depends on the ion energy. From these results, it is considered that the Cl adsorption depth and etching depth continue to change even in the energy band of the ALE window.Consequently, to achieve a higher Synergy and precise etching of GaN, tuninng of ion energy beside the ALE window should be necessary.AcknowledgementThe author thanks Drs. Masaki Hasegawa, Takayoshi Tsutsumi, Kenji Ishikawa, Masaru Hori, Hiroki Kondo, Shouhei Nakamura, Atsushi Tanide, Souichi Nadahara, Osamu Oda, Jia He for their discussions and providing the data.[1] T. Takeuchi et al., J. Phys. D: Appl. Phys. 46, 102001 (2013).[2] Y. Zhang et al., J. Vac. Sci. Technol. A 35, 060606 (2017).

(Invited) Atomic Layer Etching: Basics, New Developments & Applications

Atomic layer etching (ALE) is becoming an important technology for patterning and shaping of electronic and photonic devices. This tutorial briefly recaps the fundamentals of thermal, directional and plasma assisted atomic layer etching. Performance benefits and limitations for ALE in comparison to the continuous processing analogues such as reactive ion etching, radical and vapor etching are the consequence of the cyclic self-limited structure of ALE processes. Selection criteria for the appropriate etching technology for a given task will be presented. The enormous progress in the development of new ALE process and chemistries will be illustrated using published and potential practical applications in the manufacturing of electronic and photonics devices. They include multi-patterning, advanced planar and 3D logic and memory devices, 2D materials, emerging memories comprised of hard to etch materials, power and optical devices and combinations of ALE and atomic layer deposition.

(Invited) Investigating ALE Approaches for Novel Metal Oxide Patterning at Sub-100 Nm Pitch for High-Density Memory & Compute Applications

Atomic layer etching (ALE) continues to garner wide attention as a technique for controlled patterning of different materials.1,2 However, a substantial amount of these studies are carried out on blanket films. It is therefore pivotal to investigate the feasibility of ALE for patterning high-density features as it exhibits the potential to be the preferred etching method for novel materials in the semiconductor industry.This talk will focus on the impact of ALE in the patterning of complex metal oxides like InGaZnO and MgZnO. These metal oxides are potential contenders as channel materials in high-performing transistors for memory and compute applications.3 Therefore, several critical criteria need to be followed when ALE conditions are being defined. The channel needs to be patterned with minimal physical and chemical damage such that there is little or no impact on the mobility parameters of the channel.The etching process should not induce redeposition onto the hard mask which also acts as a top contact in an integrated stack within the chip. In the case of InGaZnO, ALE-based patterning down to pitch 36 nm will be discussed in a systematic fashion.4 At such scaled pitches, it is observed that the etching challenges highlighted above cannot be resolved completely by ALE itself. Therefore, ALE in conjunction with other patterning approaches such as plasma pulsing needs to be employed to achieve satisfactory etching of the features at pitch 36 nm.On the other hand, when the metal oxide layer comprises a non-volatile element like Mg (in MgZnO), the etching mechanism tends to be both physical and chemical. In this case, it is still seen that the ALE approach provides a more controlled way of removing the layer without damaging the layer composition when compared to its conventional counterpart – reactive ion etching (RIE) at pitch 90 nm.5 REFERRENCES (1) Metzler, D.; Bruce, R. L.; Engelmann, S.; Joseph, E. A.; Oehrlein, G. S.; Fluorocarbon Assisted Atomic Layer Etching of SiO2 Using Cyclic Ar/C4F8 Plasma. J. Vac. Sci. Technol. A 2014, 32, 020603.(2) Metzler, D.; Li, C.; Engelmann, S.; Bruce, R. L.; Joseph, E. A.; Oehrlein, G. S.; Fluorocarbon Assisted Atomic Layer Etching of SiO2 and Si Using Cyclic Ar/C4F8 and Ar/CHF3 plasma. J. Vac. Sci. Technol. A 2016, 34, 01B101.(3) Belmonte, A.; Oh, H.; Rassoul, N.; Donadio, G. L.; Mitard, J.; Dekkers, H.; Delhougne, R.; Subhechha, S.; Chasin, A.; van Setten, M. J.; Kljucar, L.; Mao, M.; Puliyalil, H.; Pak, M.; Teugels, L.; Tsvetanova, D.; Banerjee, K.; Souriau, L.; Tokei, Z.; Goux, L.; Kar, G. S.; Capacitor-Less, Long-Retention (>400s) DRAM Cell Paving the Way towards Low-Power andHigh-Density Monolithic 3D DRAM. 2020 IEEE International Electron Devices Meeting (IEDM) 2020, pp. 28.2.1-28.2.4.(4) Kundu, S.; Decoster, S.; Bezard, P.; Mehta, A. N.; Dekkers, H.; Lazzarino F.; High-Density Patterning of InGaZnO by CH4: a Comparative Study of RIE and Pulsed Plasma ALE. ACS Appl. Mater. Interfaces 2022, 14, 29, 34029–34039.(5) Ghorbani, L.; Kundu, S.; De Gendt, S.; Manuscript in preparation.

Precursor Vapor Pressure Estimation and Precise QCM Measurement for ALD Process Development with Ideal ALD Characteristics

Atomic Layer Deposition (ALD) produces thin films by alternately supplying precursors and reaction gases. In this process, a film with one atomic layer or fewer is formed in a single cycle. By properly controlling the number of cycles, the film thickness can be precisely controlled and reproducible film formation is possible. This technology is widely used in the production of semiconductor integrated circuits (ULSIs). The amount of growth per cycle is called GPC, and it is well known that GPC remains constant over a temperature range known as the ALD Window, within which ideal ALD film-formation characteristics can be obtained. Therefore, a wide ALD window is important for constructing an easy-to-use ALD process. The GPC is constant in the ALD Window because the coverage factor of the chemisorbed precursor is nearly unity. Therefore, it is necessary to consider the conditions under which saturated chemisorption occurs during the adsorption process of the precursor. The surface coverage factor depends on the adsorption constant K and precursor concentration C according to the "Langmuir-Hinshelwood equation," as shown below.θ=KC/(1+KC)If the product of the adsorption equilibrium constant K and the precursor concentration C is large (e.g., 100 or more), the coverage factor θ is almost constant at unity, even at different substrate surface temperatures; that is, even if the values of K differ slightly, or even if the concentration C differs slightly between the center and the edge of the wafer. This is the main reason for the good thickness reproducibility and uniformity of the ALD process.We developed a method to precisely estimate the precursor concentration, that is, the saturated vapor pressure, using quantum chemical calculations (the Modified COSMO-SAC method). This allowed us to identify compounds that could be supplied at appropriate concentrations as ALD precursors. This vapor pressure estimation is also effective for constructing the Atomic Layer Etching (ALE) process.The adsorption equilibrium constant K of the precursor can be determined by quantum chemical calculations; however, this is time-consuming and computationally expensive. For the synthesized precursor compounds, the adsorption equilibrium constant K can be easily determined experimentally using precise Quartz Crystal Microbalance (QCM) measurements. As QCM is very sensitive to the temperature change, we have specially made “AT cut” Quartz Crystal which is insensitive to the temperature fluctuation at the desired temperature. The combination of a custom-made oscillation circuit for the above AT cut crystal and a frequency counter enables measurement of weight change with a sensitivity of 0.3 ng/cm2 or less and measurement of weight change over time due to adsorption or reaction with high time resolution of 20 points/sec. We combined these calculations with experiments to develop ALD systems that exhibit ideal ALD properties.

Threshold Voltage Shift of P-Ch GaN Misfets with Charge Trapping Insulator

The realization of high-performance p-channel devices and threshold voltage control are desired to achieve GaN CMOS circuits. Recess-gate devices on polarized junction substrates have been reported as candidates for p-channel devices that can be integrated with n-channel devices, including HEMTs [1]. In addition, we have reported that the use of a quasi-atomic layer etching process with nitrogen plasma to fabricate the recessed gate structure improves the MIS interface characteristics and increases the drive current [2]. However, regarding threshold voltage control, the recessed gate structure may not be sufficient. Although control by the back gate is a candidate, other control methods are worth considering for circuit simplicity. In this study, we investigated the threshold control by introducing a charge trapping layer into the gate insulator.Figure 1 shows the schematic structure of p-channel GaN MISFETs with a charge-trapping layer fabricated on a polarization junction substrate. The insulator, Al2O3/HfO2/Al2O3 layer, was formed by atomic layer deposition. A negative threshold voltage shift could be expected when positive charges are trapped in the HfO2 layer or at the HfO2/Al2O3 interfaces.Figure 2 shows the I d-V g characteristics of a p-channel MISFET. V d was set to -3 V, and two consecutive double-sweep measurements were performed. Figure 2(a) shows the results of measurements with a V g range of +5 to -6 V. It shows a large hysteresis, with a negative sweep changing to the on state at a positive voltage and a positive sweep to the off state at a negative voltage. The second sweep also reproduces the first sweep's characteristics. This result can be attributed to the fact that the negative gate voltage introduces positive charges into the charge-trapping layer, resulting in a negative threshold voltage, and that the positive gate voltage completely removes the positive charge from the charge-capture layer, resulting in a positive threshold voltage again. On the other hand, Fig. 2(b) shows that, using the V g range of +2 to -6 V, the threshold voltage of the negative sweep in the second sweep shifts to negative. This result indicates that only partial charge was released from the charge trapping layer, and the remaining charge caused the shift. Also, Fig. 2(c) shows the results of the V g range of 0 to -6 V. The hysteresis at the second sweep is significantly reduced, indicating normally-off operation. This is considered to be a result of the positive charge captured in the charge-trapping layer being retained in the negative gate voltage range.Furthermore, Figs. 2(d), (e), and (f) present the vertical axes of Figs. 2(a), (b), and (c)c in logarithmic form, respectively, and in addition, I g is also shown. The gate leakage current is kept low compared to the drain current, and an on-off ratio of more than five orders of magnitude is obtained. Additionally, there is no significant change in the subthreshold slope due to threshold voltage variation, indicating that the charging and discharging of the charge trapping layer does not significantly affect the carrier transport properties in channel region.In this study, the threshold voltage shift and resulting normally-off operation of p-channel GaN MOSFETs is demonstrated by using a charge trapping layer. The same effect is promising for threshold voltage control of n-channel devices, and this technique is expected to be used for power-saving GaN CMOS circuits with two-dimensional carrier gases. Acknowledgments This work was supported by JSPS KAKENHI Grant Number 21K04172.

Modeling and Optimization of Wet ALE Process

Atomic layer etching (ALE) has become an important process for semiconductor device manufacturing due to its unique ability to control surface etching with single molecular level control. ALE first began in the laboratory over thirty years ago, and in the past ten years it has matured into an important part of the semiconductor manufacturing process with several solutions available on the market for high volume manufacturing.Most ALE processes have been developed in a vapor or rarified gas environment, often using a thermal or plasma process to facilitate the required chemical reactions. (1) In recent years there has also been work on digital etching with liquid chemistry, including ALE processes for copper, cobalt, ruthenium, and noble metals (2-5).With wet ALE processes relatively unexplored compared to the longer studied vapor phase processes, there has not been much work done to understand how the interaction of fluid flow and the chemical reaction kinetics can affect a wet ALE process. Digital wet etch processes generally require two different solvents for the ligand deposition/adsorption and subsequent etching steps, and it’s important to minimize any mixing of the two liquids: otherwise the etch process ceases to be digital and instead becomes a continuous etch process, with resulting problems in roughness and local nonuniformity.In this paper we will present results of a series of simulations to model the sequentially switching liquid flow and surface reactions of an ALE process: both in a simplified flow cell system and in center dispense over a spinning wafer.The ALE reactions are modeled assuming Langmuir isotherms: one for the ligand deposition and another for the subsequent etching step. The kinetic equation for a pseudo first order heterogeneous surface adsorption isotherm is as follows: dq/dt = k(qe - q)Where q is the surface adsorption density, t is time, k is the reaction rate constant, and qe is the equilibrium concentration of the adsorbate. qe is determined using the standard Langmuir isotherm: qe = q∞ (K cA /(1 + K cA ))Where q∞ is the maximum possible surface adsorbate concentration, cA is the concentration of adsorbate in the solvent, and K is the Langmuir adsorption equilibrium constant. A similar set of equations are used for the desorption in the etching step, with different values for the rate constant k and equilibrium surface density qe .An example of the spinning wafer liquid dispense simulation is shown in Figure 1. This is an axisymmetric simulation, where liquid is being continually dispensed at 1 L/min onto the center of a wafer spinning at 1000 RPM, with the liquid switching to a different solvent at t = 0. The figure shows the volume fraction in the liquid film at 0.1s as the displacing fluid flows from the center of the wafer at the left to the edge of the wafer at the right. The volume fraction at the bottom boundary, which represents the wafer surface, shows that the transition from one solvent to another is not instantaneous, and that there will be some mixing between the two.Our analysis and results will also include dimensional analysis of the chemical reaction and fluid flow system, showing how parameters like reaction rate constants, spin speed, dispense flow rate, flow velocity, and solvent switching frequency can affect the etching performance in terms of etching uniformity and surface roughness for any generalized wet digital etch system. Kanarik, K. J.; Lill, T.; Hudson, E. A.; Sriraman, S.; Tan, S.; Marks, J.; Vahedi, V.; Gottscho, R. A. Overview of Atomic Layer Etching in the Semiconductor Industry. JVST A 2015, 33 (2), 020802.Netzband, C.; Arkalgud, S.; Abel, P.; Faguet, J. Wet Atomic Layer Etching of Copper Structures for Highly Scaled Copper Hybrid Bonding and Fully Aligned Vias. In 2022 IEEE 72nd Electronic Components and Technology Conference (ECTC); 2022; pp 707–711.Abel, P. Wet Atomic Layer Etching Using Self-Limiting and Solubility-Limited Reactions. US10982335B2, April 20, 2021.Abel, P. Methods for Wet Atomic Layer Etching of Ruthenium. US11802342B2, October 31, 2023.Abel, P. Methods for Wet Etching of Noble Metals. US20230121246A1, April 20, 2023. Figure 1

Plasma Atomic Layer Etching of Dielectric Materials with Low Global Warming Fluoro-Ether Isomers

In this work, the comparative study of the plasmas of C5F10O and C4H3F7O isomers with low global warming potential (GWP) was conducted in plasma atomic layer etching (ALE) processes of dielectric materials. Plasma atomic layer etching processes for silicon oxide and silicon nitride were developed with perfluoropropyl vinyl ether (PPVE) and perfluoroisopropyl vinyl ether (PIPVE) as C5F10O isomers, and heptafluoropropyl methyl ether (HFE-347mcc3) and heptafluoroisopropyl methyl ether (HFE-347mmy) as C4H3F7O isomers. In the surface fluorination step, the dielectric surfaces were fluorinated with C5F10O and C4H3F7O isomer plasmas and the fluorinated layer was removed by ion bombardment with Ar plasma. The F1s/C1s ratio of the fluorocarbon layer in PPVE plasma analyzed by X-ray photoelectron spectroscopy (XPS) was higher when it is compared to those in PIPVE, HFE-347mcc3, and HFE-347mmy plasmas. In the removal step, ALE window was identified in 50.0 ~ 57.5 V for C5F10O isomers and 50 ~ 60 V for C4H3F7O isomers and the etch per cycle (EPC) of SiO2 was determined to be 5.4, 3.3, 2.1, and 1.8 Å/cycle for PPVE, PIPVE, HFE-347mcc3, and HFE-347mmy, respectively in the ALE window region. The EPC of SiO2 was the highest in the PPVE with a high F1s/C1s ratio of 1.57, and the lowest in the HFE-347mmy with a low F1s/C1s ratio of 1.05. The global warming effect of the exhaust gases was evaluated by carbon dioxide equivalent values determined from the concentration of the exhaust gases. The carbon dioxide equivalent was reduced up to 90%, compared to that of C4F8 plasma. The carbon dioxide equivalent of C4H3F7O isomer plasmas was the lower than that of C5F10O isomer plasmas due to the generation of HF and CO, having much lower GWPs as major reaction products.

Selective Etching of SiO2 over Si3N4 through Varying the Concentration of Fluorine Species

Silicon dioxide (SiO2) and silicon nitride (Si3N4) are widely used as an insulating layer to separate interconnection, due to the characteristic of their wide band gap. As the feature size of semiconductors has been continuously decreasing and their structures have become more complex recent years, SiO2 as an insulating layer is reaching its limit. One of the ways to overcome this limitation, next generation 3D structure semiconductors are developed. In order to manufacture these kinds of devices, a removal of SiO2 is required, however, as both SiO2 and Si3N4 layers are revealed, the highly selective SiO2 etching process over Si3N4 is needed. If the Si3N4 layers were etched during the SiO2 layer etching process, the Si3N4 layer could not be function as an insulating layer and an etch stop layer. As an etchant for the SiO2 layer, hydrofluoric acid (HF) and ammonium fluoride (NH4F) combining solution is mainly used. However, it is known that HF solution also causes the material loss of the Si3N4 layers. Therefore, the study of etching behaviors of SiO2 and Si3N4 in HF solution is needed. In HF solutions, main etching species of SiO2 and Si3N4 exists as fluorine species. The concentration of these fluorine species depends on various conditions, such as pH of the solution or the composition of HF and NH4F. Therefore, the dependence of SiO2 and Si3N4 etching rates on the conditions of HF solutions were investigated.To investigate the etching rates of SiO2 and Si3N4, the blanket SiO2 and Si3N4 wafer in which deposited on Si wafer by the low-pressured chemical vapor deposition method were used, respectively. A patterned SiO2/Si3N4 multi-stack structures were fabricated by plasma-enhanced chemical vapor deposition, to verify whether SiO2 was selectively etched over Si3N4 in HF solution. The HF solutions were prepared by adding various concentrations of HF to deionized water and NH4F was added in some cases. The pH of the HF solution was controlled by adding hydrochloric acid or ammonium hydroxide. The temperature maintained at 25 °C during the etching processes using a water bath. The blanket SiO2 and Si3N4 wafers were immersed in these solutions for 3 and 60 mins, respectively. The etching depth of the SiO2 and Si3N4 films was measured by spectroscopic ellipsometry. The morphology of patterned SiO2/Si3N4 multi-stack structures after etching process was observed using field-emission scanning electron microscopy (FE-SEM). The pH and the concentrations of each fluorine species of the prepared HF solutions were calculated based on the equilibrium constants, molar balance, and charge balance.To obtain the HF solution with the high SiO2 etching selectivity over Si3N4, blanket SiO2 and Si3N4 wafers were etched under various pH and initial concentrations of HF solution. As the pH of the HF solution was increased, at the same initial HF concentration, the SiO2/Si3N4 etching selectivity was increased. Meanwhile, the etching selectivity of SiO2 over Si3N4 was increased with the initial concentrations of HF increased, at a fixed pH of the solution. To investigate the reason for the dependencies of the SiO2 and Si3N4 etching rates on pH and initial concentrations of HF, the concentrations of each fluorine species were calculated. As a result, the etching mechanisms and the etching behaviors of SiO2 and Si3N4 in the HF solutions were suggested. Based on the etching kinetics of SiO2 and Si3N4, a patterned SiO2/Si3N4 multi-stack structure etching conditions were controlled to investigate the SiO2/Si3N4 selective etching ability of the HF solution. The cross-sectional FE-SEM images visually showed that high SiO2 etching selectivity compared to Si3N4 was achieved. As a result, highly selective SiO2 etching without loss of Si3N4 was obtained by adjusting only the concentrations of HF and NH4F, without any special additives through the suggested SiO2 and Si3N4 etching kinetics.

Atomic Layer Processing (ALP): Ubi es et Quo Vadis?

AbstractAtomic Layer Processing (ALP) techniques have transformed materials engineering by enabling atomic/molecular‐level control over composition, fidelity in structure replication, and properties. Tracing its origins to pioneering molecular layering and atomic layer deposition work in the mid‐20th century, this multifaceted field has remarkably diversified to include molecular layer deposition (MLD), atomic layer etching (ALE), area‐selective deposition (ASD), and vapor‐phase infiltration (VPI) processes. ALP is making great impacts across diverse disciplines – facilitating semiconductor miniaturization through ultrathin dielectric films, improving battery materials and engineering catalysts for energy applications, creating bioactive surfaces for advanced biomaterials, and promoting sustainable membranes for environmental remediation. As ALP techniques continue evolving through integration with additive manufacturing, machine learning, and in situ diagnostics, new frontiers in materials design are emerging, driven by the growing focus on environmental considerations like renewable precursors, energy‐efficient processes, and waste minimization. This perspective article examines ALP's historical development, highlights current state‐of‐the‐art applications across selected fields, and provides insights into the anticipated future trajectory, emerging application domains, and the pivotal role of academic‐industry‐research laboratory collaborations in catalyzing ALP innovations and facilitating its widespread adoption as a transformative manufacturing platform.