Threshold Voltage Shift of P-Ch GaN Misfets with Charge Trapping Insulator

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The realization of high-performance p-channel devices and threshold voltage control are desired to achieve GaN CMOS circuits. Recess-gate devices on polarized junction substrates have been reported as candidates for p-channel devices that can be integrated with n-channel devices, including HEMTs [1]. In addition, we have reported that the use of a quasi-atomic layer etching process with nitrogen plasma to fabricate the recessed gate structure improves the MIS interface characteristics and increases the drive current [2]. However, regarding threshold voltage control, the recessed gate structure may not be sufficient. Although control by the back gate is a candidate, other control methods are worth considering for circuit simplicity. In this study, we investigated the threshold control by introducing a charge trapping layer into the gate insulator.Figure 1 shows the schematic structure of p-channel GaN MISFETs with a charge-trapping layer fabricated on a polarization junction substrate. The insulator, Al2O3/HfO2/Al2O3 layer, was formed by atomic layer deposition. A negative threshold voltage shift could be expected when positive charges are trapped in the HfO2 layer or at the HfO2/Al2O3 interfaces.Figure 2 shows the I d-V g characteristics of a p-channel MISFET. V d was set to -3 V, and two consecutive double-sweep measurements were performed. Figure 2(a) shows the results of measurements with a V g range of +5 to -6 V. It shows a large hysteresis, with a negative sweep changing to the on state at a positive voltage and a positive sweep to the off state at a negative voltage. The second sweep also reproduces the first sweep's characteristics. This result can be attributed to the fact that the negative gate voltage introduces positive charges into the charge-trapping layer, resulting in a negative threshold voltage, and that the positive gate voltage completely removes the positive charge from the charge-capture layer, resulting in a positive threshold voltage again. On the other hand, Fig. 2(b) shows that, using the V g range of +2 to -6 V, the threshold voltage of the negative sweep in the second sweep shifts to negative. This result indicates that only partial charge was released from the charge trapping layer, and the remaining charge caused the shift. Also, Fig. 2(c) shows the results of the V g range of 0 to -6 V. The hysteresis at the second sweep is significantly reduced, indicating normally-off operation. This is considered to be a result of the positive charge captured in the charge-trapping layer being retained in the negative gate voltage range.Furthermore, Figs. 2(d), (e), and (f) present the vertical axes of Figs. 2(a), (b), and (c)c in logarithmic form, respectively, and in addition, I g is also shown. The gate leakage current is kept low compared to the drain current, and an on-off ratio of more than five orders of magnitude is obtained. Additionally, there is no significant change in the subthreshold slope due to threshold voltage variation, indicating that the charging and discharging of the charge trapping layer does not significantly affect the carrier transport properties in channel region.In this study, the threshold voltage shift and resulting normally-off operation of p-channel GaN MOSFETs is demonstrated by using a charge trapping layer. The same effect is promising for threshold voltage control of n-channel devices, and this technique is expected to be used for power-saving GaN CMOS circuits with two-dimensional carrier gases. Acknowledgments This work was supported by JSPS KAKENHI Grant Number 21K04172.