Trench Etching Research Articles

Suppression of parasitic JFET effect in trench IGBTs by using a self-aligned p base process

This paper presents the suppression of the parasitic JFET effect in high voltage Trench insulated gate bipolar transistors (IGBTs) by employing a new self-aligned p base process. The parasitic JFET effect is no longer negligible because the lowly doped n − drift region becomes longer and at the same time the cell current density becomes lower in high voltage applications. The self-aligned p base process is based on the use of a common nitride mask for trench etching and p boron diffusion and therefore eliminates an extra process mask. Furthermore, the self-aligned p base structure effectively suppresses the parasitic JFET effect into a small area near the trench source and results in considerably enhanced on-state performance. Extensive numerical simulations using the MEDICI simulator have been carried out and the results show that by using the new self-aligned p base process one can relieve the pressure resulted from processing very deep trenches in high voltage Trench IGBTs.

Deposition of silicon oxychloride films on chamber walls during Cl2/O2 plasma etching of Si

The chemical nature and deposition rate of the silicon oxychloride films deposited on the chamber walls during Cl2/O2 plasma etching of Si were investigated using multiple total internal reflection-Fourier transform infrared spectroscopy. The differences in the infrared spectra of films deposited under different etching conditions were quantified through the Si–O and OSi–Cl absorption band intensities and positions to determine the growth rate and composition of these films. The changes in the film’s deposition rate and composition with rf bias power and O2 flow rate gave insight into the deposition mechanism. Based on our experimental observations, we propose that the silicon oxychloride film is deposited through oxidation of SiClx molecules adsorbed on the reactor walls and suggest a kinetic expression for the film deposition rate. This kinetic expression may also be used judiciously for describing the silicon oxychloride deposition on the sidewalls of etched features in gate etching and shallow trench isolation.

Etching of SiO2 features in fluorocarbon plasmas: Explanation and prediction of gas-phase-composition effects on aspect ratio dependent phenomena in trenches

A model to calculate etching rates in SiO2 features in fluorocarbon plasmas is presented. The model can predict several aspect ratio dependent phenomena such as reactive ion etching (RIE) lag, etch stop, inverse RIE lag, and aspect ratio independent etching (ARIE) at least for a limited range of aspect ratio values. The model includes three components: (a) a surface model for open area etching of SiO2 (and Si) [Gogolides et al., J. Appl. Phys. 88, 5570 (2000)]; (b) a flux calculator, which calculates local fluxes on each elementary surface of the feature being etched; and (c) a coupling of the two models (a) and (b), the focal point of coupling being the simultaneous calculation of the neutral species fluxes and the corresponding effective sticking coefficients. The model is applied for trench etching and the gas phase conditions considered correspond to a generic fluorocarbon gas. A different approach is presented by which the gas phase composition is divided (i.e., mapped) into regions leading to (a) deposition, (b) RIE lag with no etch stop, (c) intense RIE lag and etch stop, (d) inverse RIE lag, and (e) ARIE. Based on the proposed model an explanation of the aspect ratio dependent phenomena and ARIE is attempted, and a comparison with experimental data is done. Two parameters were found to be important in this explanation: the polymer surface coverage at the bottom of the etched feature and the effective sticking coefficients of the neutral species on the sidewalls of the etched feature.

Electrostatically driven microgripper

Abstract In this work we report on microactuators and microgrippers fabricated from SOI (silicon-on-insulator) wafers by a surface and bulk micromachining fabrication technology. The main advantages of this technology are: (a) large thickness of the devices (10–40 μm) resulting in devices which are stable against disturbing forces perpendicular (z-direction) to the ground plate; (b) the small number of fabrication steps required. Only three steps are required: lithography, trench etching of silicon, and release of movable parts (selective wet etching of the buried oxide layer). The linear motion (‘pull action’) of the microactuator is converted into a rotational gripping motion by a system of elastic spring beams. At a voltage of 90 V, the gripper tweezers are closed.

Response surface methodology applied to silicon trench etching in Cl 2/HBr/O 2 using transformer coupled plasma technique

The response surface methodology (RSM) has been used in this study to investigate the effect of various control factors on the performance of silicon trench etch in high-density transformer coupled plasma (TCP) on Cl 2/HBr/O 2-based chemistry. The TCP source power, bias power, and Cl 2 content of the Cl 2/HBr mixture were the process variables. The etch rate and sidewall profile angle were employed as the response items for RSM analysis. Quantitative relationships between etching characteristics and process parameters have been established. The possible mechanisms are also proposed to explain the different sidewall profile angles as varying the parameters.

Challenges in Etching of OSG Low- K Materials for Dual-Damascene Metallization

AbstractIssues associated with trench etching in low-k OSG (organosilicate glass) films for dual damascene applications and in particular for “via-first” integration scheme were the focus of this study. As a result of designed experiment in dipole ring magnet (DRM) etcher with C4F8/N2/Ar gas mixture the trench process was established with sidewall profile 89° and flat bottom. Selectivity obtained was enough to pursue etch processes using planarizing BARC (bottom antireflective coating) for additional via bottom protection. BARC fill in vias and BARC opening time were tuned to reduce generation of polymers during etch. Effective combination of dry /wet clean recipes was developed for removal of post-RIE (reactive ion etching) residues without significant changes in OSG k-value. Optimized processes were successfully used for creating dual damascene structure complying with integration requirements for 0.13 μm design rules.

Modeling the High-Voltage Gas-Discharge-Plasma Etching of SiO2

The dry etching of trenches in SiO2 by high-voltage gas discharge is studied theoretically and experimentally. General relations between etch rate and process parameters are established. The formalism is confirmed by experiment with a CF4 plasma.

Dual Damascene Etching Process Using Sacrificial Spin-on-Glass Film

The dual damascene (DD) formation process for sub 0.2 µm feature size devices has been investigated. The via-first DD process, where via holes are first formed, followed by trench formation, used the antireflection film in via holes after the trench pattern lithography process. In subsequential trench etch process, crownlike etch residues of SiO2 were formed around via holes due to etch inhibiting effect of antireflection films in via holes. A spin-on-glass (SOG) film is filled in via holes as a sacrificial film before trench pattern lithography was used. It could eliminate the crownlike etch residues because of the absence of an antireflection film in via holes. Moreover, it could give via holes a rounded profile at their top edges. This DD process used for fabricating films with no etch residues and rounded via holes reduces the aspect ratio of via holes and was confirmed to be effective for subsequential metal filling process.

1D Bragg reflector in the Tomonaga–Luttinger liquid regime and Fermi liquid regimes

Employing an array of shallow etched trenches aligned transverse to current flow, we have fabricated long (1– 2 μm ) split-gate quantum wires with weak periodic potential modulation on a GaAs/AlGaAs 2DEG wafer, thereby realizing a 1D Bragg reflector at a very low temperature. In the presence of the first and second edge states, i.e. in the Fermi liquid regime, we observe two groups of conductance dips due to the spin-separate reflection resonances. On the other hand, in the weak magnetic field range, we observe a dip of conductance with temperature as a signature of the Tomonaga–Luttinger liquid effects.

Application of magnetic neutral loop discharge plasma in deep silica etching

The electron temperature Te is one of the key parameters for process plasma because the decomposition of most reactive gases depends on the kinetic energy of electrons in the plasma. Pressure is another important parameter in the etching process for microelectromechanical systems (MEMS). Low pressure can avoid etch product substrate redepositing by reducing the collision between neutral particles and etch products in the gas phase. Also, low pressure may reduce the scattering of incident ions in the sheath that may reduce the negative taper angle for trench etching. Therefore, this study is focused on low pressure (<0.67 Pa), low Te plasma production for optical MEMS etching processes. To reduce the Te and keep the high density of the plasma, use of a parallel turn antenna was proposed and it was applied in magnetic neutral loop discharge plasma, where the Te is desirably reduced to about 2.5 eV while the density is about 1.2×1011 cm−3 at pressure of 0.2 Pa. With this improvement in plasma production, fused quartz and chemical vapor deposition SiO2 were successfully etched in a trench 5–40 μm deep at a high etch rate of over 500 nm/min. The vertical angles are about 90° and the surface roughness is less than 50 nm as evaluated by a scanning electron microscope picture, where Cr, WSi and Si were used as hard masks of SiO2 in order to achieve the selectivity required.

Trench etch processes for dual damascene patterning of low-k dielectrics

The use of dual damascene patterning for integration of Cu with low-k dielectric films has introduced new challenges for plasma etch processes. With a via-first dual damascene approach, an important issue for trench etch is defect formation (i.e., oxide ridges) around vias which can degrade device reliability. The use of low-k films as the dielectric material adds additional complexity and more limitation on the etch process parameters. This article discusses the development of etch processes that meet the special requirements for Cu/low-k dual damascene trench etch. All experiments were conducted in a medium-density TEL dipole ring magnet system. The dielectric film used here was an organosilicate glass (OSG). Using C4F8/N2/Ar chemistry, a trade-off was observed between etch rate and oxide ridge formation. The N2:Ar ratio was found to be the key parameter in controlling the severity of the oxide ridges, but eliminating the ridges using the N2:Ar ratio resulted in a low OSG etch rate and poor throughput. However, we found an alternative method which achieves a high OSG etch rate while maintaining critical dimension control and ridge-free conditions. The effect of various process parameters on the OSG etch rate and ridge formation is detailed. A comparison of experimental results against numerical simulations of C4F8-based bulk plasmas with varying gas flow ratios is also reported.

Understanding the evolution of trench profiles in the via-first dual damascene integration scheme

The introduction of copper interconnects into integrated circuits has increased the use of dual damascene dielectric etch applications because copper films are difficult to plasma etch. Fencing and faceting around the via hole during the trench etch of the via-first dual damascene integration scheme are particularly detrimental and can lead to problems during copper metallization and ultimately to device failure. Therefore, it is imperative that the evolution of these features be understood so that they can be avoided. In this article we will begin with an overview of the via-first dual damascene integration scheme. Experimental results will then be presented that indicate the evolution of these features is heavily dependent upon the existing via profile and whether bottom antireflection coating and/or photoresist is in the via hole prior to starting the trench etch. An empirical model for fence formation was then confirmed by a simple profile simulator written in Visual Basic. Finally, several options for avoiding the evolution of fencing and faceting during the trench etch will be proposed.

Oxide Dual Damascene Trench Etch Profile Control

A systematic study of trench profile evolution in a medium-density oxide etch reactor is presented. A Langmuir site balance model is developed in the limit of unity sticking coefficient which exhibits a flat etch front as is frequently required for dual damascene applications. The model indicates that it is desirable to operate in a neutral-limited ion-assisted etch regime. Physical sputtering is also shown to be necessary, but this etch contribution must be kept small with respect to the ion-assisted etch rate. The model also indicates how either microtrenching or bottom rounding may be controlled or avoided altogether. Model predictions are compared with experimental data obtained from a Lam Research 4520XLE medium density reactor. This work includes a study of the trench bottom rounding dependencies upon pressure, etch time, aspect ratio, and process gas flow for a fluorocarbon-based etch process. The model is shown to qualitatively capture experimentally observed process trends. In some regimes, good quantitative agreement with observed measurement is seen. It can thus serve as a useful guide for trench etch process development. © 2001 The Electrochemical Society. All rights reserved.

The dependence ofUMOSFET characteristics and reliability on geometry andprocessing

We have examined the impact of trench processing and trench anddevice cell geometries on the characteristics of a singlen-channel U-shaped trench metal-oxide-silicon field-effecttransistor (n-UMOSFET) and a device cell comprising severaln-UMOSFETs. The geometrical parameters investigated includedthe trench depth and width, the trench cross-section and thedevice cell pitch. We have found out that the geometry does notaffect the electron mobility in the channel; however, theeffects of the geometry on the characteristics of the isolateddevice or device cell are manifested on the spreading resistance of thedrain end. Trench processing, in the form of trench etching,trench cleaning and subsequent gate-oxide growth, is observed toprimarily influence the n-UMOSFET's immunity to electricalstress, which is studied using charge pumping current andgate-oxide breakdown measurements. It is shown that thegate-oxide edge adjacent to the drain and the oxide/siliconinterface overlapping the drain are the regions most susceptibleto degradation by Fowler-Nordheim stress. Theseobservations coupled with results from scanning electronmicroscopy suggest that the gate-oxide growth non-uniformity aswell as its condition at the trench corners are the key factorsin determining the n-UMOSFET's reliability.

Profile Control of SiO2 Trench Etching for Damascene Interconnection Process

The purpose of the present study is to reveal a microtrench generation mechanism in the damascene trench etch process for SiO2 film. Experiments are discussed for the CO gas flow and the pressure change, employing a C4F8/CO magnetron etch system. Increasing the CO gas flow or the pressure prevents the microtrench generation. Moreover, the microtrench ratio A/B that is defined by the depth at the edge of the trench bottom, A and the trench depth at the center of the trench bottom, B becomes higher in accordance with increasing larger space size. In previous reports, the main effect of CO gas and pressure increase is identified as decreasing CFx radical density by dilution of C4F8 or by increasing the residence time. The reduction of CFx radical flux may prevent microtrench generation by decreasing the formation of fluorocarbon film at the trench bottom. These results suggest that the microtrench generation is caused by thicker formation of fluorocarbon films at the center of the trench bottom which has a larger solid angle than at the edge of the trench bottom.

Study of a mechanically clamped cryo-chuck device in a high density plasma for deep anisotropic etching of silicon

This article presents a study concerning a cryo-chuck device used in an inductively coupled plasma reactor for deep anisotropic etching of narrow trenches (2 μm wide) in silicon wafers of 5 in. in diameter. Thermal mechanisms in a mechanically clamped cryo-chuck system have been studied. First, wafer deformations have been measured in the chuck device. Deformations occur because of the helium backside pressure allowing thermal transfer to cool the wafer. In a second step, these deformations have been used in calculations considering the heat transfers in the substrate. In a last step, in situ temperature measurements have been made on wafers during a process using a LUXTRON® probe. This study shows the influence of the backside helium gap variation and the clamping ring temperature on the uniformity of substrate cooling.

A Microwave High-Density Plasma Source for Submicron Silicon IC Technology

A microwave high-density plasma source is applied for room-temperature deposition of thin SiO2films, filling of submicron trenches, local planarization of the chip surface, etching of deep trenches in the insulator, and resist stripping after ion implantation. The structures obtained meet stringent demands for current technologies. Uniform processing of wafers up to 300 mm in diameter is demonstrated.

2.4F/sup 2/ memory cell technology with stacked-surrounding gate transistor (S-SGT) DRAM

This paper proposes 2.4F/sup 2/ memory cell technology with stacked-surrounding gate transistor (S-SGT) DRAM. One unit of the S-SGT DRAM is formed by stacking several SGT-type cells in series vertically. The SGT-type cell itself arranges gate, source, drain and plate on a silicon pillar vertically. Both gate and plate electrode surround the silicon pillar. Subsequently applied trench etching and sidewall spacer formation during S-SGT DRAM formation causes a step-like silicon pillar structure. Due to these steps, gate, plate and diffusion layer in one S-SGT DRAM unit are fabricated vertically by a self-aligned process. The cell size dependence of the self-aligned-type S-SGT DRAM was analyzed with regard to the above step widths and the number of cells in one unit. As a result, the cell design for minimizing the cell size of this device has been formulated. By using the proposed cell design, it is demonstrated by process simulation that the S-SGT DRAM in 0.5 /spl mu/m design rule can achieve a cell size of 2.4F/sup 2/, which is half of the cell size of a conventional SGT DRAM cell (4.8F/sup 2/). Therefore, the S-SGT DRAM is a promising candidate for future ultra high density DRAMs.

Enhanced wavelength tuning of an InGaAsP-InP laser with a thermal-strain-magnifying trench

We have used temperature-dependent strain from differential thermal expansion to increase the temperature tuning rate, dλ/dT, of the modal wavelength of an InP-based laser. The effectiveness of the strain may be further enhanced with a deep trench etch beneath the laser waveguide. We have obtained a 50% increase in the tuning rate, without degradation of the threshold current, and a maximum increase of 86%.

Shadow-epitaxy for flexible crystalline thin-film silicon solar cell design

Crystalline silicon thin-film solar modules require a cost-effective means for the fabrication of an integrated series connection. We introduce selective epitaxy by ion-assisted deposition through shadow masks for the integrated series connection of ultrathin monocrystalline and textured Si solar cells. The series connection is made in situ during Si-film deposition thus avoiding any trench etching. The open-circuit voltage of an experimental mini-module consisting of six cells is six times as large as the open-circuit voltage of a single cell. Epitaxy through shadow masks also permits the in situ realization of parallel multi-junction solar cells. The experimental quantum efficiency analysis of a parallel multi-junction device with three junctions reveals an enhanced carrier collection. The apparent effective diffusion length of the multi-junction cell is three times larger than that for a conventional single-junction device.