Etch Stop Research Articles

An Alternate Approach to Backside Thinning: A Doping Selective Silicon Wet Etch

Backside illuminated (BSI) technologies have been commonly used in CMOS image sensors and are finding a renewed interest for images and detectors for LiDAR application that has been driven by the automotive industry. As the integration of signal processing into microelectronic detectors progresses, active area and fill factor become issues for monolithic solutions. Processing the detector and readout circuitry (ROIC) on different wafers allows for the separate optimization of cost and performance. As a result, backside thinning had become a critical step in the process flow for BSI technologies, with the backside of wafers needed to be thinned down to within microns of active area to effectively couple incident photons.Conventional approaches to backside thinning utilize the buried oxide layer of an SOI wafer, which acts as a reliable etch stop since there are both wet and dry silicon etchants with suitable selectivity to the oxide. Despite the robust method for SOI wafer thinning, there are a few key disadvantages that attract the exploration of alternative routes. For instance, SOI wafers are expensive when compared to conventional epitaxial substrates, with the price reaching up to 5 times more depending on quantities. Additionally, the crystallinity of the silicon film on SOI wafers is typically lower than that of epitaxial silicon, which can lead to a decrease in device performance. Thus, to reduce cost and improve performance, an etch process that uses standard epitaxial substrates provides a favorable alternative. However, a method that can reliably, and precisely thin epitaxial substrates is needed. A possible approach would be to exploit a difference in dopant concentration between the substrate and epitaxial silicon. Doing so would require a wet etchant with sufficient selectivity to etch one of the silicon and use the other as an etch stop. The difficulty with this approach is that a change in dopant concentration is not as chemically distinct as a change in material. As such, reliably achieving precise and uniform final silicon film thicknesses presents a challenge that requires optimization of chemistry. Moreover, for such a method to be implemented on a production scale a working understanding of chemical bath life and wafer to wafer etch repeatability over a large sample size is necessary.This study provides a comprehensive examination on the feasibility and reliability of thinning epitaxial substrates and provides an outline for the development of a wet process that rapidly etches heavily doped substrate silicon (etch rate >5 µm/min) and uses a lightly doped device silicon layer as an etch stop (etch rate <0.2 µm/min). Optimal etchant compositions are investigated to identify a suitable chemistry for the required etch rates and selectivity. Furthermore, the effect of bath life and spiking/regeneration schemes on the performance of the etchant in a in a recirculated chemistry application is then explored. After preliminary development work was completed, the chemistry was used to thin a series of epitaxial wafers to explore the wafer-to-wafer repeatability of the developed process. Acknowledgements This project has received funding from the ECSEL Joint Undertaking (JU) under grant agreement No 876659 (iRel40). The JU receives support from the European Union’s Horizon 2020 research and innovation programme and Germany, Austria, Slovakia, Sweden, Finland, Belgium, Italy, Spain, Netherlands, Slovenia, Greece, France, Turkey. Figure 1

Reclaim Mode Post Etch Residue Remover Solutions for Advanced Technology Nodes

Back-end-of-line (BEOL) processing for creation of vias in advanced technology node semiconductor manufacturing warrants a wet chemistry capable of removing post-etch residue (PERR), titanium nitride hardmask (TiN HM) and etch stop layer (ESL), while being compatible with metals, such as copper, tungsten and cobalt. In accordance with BASF’s core competency of innovating sustainable solutions with minimal environmental impact, our reclaim mode BEOL PERR chemistries allow semiconductor manufacturers to minimize not only their cost of ownership (COO) but also their waste footprint.BASF’s reclaim mode PERR chemistries, when mixed with appropriate amount of hydrogen peroxide, facilitate oxidative wet etching of TiN HM. In this paper, we demonstrate that optimization of formulation and spiking protocol extends the bath lifetime of these chemistries beyond 24hr, which is significant improvement vis-à-vis current industry standard of single use (drain mode) chemistries. Beaker-level bath lifetime investigation of BASF’s leading formulation confirms that TiN etch rate (ER) and bath pH are stable for 48hr (Fig. 1a) when bath is loaded with commensurate amount of Ti ions. Beaker-level performance was also corroborated by 300mm wafer level assessment. BASF’s reclaim mode PERR chemistries with bath lifetime greater than 8hr offer progressively favorable cost of ownership (COO) vis-à-vis drain mode chemistry (Fig. 1b). Figure 1

Understanding of Etching Mechanism of Si3N4 Film in H3PO4 Solution For The Fabrication of 3D NAND Devices

Silicon nitride (Si3N4) has been widely used as an insulating or etch stop layer in the semiconductor devices [1]. For example, in a 3D V-NAND flash memory manufacturing process, Si3N4 is alternately stacked with silicon oxide (SiO2) to form a NAND structure. Here, it is necessary to selectively etch Si3N4 avoiding etching of SiO2 in the repeated Si3N4/SiO2 multi-stack layers. In general, phosphoric acid (H3PO4) is used to selectively etch Si3N4 against SiO2 [2]. However, since the concentration of H3PO4 solution changes with the evaporation of H2O, it is not easy to determine the concentration dependence of Si3N4 etching rate in H3PO4 solution. In order to properly control the shape of the 3D V-NAND structure, it is necessary to extensively understand the effect of H3PO4 concentration on the Si3N4 etching. The study of Si3N4 etching has been mainly focused on the effect of additives in H3PO4 on the behavior of Si3N4 etching to solve the issue such as oxide regrowth so far [3, 4]. Fundamental study of the Si3N4 etching reaction mechanism in H3PO4 is lacking. In this study, the Si3N4 etching mechanism in H3PO4 solution is elucidated systematically.For the investigation of Si3N4 etching reaction mechanism, LPCVD Si3N4 blanket wafer and Si3N4/SiO2 multi-stack layered trench wafer were used. Etching experiments of of Si3N4 were conducted in 10-95 wt% H3PO4 solutions at 160 °C. Spectroscopic ellipsometry and field emission scanning electron microscopy were used to measure the etching rate of Si3N4 after etching process.First, the changes in etching rate of Si3N4 in the various concentrations of H3PO4 solution were investigated. As shown in Fig. 1, according to our kinetic calculation and experiments, etching rate of Si3N4 increased as the H3PO4 concentration increased until the concentration of H3PO4 reaches a certain concentration that produced the highest etching rate. However, etching rate of Si3N4 decreased with the concentration of H3PO4 beyond the critical H3PO4 concentration. According to the results, there may be two concentrations of H3PO4 solution which produce an identical etching rate of Si3N4. It is also suggested that not only H3PO4 but also H2O plays an important role in the Si3N4 etching kinetics.To investigate the role of H2O and H3PO4 in the etching reaction of Si3N4, kinetic isotope effect (KIE) of Si3N4 etching reaction in H3PO4 solution was used. KIE provides information about which reactant determines the rate-limiting step. In this study, each reactant of Si3N4 etching reaction, H2O or H3PO4, was substituted with D2O and D3PO4, respectively. Then, etching of Si3N4 was conducted in four different solutions. As shown in Fig. 2, when H3PO4 was replaced by D3PO4, the Si3N4 etching rate was not significantly changed. However, when H2O was replaced by D2O, the Si3N4 etching rate decreased by 30 %. Therefore, it is thought that rate-limiting step of the Si3N4 etching reaction is determined by an elementary reaction related to H2O rather than H3PO4.Based on the above results, Si3N4 etching reaction mechanism was suggested. First, the Si3N4 surface termination (-NH2) is substituted with H2PO4 -, which is a weak nucleophile, by an SN1-like reaction. When H2PO4 - binds to Si, the backbone of Si3N4 is weakened because the electronegativity of O (3.44) is greater than N (3.04). Next, the Si-N of the weakened backbone of Si3N4 is substituted with Si-OH by an SN2-like reaction of H2O. This SN2-like reaction is considered as a rate-limiting step. It is believed that understanding of etching mechanism of Si3N4 in H3PO4 solution will improve selective etching process of Si3N4 for the integration of 3D V-NAND.

Study of Etch Stop Layer on Characteristics of Amorphous Aluminum Oxide Thin Film

To protect the active layer, which are inter layer dielectrics (ILD) and metal lines, from being damaged by UV laser during the etching process, etch stop layers (ESL) are used in patterning process of the integrated circuits (ICs) fabrication in back end of line (BEOL). The ESL material should have a higher etch selectivity than the active layer. Therefore, it must have a low dielectric constant and high chemical resistance. Aluminum oxide compounds (AlOx, AlOC, AlON, etc.) are highly suitable for use as ESL due to the low dielectric constant between about 4 and 9, high etch selectivity, high density (2.5-3.8 g/cm3) and pattern transfer capability. We focused on lowering the dielectric permittivity and increasing the density by controlling the precursor/reactant pulsed time of atomic layer deposition (ALD).

Two-dimensional guided-mode resonance gratings with an etch-stop layer and high tolerance to fabrication errors.

Guided-mode resonance (GMR) bandpass filters have many important applications. The tolerance of fabrication errors that easily cause the transmission wavelength to shift has been well studied for one-dimensional (1D) anisotropic GMR gratings. However, the tolerance of two-dimensional (2D) GMR gratings, especially for different design architectures, has rarely been explored, which prevents the achievement of a high-tolerance unpolarized design. Here, GMR filters with common 2D zero-contrast gratings (ZCGs) were first investigated to reveal their differences from 1D gratings in fabrication tolerance. We demonstrated that 2D ZCGs are highly sensitive to errors in the grating linewidth against the case of 1D gratings, and the linewidth orthogonal to a certain polarization direction has much more influence than that parallel to the polarization. By analyzing the electromagnetic fields, we found that there was an obvious field enhancement inside the gratings, which could have a strong effect on the modes in the waveguide layer through the field overlap. Therefore, we proposed the introduction of an etch-stop (ES) layer between the gratings and the waveguide-layer, which can effectively suppress the interaction between the gratings and modal evanescent fields, resulting in 4-fold increased tolerance to the errors in the grating linewidth. Finally, the proposed etch-stop ZCGs (ES-ZCGs) GMR filters were experimentally fabricated to verify the error robustness.

An Alternate Approach to Backside Thinning: A Doping Selective Silicon Wet Etch

Backside illuminated technologies have been used in complementary metal–oxide–semiconductor image sensors for years and are finding a renewed interest and are being investigated for imagers and detectors in light detection and ranging applications. Coupled with the improved performance facilitated through 3D integration, the thinning of bonded wafers has become a crucial processing step. In this study, an alternate and potentially more cost-effective method has been explored using an HNA (hydrofluoric, nitric, acetic)wet etch for backside thinning of bonded epitaxial P+/P- silicon wafers. By utilizing a dopant concentration gradient, P+ silicon is selectively etched and P- silicon can be effectively used as an etch stop. Several HNA concentrations were explored to determine ratios that yield high P+ silicon etch rates while maintaining high P+/P- selectivity. Furthermore, bath life, spiking scheme, and repeatability were examined using a large wafer sample size with the goal of developing a full process flow.

Reclaim Mode Post Etch Residue Remover Solutions for Advanced Technology Nodes

Back-end-of-line (BEOL) processing for creation of vias and trenches in advanced technology node semiconductor manufacturing warrants a wet chemistry capable of removing post-etch residues (PERR), titanium nitride hardmask (TiN HM) and etch stop layer (ESL), while being compatible with metals, such as copper, tungsten and cobalt. In accordance with BASF’s core competency of innovating sustainable solutions with minimal environmental impact, our reclaim mode BEOL PERR chemistries allow semiconductor manufacturers to minimize not only their cost of ownership (COO) but also their waste footprint. BASF’s reclaim mode PERR chemistries, when mixed with appropriate amount of hydrogen peroxide, facilitate oxidative wet etching of TiN HM. In this paper, we demonstrate that optimization of formulation chemistry and spiking protocol extends the bath lifetime of reclaim mode PERR chemistries beyond 24hr, which is a significant improvement vis-à-vis current industry standard of single use (drain mode) chemistries. Beaker-level bath lifetime investigation of BASF’s formulation confirms that TiN etch rate (ER) and bath pH are stable for 48hr when bath is loaded with commensurate amount of Ti ions. Beaker-level performance was also corroborated by 300mm wafer level assessment. BASF’s reclaim mode PERR chemistries with bath lifetime greater than 8hr offer progressively favorable cost of ownership (COO) vis-à-vis drain mode chemistry.

Patterning challenges for direct metal etch of ruthenium and molybdenum at 32 nm metal pitch and below

Ruthenium and molybdenum are candidate materials to replace Cu as the back-end-of-line interconnect metal for the tightest pitch features for future technology nodes. Due to their better figure of merit ρ0 × λ (ρ0 bulk resistivity, λ electron mean free path), it is expected that the resistance of &amp;lt;10 nm wide Ru and Mo metal lines can be significantly reduced compared to Cu. An important advantage for Ru and Mo is that both materials, in contrast to Cu, can be patterned by means of so-called direct metal etch, through reactive ion etching or atomic layer etching and can potentially be implemented without barrier. An integration scheme with direct metal etch instead of damascene patterning could simplify the overall patterning flow and eventually opens the possibility for exploring new integration concepts and patterning approaches. However, the learning on direct metal etch of Ru and Mo in the literature is scarce, especially at the relevant dimensions of today's interconnects. In this work, we will focus on the major patterning challenges we have encountered during the development of direct metal etch processes for Ru at 18 nm pitch and Mo gratings at 32 nm pitch. We have observed that the direct metal etch of Ru at these small dimensions is impacted by the growth of an oxidized layer on the sidewalls of the hard mask, which originates from the sputtering of the hard mask in combination with the O2-based Ru etch chemistry. This results in a narrowing of the trenches to be patterned and can easily lead to an etch stop in the smallest features. We will discuss several mitigation mechanisms to remove this oxidized layer, as well as to avoid the formation of such a layer. For patterning Mo with a Cl2/O2-based chemistry, the major patterning challenges we encountered are the insufficient sidewall passivation and the oxidation of the patterned Mo lines. The sidewall passivation issue has been overcome with an in situ thin SiO2-like deposition after partial Mo etch, while a possible mitigation mechanism for the Mo oxidation could be the in situ encapsulation immediately after Mo patterning.

On the elastic tensors of ultra-thin films: A study of ruthenium

Critical Dimensions (CD) of electronic device patterns have been reduced to the order of a few nanometers due to the extreme miniaturization of devices, setting the thickness of some of its constituting materials at the (sub-)nanometer level. At these length scales, the mechanical integrity of the constituting films begin to deviate strongly from their bulk material values, introducing a set of undesired reliability side-effects such as mechanical failure, delamination, and strain enhanced diffusion. Understanding the fundamentals behind these aspects is critical to further sustain technology developments. We use Density Functional Theory (DFT) to quantify how the mechanical properties of sub-10 nm thick films depend on their thickness and surface roughness, specifically for Ru [001], which is currently being investigated for CMOS interconnects, an antiferromagnetic layer, and an etch stop layer in Magnetic Random Access Memories (MRAM). Our findings underline that overlooking the impact of film dimensions and surface roughness on the mechanical properties at these CDs, hampers the optimization of device performances and challenges the validity of many experimental and modeling techniques relying on the assumption that bulk mechanical properties are preserved.

Top-emitting 940-nm thin-film VCSELs transferred onto aluminum heatsinks

Thin-film vertical cavity surface emitting lasers (VCSELs) mounted onto heatsinks open up the way toward low-power consumption and high-power operation, enabling them to be widely used for energy saving high-speed optical data communication and three-dimensional sensor applications. There are two conventional VCSEL polarity structures: p-on-n and n-on-p polarity. The former is more preferably used owing to the reduced series resistance of n-type bottom distributed Bragg reflection (DBR) as well as the lower defect densities of n-type GaAs substrates. In this study, the p-on-n structures of thin-film VCSELs, including an etch stop layer and a highly n-doped GaAs ohmic layer, were epitaxially grown in upright order by using low-pressure metalorganic chemical vapor deposition (LP-MOCVD). The p-on-n structures of thin-film VCSELs were transferred onto an aluminum heatsink via a double-transfer technique, allowing the top-emitting thin-film VCSELs to keep the p-on-n polarity with the removal of the GaAs substrate. The threshold current (Ith) and voltage (Vth) of the fabricated top-emitting thin-film VCSELs were 1 mA and 2.8 V, respectively. The optical power was 7.7 mW at a rollover point of 16.1 mA.

Thermally Robust Perpendicular SOT-MTJ Memory Cells With STT-Assisted Field-Free Switching

A back-end-of-line compatible 400 °C thermally robust perpendicular spin-orbit torque magnetic tunnel junction (p-SOT-MTJ) memory cell with a tunnel magnetoresistance ratio of 130% is demonstrated. It features an energy-efficient spin-transfer-torque-assisted field-free spin-orbit torque (SOT) switching and a novel interface-enhanced synthetic antiferromagnet (SAF). The optimal SAF with a Ru (9 Å) spacer sandwiched by Co/Pt multilayers has a high SAF coupling field of 2.8 kOe. The parallel magnetic coupling between the CoFeB-based reference layer and the bottom Co/Pt multilayer is enhanced by a magnet-coupling face-centered cubic textured Co/Pt (5 Å) multilayer buffer. The thermally induced Pt–Fe interdiffusion is effectively reduced by the W (3 Å) trilayers of texture-decoupling diffusion multibarrier. The Ta/ <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">$\beta $ </tex-math></inline-formula> -W and TaN/ <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">$\beta $ </tex-math></inline-formula> -W composite SOT channels are thick enough to be the etching stop and sustain 400 °C annealing without transforming to <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">$\alpha $ </tex-math></inline-formula> -W. Using the harmonic Hall voltage measurement, the Ta/W and TaN/W channels exhibit the large effective spin Hall angle of approximately −0.21 and −0.27, respectively. Scaling magnetic tunnel junction (MTJ) down to 30 nm size can reduce the switching time due to single-domain switching based on the micromagnetic simulation. The damping constant of ~0.018 is obtained by the ferromagnetic resonance measurement. A bigger damping constant reduces the switching time as predicted by the calibrated simulation.

In situ implementation of silicon epitaxial layer on amorphous SiO2 using reduced-pressure chemical vapor deposition

With the increasing power demand of system-on-chip structures, an ultrathin body is increasingly important owing to its low power leakage; silicon-on-insulator (SOI) technology is used to fabricate such ultrathin platforms. However, the contemporary SOI process and the wafer itself are complex and expensive. In this study, we developed an easy SOI fabrication process that can be implemented on any desired local area of a bulk silicon wafer using the commercially implemented reduced-pressure chemical vapor deposition technique. A local SOI was fabricated through the selective epitaxial growth of silicon, which can also be grown laterally on top of amorphous SiO2 patterned with a 1 μm-wide silicon seed zone and an etch stopper with dimensions of 20 × 100 μm. The local SOI, processed to a thickness of 100 nm or less by chemical mechanical polishing, exhibited a highly crystalline state, as confirmed by cross-sectional imaging and diffraction pattern analysis, surface roughness analysis, and wide-range epitaxy analysis. The local SOI exhibited a surface roughness of 0.237 nm and maintained a perfect (100) crystal plane, identical to that of the silicon wafer, under optimized process conditions. We successfully fabricated reconfigurable transistors on the present local SOI, which implies that contemporary silicon electronics can take advantage of SOI devices on its own platform.

Single-step reactive ion etching process for device integration of hafnium-zirconium-oxide (HZO)/titanium nitride (TiN) stacks

The integration of new materials such as high-k dielectrics or metals into advanced CMOS gate stacks has led to major developments in plasma etching. The authors present a study which is dedicated to the etching of amorphous hafnium zirconium oxide (HZO) and titanium nitride (TiN) layers with Ar/Cl2 chemistry in one single step. By adjusting the gas ratio and the inductively coupled plasma power, the etching process is shown to have a slow and well controllable etch rate for HZO and TiN. Additionally, a high selectivity between both materials and SiO2 can be achieved. Gate stack etching was successfully demonstrated and transmission electron microscopy-images revealed good anisotropic etching for HZO and TiN with an etch stop in SiO2 without damaging the silicon underneath. The process is further applied for the fabrication of metal-ferroelectric-metal capacitors, here TiN-HZO-TiN, and the feasibility of the chosen material combination is proven by electrical characterization. The strategy of using low temperature plasma-enhanced atomic layer deposition for TiN-deposition and forming gas anneal after structuring leads to high remanent polarization-values.

Impact of selective thermal etching in mixed H2/NH3 atmosphere on crystal quality of AlGaN/GaN heterostructures

We investigated the impact of selective thermal etching in a mixed hydrogen and ammonia atmosphere on the crystal quality and electrical characteristics of Ga- and N-polar AlGaN/GaN heterostructures. It was revealed that the etching rate of N-polar GaN is lower than that of Ga-polar GaN under our experimental conditions, and they showed a similar dependence on process temperature with almost the same activation energies. We demonstrated the use of a thin AlGaN layer as a selective etching stopper for both Ga- and N-polarity. The AlGaN stoppers exhibited a smooth surface after etching the GaN layer above them. As for the electrical characteristics, there was no significant degradation in the mobility of the two-dimensional electron gas. The results indicate that selective thermal etching is a promising technique for device fabrication and is especially suitable for precise GaN layer removal when GaN-based devices are fabricated with an epitaxial layer transfer technique.

Smooth GaN membranes by polarization-assisted electrochemical etching

III-nitride membranes offer promising perspectives and improved device designs in photonics, electronics, and optomechanics. However, the removal of the growth substrate often leads to a rough membrane surface, which increases scattering losses in optical devices. In this work, we demonstrate membranes with etched surface roughness comparable to that of the as-grown epitaxial material, accomplished by the implementation of a properly designed built-in polarization field near the top of the sacrificial layer from an AlInN interlayer, which is polarization-mismatched to GaN. This leads to a steeper reduction in free carrier density during the electrochemical etching of the sacrificial layer, limiting the etching current and thus causing an abrupter etch stop. As a result, the root mean square roughness is reduced to 0.4 nm over 5 × 5 μm2. These smooth membranes open attractive pathways for the fabrication of high-quality optical cavities and waveguides operating in the ultraviolet and visible spectral regions.

Epitaxial Growth of Active Si on Top of SiGe Etch Stop Layer in View of 3D Device Integration

We describe challenges of the epitaxial Si-cap/Si0.75Ge0.25//Si-substrate growth process, in view of its application in 3D device integration schemes using Si0.75Ge0.25 as backside etch stop layer with a focus on high throughput epi processing without compromising material quality. While fully strained Si0.75Ge0.25 with a thickness >10 times larger than the theoretical thickness for layer relaxation can be grown, it is challenging to completely avoid misfit dislocations at the wafer edge during Si-growth on top of strained Si0.75Ge0.25, even for thinner Si0.75Ge0.25 layers and when growing the Si-cap layer at a lower temperature. Extremely sensitive characterization methods are mandatory to detect the extremely low density of misfit dislocations at the wafer edge. Light scattering measurements are most reliable. The epitaxial Si-cap/Si0.75Ge0.25//Si-substrate layer stacks are stable against post-epi thermal processing steps, typically applied before wafer-to-wafer bonding and Si-substrate and Si0.75Ge0.25 backside removal.

Selective etching of hexagonal boron nitride by high-pressure CF4 plasma for individual one-dimensional ohmic contacts to graphene layers

We describe a technique for fabricating one-dimensional Ohmic contacts to individual graphene layers encapsulated in hexagonal boron nitride (h-BN) using CF4 and O2 plasmas. The high etch selectivity of h-BN against graphene (&amp;gt;1000) is achieved by increasing the plasma pressure, which enables etching of h-BN, while graphene acts as an etch stop to protect underlying h-BN. A low-pressure O2 plasma anisotropically etches graphene in the vertical direction, which exposes graphene edges at h-BN sidewalls. Despite the O2 plasma bombardment, the lower h-BN layer functions as an insulating layer. Thus, this method allows us to pattern metal electrodes on h-BN over a second graphene layer. Subsequent electron-beam lithography and evaporation fabricate metal contacts at the graphene edges that are active down to cryogenic temperatures. This fabrication method is demonstrated by the preparation of a graphene Hall bar with a graphite backgate and double bilayer-graphene Hall bar devices. The high flexibility of the device geometries enabled by this method creates access to a variety of experiments on electrostatically coupled graphene layers.

ZrO2 Monolayer as a Removable Etch Stop Layer for Thermal Al2O3 Atomic Layer Etching Using Hydrogen Fluoride and Trimethylaluminum

A ZrO2 monolayer was demonstrated as a removable etch stop layer (ESL) for thermal Al2O3 atomic layer etching (ALE) using HF and Al(CH3)3 (trimethylaluminum (TMA)) as the reactants. The ZrO2 ESL wa...

(Invited) Epitaxial Growth of Ge/III-V Films and Hetero-Layer Lift-off for Ultra-Thin GeOI Fabrication

Monolithic 3D (M3D) integration has been thought of as an attractive idea to realize multi-functional heterogeneous integration devices. M3D integration enables us to combine logic devices with different functional devices such as memory, sensor, or optics to create extremely compact and efficient system-on-chips. Ge and III-V compound semiconductors are expected to be implemented as high mobility channel materials and optical components which cannot be realized with Si. The layer transfer technique with low processing temperature has great potential for stacking non-lattice-matched crystalline materials for M3D ICs. Here, we discuss the layer transfer technology utilizing high quality epitaxial growth, low-temperature direct bonding and advanced epitaxial lift-off (ELO) process, which reveals the applicability of transferred layers for heterogeneous integration.The low temperature ELO process is essential for realizing reliable layer transfer with different materials because the process is almost free from the issues of thermal expansion mismatch. Process flow of GaAs or Ge layer transfer with ELO process is described in Fig. 1. First of all, a lattice-matched single crystal GaAs or Ge layer is epitaxially grown on GaAs substrate with an AlAs release layer by MOCVD. Subsequently, Al2O3 layer is deposited on the epitaxial layer by atomic layer deposition (ALD). ALD Al2O3 layer serves as the buried oxide (BOX) and the passivation layer for Ge or GaAs surface. Then, Ge or GaAs layer is patterned using photolithography. The patterned GaAs or Ge/AlAs/GaAs donor wafer is then bonded on host substrate by direct bonding technique with wet activation process. Finally, the epitaxial GaAs or Ge layer is transferred on host substrates by splitting GaAs donor wafer from AlAs layer with HCl side etching thanks to extremely high etching selectivity. Note that the fabrication of patterned transfer layer is effective in shortening the required time of ELO process. In this ELO process, the thickness of a transferred layer can be control by epitaxial layer thickness. After the layer transfer process, the released donor GaAs wafer can be reclaimed and reused for the subsequent re-epitaxial growth to reduce the process cost.Figs. 2 (a) and (b) show cross-sectional SEM and TEM images of fabricated GeOI substrate with different BOX structures. Ge pattern edge shows no peeling from SiO2(100nm)/Si substrate, indicating strong bonding strength at the pattern edge. In Fig. 2 (b), the bonding interface is clearly observed at Al2O3(5nm)/SiO2(50nm) interface formed by the wet activation process. The bonding interface exhibits very smooth and no defect. There is no observable defect in transferred Ge layer, suggesting dislocation density is below TEM detection limit. Compared to Smart-CutTM technique, ELO process has significant advantages in terms of crystal quality, thickness control and the surface flatness thanks to totally low temperature processing.To reduce wafer-scale thickness variation, etching stopper (ES) technique with high etching selectivity is quite useful. As a donor wafer, we prepare Ge active layer (20nm)/SiGe ES layer (5nm)/Ge buffer layer/AlAs/GaAs structures. Here, the SiGe layer serves as ES against the etching of Ge buffer layer to control the final GeOI thickness and attain the wafer-scale thickness uniformity. In addition, Si passivation on Ge surface was performed during initial epitaxial growth of donor wafer since Si passivation was proved to be effective in reducing interfacial trap density (D it) between Ge and oxide. After ELO process, Ge buffer layer /SiGe ES layer/Ge active layer / Al2O3 /SiO2/Si heterostructure was obtained. Then, the top Ge buffer layer was removed in HCl/H2O2 solution. We found the etching selectivity was more than 30 between Ge and SiGe layer, which is high enough to yield very smooth SiGe surface. Finally, SiGe layer was removed by TMAH preferentially.Further conformal thinning of Ge active layer was performed by the cyclic dry oxidation/wet digital etching (DE) at room temperature. In addition to thickness control with the etching rate of about 0.8 nm/cycle, it is found that dozens digital etching (DDE) process is effective for reducing Ge surface roughness. Finally, UTB GeOI substrates with high crystal quality down to 3 nm have been successfully fabricated through SiGe ES and DDE processes. Ultra-smooth GeOI surface with reduced thickness fluctuation was confirmed after DDE by TEM cross-sectional images, resulting in significant improvement of device performances. Figure 1

Fabrication of Pixelated GaAs Detectors for Ultrafast Hard X-Ray Imaging

Sandia National Laboratories is developing GaAs photodiode arrays compatible with the Ultra-Fast X-ray Imager (UXI) platform for sub-nanosecond hard x-ray diagnostics. These 25 µm pitch pixelated detector arrays are particularly useful in the diagnostics of high energy density (HED) experiments to capture spatial variations as they evolve. Existing UXI sensors consist of a backside illuminated Si detector array bonded to a read-out integrated circuit (ROIC), which offers peak sensitivity to soft (<10keV) x-rays [1]. Substituting the Si detector with materials with higher atomic numbers Z, such as GaAs and CdTe, the sensitivity of the imager can be improved for higher x-ray energies [2]. The integration of these higher Z materials at useful pixel sizes and appropriate thicknesses (10s of µm) is challenging due to less mature processing and integration techniques. Here, we report on the fabrication of small pixel arrays using epitaxially-grown GaAs p-i-n diodes, integrated onto Si fanout packages with sub-nanosecond response times.We have previously reported on discrete fast, hard x-ray GaAs detectors [3]. This paper focuses on transferring this prior work on single-element detectors to fine-pitch pixelated imaging arrays. Fabrication of the backside-illuminated detector array begins with the separate fabrication of the Si readout and GaAs detector chips, continues with In bump flip-chip bonding, and is then completed by removing the GaAs substrate and making backside contact to bias the detectors. A cross-sectional schematic of the fabricated device is given in Fig. 1.The Si fanouts were fabricated in the Sandia MESA SiFab facility. Each fanout chip has a series of 1x1 mm2 bonding sites with 25 µm pitch pixels arrays ranging in size from 3x3 to 36x36. Growth and fabrication of the GaAs detectors was carried out in the Sandia MESA MicroFab facility. Molecular beam epitaxy is used to grow a series of wafers with GaAs p-i-n diode structures on commercial n-type GaAs wafers. The epitaxial structure consists of, from the substrate up, 200 nm of undoped GaAs, 400 nm of undoped Al0.4Ga0.6As to serve as an etch stop, 1 µm of n-type GaAs, 4 to 40 µm of undoped GaAs, and 400 nm of p-type GaAs.The GaAs devices are fabricated using standard III-V semiconductor processing techniques. The bond-side (p-contact) metal contact is made with a Ti/Pt/Au metal stack. Next, the pixels are electrically isolated by wet etching through the p-GaAs and into the undoped GaAs region. A silicon nitride passivation is then deposited by PECVD and patterned to reduce dark current [3]. Finally, underbump metal and In bumps are deposited on both the Si fanout and GaAs detector chips. After In deposition, the chips are singulated and flip-chip bonded. After bonding, the parts are underfilled with a low viscosity epoxy to provide additional mechanical stability. The left chip in Fig. 2(a) shows a bonded pair after flip-chip bonding.After bonding, the GaAs substrate is removed to allow backside metallization and illumination. The bulk of the substrate is first removed by mechanical lapping to thin the detector chip from approximately 630 µm to 70 µm. Next, a selective wet etch (5:1 citric acid:H2O2) is used to uniformly etch to the stop layer. Finally, a timed wet etch is used to remove the etch stop layer and expose the backside n-contact. These thinning steps are shown in Figs. 2(a) and (b). Backside metal contacts are formed using a low-temperature process to prevent melting the In bumps [4]. After fabrication, devices are packaged onto a custom PCB designed to allow for flexible readout as shown in Fig. 2(d).Sandia National Laboratories is a multimission laboratory managed and operated by National Technology and Engineering Solutions of Sandia, LLC, a wholly owned subsidiary of Honeywell International, Inc., for the U.S. Department of Energy’s National Nuclear Security Administration under contract DE-NA-0003525. This paper describes objective technical results and analysis. Any subjective views or opinions that might be expressed in the paper do not necessarily represent the views of the U.S. Department of Energy or the United States Government.SAND2020-5273AREFERENCES[1] L. Claus, et al., “Design and characterization of an improved, 2 ns, multi-frame imager for the Ultra-Fast X-ray Imager (UXI) program at Sandia National Laboratories,” Proc. SPIE, 10390, 2017.[2] Q. Looker, et al., “Synchrotron characterization of high-Z, current-mode x-ray detectors,” Rev. Sci. Instrum. 91, 023509, 2020.[3] Q. Looker, et al., “GaAs x-ray detectors with sub-nanosecond temporal response,” Rev. Sci. Instrum. 90, 113505, 2019.[4] M. G. Wood, et al., “Formation of Ohmic contacts to n-GaAs at temperatures compatible with indium flip-chip bonding,” Proc. Electrochem. Soc., 881, 2019. Figure 1